25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips.c,v 1.34 2005/03/20 20:27:26 debug Exp $ |
* $Id: cpu_mips.c,v 1.39 2005/04/15 21:39:59 debug Exp $ |
29 |
* |
* |
30 |
* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
31 |
*/ |
*/ |
728 |
if (running) |
if (running) |
729 |
dumpaddr = cpu->pc; |
dumpaddr = cpu->pc; |
730 |
|
|
731 |
|
if ((dumpaddr & 3) != 0) |
732 |
|
printf("WARNING: Unaligned address!\n"); |
733 |
|
|
734 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
735 |
dumpaddr, &offset); |
dumpaddr, &offset); |
736 |
if (symbol != NULL && offset==0) |
if (symbol != NULL && offset==0) |
1611 |
|
|
1612 |
if (tlb && vaddr < 0x1000) { |
if (tlb && vaddr < 0x1000) { |
1613 |
uint64_t offset; |
uint64_t offset; |
1614 |
char *symbol = get_symbol_name( |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
1615 |
&cpu->machine->symbol_context, cpu->cd.mips.pc_last, &offset); |
cpu->cd.mips.pc_last, &offset); |
1616 |
fatal("warning: LOW reference vaddr=0x%08x, exception %s, pc=%08llx <%s>\n", |
fatal("[ warning: LOW reference vaddr=0x%08x, exception %s, " |
1617 |
(int)vaddr, exception_names[exccode], (long long)cpu->cd.mips.pc_last, symbol? symbol : "(no symbol)"); |
"pc=%08llx <%s> ]\n", (int)vaddr, exception_names[exccode], |
1618 |
|
(long long)cpu->cd.mips.pc_last, |
1619 |
|
symbol? symbol : "(no symbol)"); |
1620 |
} |
} |
1621 |
|
|
1622 |
/* Clear the exception code bits of the cause register... */ |
/* Clear the exception code bits of the cause register... */ |
2121 |
|
|
2122 |
|
|
2123 |
#ifdef BINTRANS |
#ifdef BINTRANS |
2124 |
/* Caches are not very coozy to handle in bintrans: */ |
if ((single_step || instruction_trace_cached) |
|
switch (cpu->cd.mips.cpu_type.mmu_model) { |
|
|
case MMU3K: |
|
|
if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) { |
|
|
/* cpu->cd.mips.dont_run_next_bintrans = 1; */ |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0 = |
|
|
cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_SWAP_CACHES? |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0_cacheisol_i |
|
|
: cpu->cd.mips.vaddr_to_hostaddr_table0_cacheisol_d; |
|
|
} else { |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0 = |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0_kernel; |
|
|
|
|
|
/* TODO: cpu->cd.mips.vaddr_to_hostaddr_table0_user; */ |
|
|
} |
|
|
break; |
|
|
default: |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0 = |
|
|
cpu->cd.mips.vaddr_to_hostaddr_table0_kernel; |
|
|
/* TODO: cpu->cd.mips.vaddr_to_hostaddr_table0_user; */ |
|
|
} |
|
|
|
|
|
if ((single_step || cpu->machine->instruction_trace) |
|
2125 |
&& cpu->machine->bintrans_enable) |
&& cpu->machine->bintrans_enable) |
2126 |
cpu->cd.mips.dont_run_next_bintrans = 1; |
cpu->cd.mips.dont_run_next_bintrans = 1; |
2127 |
#endif |
#endif |
2271 |
res &= BINTRANS_N_MASK; |
res &= BINTRANS_N_MASK; |
2272 |
|
|
2273 |
if (cpu->cd.mips.cpu_type.exc_model != EXC3K) { |
if (cpu->cd.mips.cpu_type.exc_model != EXC3K) { |
|
/* TODO: 32-bit or 64-bit? */ |
|
2274 |
int x = cp0->reg[COP0_COUNT], y = cp0->reg[COP0_COMPARE]; |
int x = cp0->reg[COP0_COUNT], y = cp0->reg[COP0_COMPARE]; |
2275 |
int diff = x - y; |
int diff = x - y; |
2276 |
if (diff < 0 && diff + (res-1) >= 0 |
if (diff < 0 && diff + (res-1) >= 0 |
3311 |
* (This cache-line was written to by |
* (This cache-line was written to by |
3312 |
* someone else.) |
* someone else.) |
3313 |
*/ |
*/ |
3314 |
if (cpu->cd.mips.rmw == 0) { |
if (cpu->cd.mips.rmw == 0 || |
3315 |
|
cpu->cd.mips.rmw_addr != addr || |
3316 |
|
cpu->cd.mips.rmw_len != wlen) { |
3317 |
/* The store failed: */ |
/* The store failed: */ |
3318 |
cpu->cd.mips.gpr[rt] = 0; |
cpu->cd.mips.gpr[rt] = 0; |
3319 |
if (instruction_trace_cached) |
if (instruction_trace_cached) |