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dpavlin |
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/* |
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* Cisco 7200 (Predator) simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#ifndef __X86_TRANS_H__ |
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#define __X86_TRANS_H__ |
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#include "utils.h" |
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#include "x86-codegen.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "cp0.h" |
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#include "mips64_exec.h" |
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#define JIT_SUPPORT 1 |
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/* Manipulate bitmasks atomically */ |
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static forced_inline void atomic_or(m_uint32_t *v,m_uint32_t m) |
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{ |
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__asm__ __volatile__("lock; orl %1,%0":"=m"(*v):"ir"(m),"m"(*v)); |
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} |
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static forced_inline void atomic_and(m_uint32_t *v,m_uint32_t m) |
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{ |
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__asm__ __volatile__("lock; andl %1,%0":"=m"(*v):"ir"(m),"m"(*v)); |
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} |
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/* Wrappers to x86-codegen functions */ |
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#define insn_block_set_patch x86_patch |
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#define insn_block_set_jump x86_jump_code |
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/* MIPS instruction array */ |
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extern struct insn_tag mips64_insn_tags[]; |
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/* Push epilog for an x86 instruction block */ |
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static forced_inline void insn_block_push_epilog(insn_block_t *block) |
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{ |
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x86_ret(block->jit_ptr); |
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} |
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/* Execute JIT code */ |
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static forced_inline |
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void insn_block_exec_jit_code(cpu_mips_t *cpu,insn_block_t *block) |
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{ |
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insn_tblock_fptr jit_code; |
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m_uint32_t offset; |
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offset = (cpu->pc & MIPS_MIN_PAGE_IMASK) >> 2; |
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jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset]; |
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if (unlikely(!jit_code)) { |
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mips64_exec_single_step(cpu,vmtoh32(block->mips_code[offset])); |
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return; |
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} |
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asm volatile ("movl %0,%%edi"::"r"(cpu): |
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"esi","edi","eax","ebx","ecx","edx"); |
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jit_code(); |
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} |
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/* Set the Pointer Counter (PC) register */ |
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void mips64_set_pc(insn_block_t *b,m_uint64_t new_pc); |
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/* Set the Return Address (RA) register */ |
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void mips64_set_ra(insn_block_t *b,m_uint64_t ret_pc); |
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/* Virtual Breakpoint */ |
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void mips64_emit_breakpoint(insn_block_t *b); |
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/* Emit unhandled instruction code */ |
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int mips64_emit_invalid_delay_slot(insn_block_t *b); |
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/* |
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* Increment count register and trigger the timer IRQ if value in compare |
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* register is the same. |
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*/ |
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void mips64_inc_cp0_count_reg(insn_block_t *b); |
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/* Increment the number of executed instructions (performance debugging) */ |
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void mips64_inc_perf_counter(insn_block_t *b); |
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#endif |