24 |
/* MTS access with special access mask */ |
/* MTS access with special access mask */ |
25 |
void mips64_access_special(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t mask, |
void mips64_access_special(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t mask, |
26 |
u_int op_code,u_int op_type,u_int op_size, |
u_int op_code,u_int op_type,u_int op_size, |
27 |
m_uint64_t *data,u_int *exc) |
m_uint64_t *data) |
28 |
{ |
{ |
29 |
switch(mask) { |
switch(mask) { |
30 |
case MTS_ACC_U: |
case MTS_ACC_U: |
31 |
|
if (op_type == MTS_READ) |
32 |
|
*data = 0; |
33 |
|
|
34 |
|
if (cpu->gen->undef_mem_handler != NULL) { |
35 |
|
if (cpu->gen->undef_mem_handler(cpu->gen,vaddr,op_size,op_type, |
36 |
|
data)) |
37 |
|
return; |
38 |
|
} |
39 |
|
|
40 |
#if DEBUG_MTS_ACC_U |
#if DEBUG_MTS_ACC_U |
41 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
42 |
cpu_log(cpu->gen, |
cpu_log(cpu->gen, |
48 |
"pc=0x%llx, value=0x%8.8llx (size=%u)\n", |
"pc=0x%llx, value=0x%8.8llx (size=%u)\n", |
49 |
vaddr,cpu->pc,*data,op_size); |
vaddr,cpu->pc,*data,op_size); |
50 |
#endif |
#endif |
|
if (op_type == MTS_READ) |
|
|
*data = 0; |
|
51 |
break; |
break; |
52 |
|
|
53 |
case MTS_ACC_T: |
case MTS_ACC_T: |
63 |
memlog_dump(cpu->gen); |
memlog_dump(cpu->gen); |
64 |
#endif |
#endif |
65 |
#endif |
#endif |
66 |
|
|
67 |
cpu->cp0.reg[MIPS_CP0_BADVADDR] = vaddr; |
cpu->cp0.reg[MIPS_CP0_BADVADDR] = vaddr; |
68 |
|
|
69 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
70 |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TLB_LOAD,0); |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TLB_LOAD,0); |
71 |
else |
else |
72 |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TLB_SAVE,0); |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TLB_SAVE,0); |
73 |
|
|
74 |
|
cpu_exec_loop_enter(cpu->gen); |
75 |
} |
} |
|
|
|
|
*exc = 1; |
|
76 |
break; |
break; |
77 |
|
|
78 |
case MTS_ACC_AE: |
case MTS_ACC_AE: |
89 |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_ADDR_LOAD,0); |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_ADDR_LOAD,0); |
90 |
else |
else |
91 |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_ADDR_SAVE,0); |
mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_ADDR_SAVE,0); |
|
} |
|
92 |
|
|
93 |
*exc = 1; |
cpu_exec_loop_enter(cpu->gen); |
94 |
|
} |
95 |
break; |
break; |
96 |
} |
} |
97 |
} |
} |
121 |
mips64_mts64_slow_lookup(cpu_mips_t *cpu,m_uint64_t vaddr, |
mips64_mts64_slow_lookup(cpu_mips_t *cpu,m_uint64_t vaddr, |
122 |
u_int op_code,u_int op_size, |
u_int op_code,u_int op_size, |
123 |
u_int op_type,m_uint64_t *data, |
u_int op_type,m_uint64_t *data, |
124 |
u_int *exc,mts64_entry_t *alt_entry) |
mts64_entry_t *alt_entry) |
125 |
{ |
{ |
126 |
m_uint32_t hash_bucket,zone,sub_zone,cca; |
m_uint32_t hash_bucket,zone,sub_zone,cca; |
127 |
mts64_entry_t *entry; |
mts64_entry_t *entry; |
156 |
case 0x7fc: /* ckseg0 */ |
case 0x7fc: /* ckseg0 */ |
157 |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
158 |
map.paddr = map.vaddr - 0xFFFFFFFF80000000ULL; |
map.paddr = map.vaddr - 0xFFFFFFFF80000000ULL; |
159 |
|
map.offset = vaddr & MIPS_MIN_PAGE_IMASK; |
160 |
map.cached = TRUE; |
map.cached = TRUE; |
161 |
|
|
162 |
if (!(entry = mips64_mts64_map(cpu,op_type,&map, |
if (!(entry = mips64_mts64_map(cpu,op_type,&map, |
168 |
case 0x7fd: /* ckseg1 */ |
case 0x7fd: /* ckseg1 */ |
169 |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
170 |
map.paddr = map.vaddr - 0xFFFFFFFFA0000000ULL; |
map.paddr = map.vaddr - 0xFFFFFFFFA0000000ULL; |
171 |
|
map.offset = vaddr & MIPS_MIN_PAGE_IMASK; |
172 |
map.cached = FALSE; |
map.cached = FALSE; |
173 |
|
|
174 |
if (!(entry = mips64_mts64_map(cpu,op_type,&map, |
if (!(entry = mips64_mts64_map(cpu,op_type,&map, |
209 |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
210 |
map.paddr = (vaddr & MIPS64_XKPHYS_PHYS_MASK); |
map.paddr = (vaddr & MIPS64_XKPHYS_PHYS_MASK); |
211 |
map.paddr &= MIPS_MIN_PAGE_MASK; |
map.paddr &= MIPS_MIN_PAGE_MASK; |
212 |
|
map.offset = vaddr & MIPS_MIN_PAGE_IMASK; |
213 |
|
|
214 |
if (!(entry = mips64_mts64_map(cpu,op_type,&map,entry,alt_entry))) |
if (!(entry = mips64_mts64_map(cpu,op_type,&map,entry,alt_entry))) |
215 |
goto err_undef; |
goto err_undef; |
222 |
} |
} |
223 |
|
|
224 |
err_undef: |
err_undef: |
225 |
mips64_access_special(cpu,vaddr,MTS_ACC_U,op_code,op_type,op_size,data,exc); |
mips64_access_special(cpu,vaddr,MTS_ACC_U,op_code,op_type,op_size,data); |
226 |
return NULL; |
return NULL; |
227 |
err_address: |
err_address: |
228 |
mips64_access_special(cpu,vaddr,MTS_ACC_AE,op_code,op_type,op_size, |
mips64_access_special(cpu,vaddr,MTS_ACC_AE,op_code,op_type,op_size,data); |
|
data,exc); |
|
229 |
return NULL; |
return NULL; |
230 |
err_tlb: |
err_tlb: |
231 |
mips64_access_special(cpu,vaddr,MTS_ACC_T,op_code,op_type,op_size,data,exc); |
mips64_access_special(cpu,vaddr,MTS_ACC_T,op_code,op_type,op_size,data); |
232 |
return NULL; |
return NULL; |
233 |
} |
} |
234 |
|
|
236 |
static forced_inline |
static forced_inline |
237 |
void *mips64_mts64_access(cpu_mips_t *cpu,m_uint64_t vaddr, |
void *mips64_mts64_access(cpu_mips_t *cpu,m_uint64_t vaddr, |
238 |
u_int op_code,u_int op_size, |
u_int op_code,u_int op_size, |
239 |
u_int op_type,m_uint64_t *data, |
u_int op_type,m_uint64_t *data) |
|
u_int *exc) |
|
240 |
{ |
{ |
241 |
mts64_entry_t *entry,alt_entry; |
mts64_entry_t *entry,alt_entry; |
242 |
m_uint32_t hash_bucket; |
m_uint32_t hash_bucket; |
249 |
memlog_rec_access(cpu->gen,vaddr,*data,op_size,op_type); |
memlog_rec_access(cpu->gen,vaddr,*data,op_size,op_type); |
250 |
#endif |
#endif |
251 |
|
|
|
*exc = 0; |
|
252 |
hash_bucket = MTS64_HASH(vaddr); |
hash_bucket = MTS64_HASH(vaddr); |
253 |
entry = &cpu->mts_u.mts64_cache[hash_bucket]; |
entry = &cpu->mts_u.mts64_cache[hash_bucket]; |
254 |
|
|
262 |
/* Slow lookup if nothing found in cache */ |
/* Slow lookup if nothing found in cache */ |
263 |
if (unlikely(((vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa) || cow)) { |
if (unlikely(((vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa) || cow)) { |
264 |
entry = mips64_mts64_slow_lookup(cpu,vaddr,op_code,op_size,op_type, |
entry = mips64_mts64_slow_lookup(cpu,vaddr,op_code,op_size,op_type, |
265 |
data,exc,&alt_entry); |
data,&alt_entry); |
266 |
if (!entry) |
if (!entry) |
267 |
return NULL; |
return NULL; |
268 |
|
|
269 |
if (entry->flags & MTS_FLAG_DEV) { |
if (entry->flags & MTS_FLAG_DEV) { |
270 |
dev_id = (entry->hpa & MTS_DEVID_MASK) >> MTS_DEVID_SHIFT; |
dev_id = (entry->hpa & MTS_DEVID_MASK) >> MTS_DEVID_SHIFT; |
271 |
haddr = entry->hpa & MTS_DEVOFF_MASK; |
haddr = entry->hpa & MTS_DEVOFF_MASK; |
|
haddr += vaddr - entry->gvpa; |
|
272 |
return(dev_access_fast(cpu->gen,dev_id,haddr,op_size,op_type,data)); |
return(dev_access_fast(cpu->gen,dev_id,haddr,op_size,op_type,data)); |
273 |
} |
} |
274 |
} |
} |
288 |
mts64_entry_t *entry,alt_entry; |
mts64_entry_t *entry,alt_entry; |
289 |
m_uint32_t hash_bucket; |
m_uint32_t hash_bucket; |
290 |
m_uint64_t data = 0; |
m_uint64_t data = 0; |
|
u_int exc = 0; |
|
291 |
|
|
292 |
hash_bucket = MTS64_HASH(vaddr); |
hash_bucket = MTS64_HASH(vaddr); |
293 |
entry = &cpu->mts_u.mts64_cache[hash_bucket]; |
entry = &cpu->mts_u.mts64_cache[hash_bucket]; |
295 |
/* Slow lookup if nothing found in cache */ |
/* Slow lookup if nothing found in cache */ |
296 |
if (unlikely((vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa)) { |
if (unlikely((vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa)) { |
297 |
entry = mips64_mts64_slow_lookup(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ, |
entry = mips64_mts64_slow_lookup(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ, |
298 |
&data,&exc,&alt_entry); |
&data,&alt_entry); |
299 |
if (!entry) |
if (!entry) |
300 |
return(-1); |
return(-1); |
301 |
} |
} |
311 |
mips64_mts32_slow_lookup(cpu_mips_t *cpu,m_uint64_t vaddr, |
mips64_mts32_slow_lookup(cpu_mips_t *cpu,m_uint64_t vaddr, |
312 |
u_int op_code,u_int op_size, |
u_int op_code,u_int op_size, |
313 |
u_int op_type,m_uint64_t *data, |
u_int op_type,m_uint64_t *data, |
314 |
u_int *exc,mts32_entry_t *alt_entry) |
mts32_entry_t *alt_entry) |
315 |
{ |
{ |
316 |
m_uint32_t hash_bucket,zone; |
m_uint32_t hash_bucket,zone; |
317 |
mts32_entry_t *entry; |
mts32_entry_t *entry; |
340 |
case 0x04: /* kseg0 */ |
case 0x04: /* kseg0 */ |
341 |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
342 |
map.paddr = map.vaddr - 0xFFFFFFFF80000000ULL; |
map.paddr = map.vaddr - 0xFFFFFFFF80000000ULL; |
343 |
|
map.offset = vaddr & MIPS_MIN_PAGE_IMASK; |
344 |
map.cached = TRUE; |
map.cached = TRUE; |
345 |
|
|
346 |
if (!(entry = mips64_mts32_map(cpu,op_type,&map,entry,alt_entry))) |
if (!(entry = mips64_mts32_map(cpu,op_type,&map,entry,alt_entry))) |
351 |
case 0x05: /* kseg1 */ |
case 0x05: /* kseg1 */ |
352 |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
map.vaddr = vaddr & MIPS_MIN_PAGE_MASK; |
353 |
map.paddr = map.vaddr - 0xFFFFFFFFA0000000ULL; |
map.paddr = map.vaddr - 0xFFFFFFFFA0000000ULL; |
354 |
|
map.offset = vaddr & MIPS_MIN_PAGE_IMASK; |
355 |
map.cached = FALSE; |
map.cached = FALSE; |
356 |
|
|
357 |
if (!(entry = mips64_mts32_map(cpu,op_type,&map,entry,alt_entry))) |
if (!(entry = mips64_mts32_map(cpu,op_type,&map,entry,alt_entry))) |
372 |
} |
} |
373 |
|
|
374 |
err_undef: |
err_undef: |
375 |
mips64_access_special(cpu,vaddr,MTS_ACC_U,op_code,op_type,op_size,data,exc); |
mips64_access_special(cpu,vaddr,MTS_ACC_U,op_code,op_type,op_size,data); |
376 |
return NULL; |
return NULL; |
377 |
err_address: |
err_address: |
378 |
mips64_access_special(cpu,vaddr,MTS_ACC_AE,op_code,op_type,op_size, |
mips64_access_special(cpu,vaddr,MTS_ACC_AE,op_code,op_type,op_size,data); |
|
data,exc); |
|
379 |
return NULL; |
return NULL; |
380 |
err_tlb: |
err_tlb: |
381 |
mips64_access_special(cpu,vaddr,MTS_ACC_T,op_code,op_type,op_size,data,exc); |
mips64_access_special(cpu,vaddr,MTS_ACC_T,op_code,op_type,op_size,data); |
382 |
return NULL; |
return NULL; |
383 |
} |
} |
384 |
|
|
386 |
static forced_inline |
static forced_inline |
387 |
void *mips64_mts32_access(cpu_mips_t *cpu,m_uint64_t vaddr, |
void *mips64_mts32_access(cpu_mips_t *cpu,m_uint64_t vaddr, |
388 |
u_int op_code,u_int op_size, |
u_int op_code,u_int op_size, |
389 |
u_int op_type,m_uint64_t *data, |
u_int op_type,m_uint64_t *data) |
|
u_int *exc) |
|
390 |
{ |
{ |
391 |
mts32_entry_t *entry,alt_entry; |
mts32_entry_t *entry,alt_entry; |
392 |
m_uint32_t hash_bucket; |
m_uint32_t hash_bucket; |
399 |
memlog_rec_access(cpu->gen,vaddr,*data,op_size,op_type); |
memlog_rec_access(cpu->gen,vaddr,*data,op_size,op_type); |
400 |
#endif |
#endif |
401 |
|
|
|
*exc = 0; |
|
402 |
hash_bucket = MTS32_HASH(vaddr); |
hash_bucket = MTS32_HASH(vaddr); |
403 |
entry = &cpu->mts_u.mts32_cache[hash_bucket]; |
entry = &cpu->mts_u.mts32_cache[hash_bucket]; |
404 |
|
|
414 |
cow)) |
cow)) |
415 |
{ |
{ |
416 |
entry = mips64_mts32_slow_lookup(cpu,vaddr,op_code,op_size,op_type, |
entry = mips64_mts32_slow_lookup(cpu,vaddr,op_code,op_size,op_type, |
417 |
data,exc,&alt_entry); |
data,&alt_entry); |
418 |
if (!entry) |
if (!entry) |
419 |
return NULL; |
return NULL; |
420 |
|
|
421 |
if (entry->flags & MTS_FLAG_DEV) { |
if (entry->flags & MTS_FLAG_DEV) { |
422 |
dev_id = (entry->hpa & MTS_DEVID_MASK) >> MTS_DEVID_SHIFT; |
dev_id = (entry->hpa & MTS_DEVID_MASK) >> MTS_DEVID_SHIFT; |
423 |
haddr = entry->hpa & MTS_DEVOFF_MASK; |
haddr = entry->hpa & MTS_DEVOFF_MASK; |
|
haddr += vaddr - entry->gvpa; |
|
424 |
return(dev_access_fast(cpu->gen,dev_id,haddr,op_size,op_type,data)); |
return(dev_access_fast(cpu->gen,dev_id,haddr,op_size,op_type,data)); |
425 |
} |
} |
426 |
} |
} |
440 |
mts32_entry_t *entry,alt_entry; |
mts32_entry_t *entry,alt_entry; |
441 |
m_uint32_t hash_bucket; |
m_uint32_t hash_bucket; |
442 |
m_uint64_t data = 0; |
m_uint64_t data = 0; |
|
u_int exc = 0; |
|
443 |
|
|
444 |
hash_bucket = MTS32_HASH(vaddr); |
hash_bucket = MTS32_HASH(vaddr); |
445 |
entry = &cpu->mts_u.mts32_cache[hash_bucket]; |
entry = &cpu->mts_u.mts32_cache[hash_bucket]; |
447 |
/* Slow lookup if nothing found in cache */ |
/* Slow lookup if nothing found in cache */ |
448 |
if (unlikely(((m_uint32_t)vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa)) { |
if (unlikely(((m_uint32_t)vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa)) { |
449 |
entry = mips64_mts32_slow_lookup(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ, |
entry = mips64_mts32_slow_lookup(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ, |
450 |
&data,&exc,&alt_entry); |
&data,&alt_entry); |
451 |
if (!entry) |
if (!entry) |
452 |
return(-1); |
return(-1); |
453 |
} |
} |