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dpavlin |
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/* |
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dpavlin |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* MIPS64 Step-by-step execution. |
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*/ |
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#if __GNUC__ > 2 |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <unistd.h> |
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#include <string.h> |
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#include <sys/types.h> |
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#include <sys/stat.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include "cpu.h" |
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#include "vm.h" |
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#include "mips64_exec.h" |
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#include "memory.h" |
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#include "insn_lookup.h" |
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#include "dynamips.h" |
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/* Forward declaration of instruction array */ |
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static struct mips64_insn_exec_tag mips64_exec_tags[]; |
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static insn_lookup_t *ilt = NULL; |
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/* ILT */ |
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static forced_inline void *mips64_exec_get_insn(int index) |
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{ |
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return(&mips64_exec_tags[index]); |
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} |
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static int mips64_exec_chk_lo(struct mips64_insn_exec_tag *tag,int value) |
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{ |
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return((value & tag->mask) == (tag->value & 0xFFFF)); |
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} |
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static int mips64_exec_chk_hi(struct mips64_insn_exec_tag *tag,int value) |
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{ |
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return((value & (tag->mask >> 16)) == (tag->value >> 16)); |
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} |
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/* Initialize instruction lookup table */ |
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void mips64_exec_create_ilt(void) |
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{ |
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int i,count; |
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for(i=0,count=0;mips64_exec_tags[i].exec;i++) |
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count++; |
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ilt = ilt_create("mips64e",count, |
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(ilt_get_insn_cbk_t)mips64_exec_get_insn, |
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(ilt_check_cbk_t)mips64_exec_chk_lo, |
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(ilt_check_cbk_t)mips64_exec_chk_hi); |
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} |
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/* Dump statistics */ |
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void mips64_dump_stats(cpu_mips_t *cpu) |
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{ |
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int i; |
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#if NJM_STATS_ENABLE |
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printf("\n"); |
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for(i=0;mips64_exec_tags[i].exec;i++) |
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printf(" * %-10s : %10llu\n", |
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mips64_exec_tags[i].name,mips64_exec_tags[i].count); |
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printf("%llu instructions executed since startup.\n",cpu->insn_exec_count); |
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#else |
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printf("Statistics support is not compiled in.\n"); |
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#endif |
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} |
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/* Dump an instruction */ |
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int mips64_dump_insn(char *buffer,size_t buf_size,size_t insn_name_size, |
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m_uint64_t pc,mips_insn_t instruction) |
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{ |
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char insn_name[64],insn_format[32],*name; |
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int base,rs,rd,rt,sa,offset,imm; |
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struct mips64_insn_exec_tag *tag; |
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m_uint64_t new_pc; |
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int index; |
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/* Lookup for instruction */ |
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index = ilt_lookup(ilt,instruction); |
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tag = mips64_exec_get_insn(index); |
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if (!tag) { |
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snprintf(buffer,buf_size,"%8.8x (unknown)",instruction); |
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return(-1); |
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} |
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if (!(name = tag->name)) |
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name = "[unknown]"; |
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if (!insn_name_size) |
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insn_name_size = 10; |
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snprintf(insn_format,sizeof(insn_format),"%%-%lus",(u_long)insn_name_size); |
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snprintf(insn_name,sizeof(insn_name),insn_format,name); |
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switch(tag->instr_type) { |
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case 1: /* instructions without operands */ |
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snprintf(buffer,buf_size,"%8.8x %s",instruction,insn_name); |
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break; |
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case 2: /* load/store instructions */ |
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base = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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offset = (m_int16_t)bits(instruction,0,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%d(%s)", |
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instruction,insn_name,mips64_gpr_reg_names[rt], |
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offset,mips64_gpr_reg_names[base]); |
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break; |
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case 3: /* GPR[rd] = GPR[rs] op GPR[rt] */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,%s", |
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instruction,insn_name,mips64_gpr_reg_names[rd], |
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mips64_gpr_reg_names[rs],mips64_gpr_reg_names[rt]); |
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break; |
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case 4: /* GPR[rd] = GPR[rt] op GPR[rs] */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,%s", |
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instruction,insn_name,mips64_gpr_reg_names[rd], |
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mips64_gpr_reg_names[rt],mips64_gpr_reg_names[rs]); |
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break; |
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case 5: /* GPR[rt] = GPR[rs] op immediate (hex) */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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imm = bits(instruction,0,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,0x%x", |
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instruction,insn_name,mips64_gpr_reg_names[rt], |
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mips64_gpr_reg_names[rs],imm); |
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break; |
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case 6: /* GPR[rt] = GPR[rs] op immediate (dec) */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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imm = bits(instruction,0,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,%d", |
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instruction,insn_name,mips64_gpr_reg_names[rt], |
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mips64_gpr_reg_names[rs],(m_int16_t)imm); |
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break; |
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case 7: /* GPR[rd] = GPR[rt] op sa */ |
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rt = bits(instruction,16,20); |
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rd = bits(instruction,11,15); |
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sa = bits(instruction,6,10); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,%d", |
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instruction,insn_name,mips64_gpr_reg_names[rd], |
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mips64_gpr_reg_names[rt],sa); |
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break; |
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case 8: /* Branch with: GPR[rs] / GPR[rt] / offset */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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offset = bits(instruction,0,15); |
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new_pc = (pc + 4) + sign_extend(offset << 2,18); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s,0x%llx", |
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instruction,insn_name,mips64_gpr_reg_names[rs], |
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mips64_gpr_reg_names[rt],new_pc); |
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break; |
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case 9: /* Branch with: GPR[rs] / offset */ |
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rs = bits(instruction,21,25); |
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offset = bits(instruction,0,15); |
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new_pc = (pc + 4) + sign_extend(offset << 2,18); |
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snprintf(buffer,buf_size,"%8.8x %s %s,0x%llx", |
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instruction,insn_name,mips64_gpr_reg_names[rs],new_pc); |
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break; |
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case 10: /* Branch with: offset */ |
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offset = bits(instruction,0,15); |
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new_pc = (pc + 4) + sign_extend(offset << 2,18); |
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snprintf(buffer,buf_size,"%8.8x %s 0x%llx", |
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instruction,insn_name,new_pc); |
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break; |
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case 11: /* Jump */ |
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offset = bits(instruction,0,25); |
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new_pc = (pc & ~((1 << 28) - 1)) | (offset << 2); |
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snprintf(buffer,buf_size,"%8.8x %s 0x%llx", |
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instruction,insn_name,new_pc); |
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break; |
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case 13: /* op GPR[rs] */ |
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rs = bits(instruction,21,25); |
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snprintf(buffer,buf_size,"%8.8x %s %s", |
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instruction,insn_name,mips64_gpr_reg_names[rs]); |
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break; |
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case 14: /* op GPR[rd] */ |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s", |
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instruction,insn_name,mips64_gpr_reg_names[rd]); |
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break; |
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case 15: /* op GPR[rd], GPR[rs] */ |
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rs = bits(instruction,21,25); |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s", |
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instruction,insn_name,mips64_gpr_reg_names[rd], |
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mips64_gpr_reg_names[rs]); |
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break; |
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case 16: /* op GPR[rt], imm */ |
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rt = bits(instruction,16,20); |
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imm = bits(instruction,0,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,0x%x", |
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instruction,insn_name,mips64_gpr_reg_names[rt],imm); |
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break; |
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case 17: /* op GPR[rs], GPR[rt] */ |
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rs = bits(instruction,21,25); |
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rt = bits(instruction,16,20); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s", |
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instruction,insn_name,mips64_gpr_reg_names[rs], |
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mips64_gpr_reg_names[rt]); |
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break; |
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case 18: /* op GPR[rt], CP0[rd] */ |
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rt = bits(instruction,16,20); |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,%s", |
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instruction,insn_name,mips64_gpr_reg_names[rt], |
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mips64_cp0_reg_names[rd]); |
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break; |
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case 19: /* op GPR[rt], $rd */ |
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rt = bits(instruction,16,20); |
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rd = bits(instruction,11,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,$%d", |
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instruction,insn_name,mips64_gpr_reg_names[rt],rd); |
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break; |
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case 20: /* op GPR[rs], imm */ |
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rs = bits(instruction,21,25); |
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imm = bits(instruction,0,15); |
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snprintf(buffer,buf_size,"%8.8x %s %s,0x%x", |
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instruction,insn_name,mips64_gpr_reg_names[rs],imm); |
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break; |
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default: |
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snprintf(buffer,buf_size,"%8.8x %s (TO DEFINE - %d)", |
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instruction,insn_name,tag->instr_type); |
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return(-1); |
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} |
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return(0); |
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} |
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/* Dump an instruction block */ |
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void mips64_dump_insn_block(cpu_mips_t *cpu,m_uint64_t pc,u_int count, |
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size_t insn_name_size) |
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{ |
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mips_insn_t *ptr,insn; |
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char buffer[80]; |
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int i; |
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for(i=0;i<count;i++) { |
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ptr = cpu->mem_op_lookup(cpu,pc); |
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insn = vmtoh32(*ptr); |
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mips64_dump_insn(buffer,sizeof(buffer),insn_name_size,pc,insn); |
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printf("0x%llx: %s\n",pc,buffer); |
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pc += sizeof(mips_insn_t); |
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} |
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} |
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/* Execute a memory operation */ |
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static forced_inline int mips64_exec_memop(cpu_mips_t *cpu,int memop, |
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m_uint64_t vaddr,u_int dst_reg, |
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int keep_ll_bit) |
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{ |
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fastcall mips_memop_fn fn; |
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if (!keep_ll_bit) cpu->ll_bit = 0; |
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fn = cpu->mem_op_fn[memop]; |
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return(fn(cpu,vaddr,dst_reg)); |
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} |
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293 |
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/* Execute a memory operation (2) */ |
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static forced_inline int mips64_exec_memop2(cpu_mips_t *cpu,int memop, |
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m_uint64_t base,int offset, |
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u_int dst_reg,int keep_ll_bit) |
297 |
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{ |
298 |
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m_uint64_t vaddr = cpu->gpr[base] + sign_extend(offset,16); |
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fastcall mips_memop_fn fn; |
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301 |
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if (!keep_ll_bit) cpu->ll_bit = 0; |
302 |
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fn = cpu->mem_op_fn[memop]; |
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return(fn(cpu,vaddr,dst_reg)); |
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} |
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306 |
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/* Fetch an instruction */ |
307 |
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static forced_inline int mips64_exec_fetch(cpu_mips_t *cpu,m_uint64_t pc, |
308 |
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mips_insn_t *insn) |
309 |
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{ |
310 |
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m_uint64_t exec_page; |
311 |
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m_uint32_t offset; |
312 |
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313 |
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exec_page = pc & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; |
314 |
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315 |
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if (unlikely(exec_page != cpu->njm_exec_page)) { |
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cpu->njm_exec_page = exec_page; |
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cpu->njm_exec_ptr = cpu->mem_op_lookup(cpu,exec_page); |
318 |
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} |
319 |
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320 |
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offset = (pc & MIPS_MIN_PAGE_IMASK) >> 2; |
321 |
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*insn = vmtoh32(cpu->njm_exec_ptr[offset]); |
322 |
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return(0); |
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} |
324 |
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325 |
dpavlin |
8 |
/* Unknown opcode */ |
326 |
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static fastcall int mips64_exec_unknown(cpu_mips_t *cpu,mips_insn_t insn) |
327 |
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{ |
328 |
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printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n",insn,cpu->pc); |
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mips64_dump_regs(cpu->gen); |
330 |
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return(0); |
331 |
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} |
332 |
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333 |
dpavlin |
1 |
/* Execute a single instruction */ |
334 |
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static forced_inline int |
335 |
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mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction) |
336 |
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{ |
337 |
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register fastcall int (*exec)(cpu_mips_t *,mips_insn_t) = NULL; |
338 |
dpavlin |
7 |
struct mips64_insn_exec_tag *tag; |
339 |
dpavlin |
1 |
int index; |
340 |
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|
341 |
dpavlin |
7 |
#if DEBUG_INSN_PERF_CNT |
342 |
dpavlin |
1 |
cpu->perf_counter++; |
343 |
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#endif |
344 |
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345 |
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/* Increment CP0 count register */ |
346 |
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mips64_exec_inc_cp0_cnt(cpu); |
347 |
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348 |
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/* Lookup for instruction */ |
349 |
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index = ilt_lookup(ilt,instruction); |
350 |
|
|
tag = mips64_exec_get_insn(index); |
351 |
|
|
exec = tag->exec; |
352 |
|
|
|
353 |
|
|
#if NJM_STATS_ENABLE |
354 |
dpavlin |
8 |
cpu->insn_exec_count++; |
355 |
|
|
mips64_exec_tags[index].count++; |
356 |
dpavlin |
1 |
#endif |
357 |
|
|
#if 0 |
358 |
|
|
{ |
359 |
|
|
char buffer[80]; |
360 |
|
|
|
361 |
|
|
if (mips64_dump_insn(buffer,sizeof(buffer),0,cpu->pc,instruction)!=-1) |
362 |
|
|
fprintf(log_file,"0x%llx: %s\n",cpu->pc,buffer); |
363 |
|
|
} |
364 |
|
|
#endif |
365 |
|
|
|
366 |
dpavlin |
8 |
return(exec(cpu,instruction)); |
367 |
dpavlin |
1 |
} |
368 |
|
|
|
369 |
|
|
/* Single-step execution */ |
370 |
dpavlin |
7 |
fastcall void mips64_exec_single_step(cpu_mips_t *cpu,mips_insn_t instruction) |
371 |
dpavlin |
1 |
{ |
372 |
|
|
int res; |
373 |
|
|
|
374 |
|
|
res = mips64_exec_single_instruction(cpu,instruction); |
375 |
|
|
|
376 |
|
|
/* Normal flow ? */ |
377 |
|
|
if (likely(!res)) cpu->pc += 4; |
378 |
|
|
} |
379 |
|
|
|
380 |
|
|
/* Run MIPS code in step-by-step mode */ |
381 |
dpavlin |
7 |
void *mips64_exec_run_cpu(cpu_gen_t *gen) |
382 |
dpavlin |
1 |
{ |
383 |
dpavlin |
7 |
cpu_mips_t *cpu = CPU_MIPS64(gen); |
384 |
dpavlin |
1 |
pthread_t timer_irq_thread; |
385 |
dpavlin |
7 |
int timer_irq_check = 0; |
386 |
dpavlin |
1 |
mips_insn_t insn; |
387 |
|
|
int res; |
388 |
|
|
|
389 |
|
|
if (pthread_create(&timer_irq_thread,NULL, |
390 |
|
|
(void *)mips64_timer_irq_run,cpu)) |
391 |
|
|
{ |
392 |
|
|
fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n", |
393 |
dpavlin |
7 |
cpu->vm->name,gen->id); |
394 |
|
|
cpu_stop(gen); |
395 |
dpavlin |
1 |
return NULL; |
396 |
|
|
} |
397 |
|
|
|
398 |
dpavlin |
7 |
gen->cpu_thread_running = TRUE; |
399 |
dpavlin |
3 |
|
400 |
dpavlin |
1 |
start_cpu: |
401 |
dpavlin |
7 |
gen->idle_count = 0; |
402 |
dpavlin |
3 |
|
403 |
dpavlin |
1 |
for(;;) { |
404 |
dpavlin |
7 |
if (unlikely(gen->state != CPU_STATE_RUNNING)) |
405 |
dpavlin |
1 |
break; |
406 |
|
|
|
407 |
|
|
/* Handle virtual idle loop */ |
408 |
|
|
if (unlikely(cpu->pc == cpu->idle_pc)) { |
409 |
dpavlin |
7 |
if (++gen->idle_count == gen->idle_max) { |
410 |
|
|
cpu_idle_loop(gen); |
411 |
|
|
gen->idle_count = 0; |
412 |
dpavlin |
1 |
} |
413 |
|
|
} |
414 |
|
|
|
415 |
|
|
/* Handle the virtual CPU clock */ |
416 |
|
|
if (++timer_irq_check == cpu->timer_irq_check_itv) { |
417 |
|
|
timer_irq_check = 0; |
418 |
|
|
|
419 |
|
|
if (cpu->timer_irq_pending && !cpu->irq_disable) { |
420 |
|
|
mips64_trigger_timer_irq(cpu); |
421 |
|
|
mips64_trigger_irq(cpu); |
422 |
|
|
cpu->timer_irq_pending--; |
423 |
|
|
} |
424 |
|
|
} |
425 |
|
|
|
426 |
|
|
/* Reset "zero register" (for safety) */ |
427 |
|
|
cpu->gpr[0] = 0; |
428 |
|
|
|
429 |
|
|
/* Check IRQ */ |
430 |
|
|
if (unlikely(cpu->irq_pending)) { |
431 |
|
|
mips64_trigger_irq(cpu); |
432 |
|
|
continue; |
433 |
|
|
} |
434 |
|
|
|
435 |
|
|
/* Fetch and execute the instruction */ |
436 |
|
|
mips64_exec_fetch(cpu,cpu->pc,&insn); |
437 |
|
|
res = mips64_exec_single_instruction(cpu,insn); |
438 |
|
|
|
439 |
|
|
/* Normal flow ? */ |
440 |
dpavlin |
7 |
if (likely(!res)) cpu->pc += sizeof(mips_insn_t); |
441 |
dpavlin |
1 |
} |
442 |
|
|
|
443 |
|
|
if (!cpu->pc) { |
444 |
dpavlin |
7 |
cpu_stop(gen); |
445 |
|
|
cpu_log(gen,"SLOW_EXEC","PC=0, halting CPU.\n"); |
446 |
dpavlin |
1 |
} |
447 |
|
|
|
448 |
|
|
/* Check regularly if the CPU has been restarted */ |
449 |
dpavlin |
7 |
while(gen->cpu_thread_running) { |
450 |
|
|
gen->seq_state++; |
451 |
dpavlin |
1 |
|
452 |
dpavlin |
7 |
switch(gen->state) { |
453 |
|
|
case CPU_STATE_RUNNING: |
454 |
|
|
gen->state = CPU_STATE_RUNNING; |
455 |
dpavlin |
1 |
goto start_cpu; |
456 |
|
|
|
457 |
dpavlin |
7 |
case CPU_STATE_HALTED: |
458 |
|
|
gen->cpu_thread_running = FALSE; |
459 |
dpavlin |
1 |
pthread_join(timer_irq_thread,NULL); |
460 |
|
|
break; |
461 |
|
|
} |
462 |
|
|
|
463 |
|
|
/* CPU is paused */ |
464 |
|
|
usleep(200000); |
465 |
|
|
} |
466 |
|
|
|
467 |
|
|
return NULL; |
468 |
|
|
} |
469 |
|
|
|
470 |
|
|
/* Execute the instruction in delay slot */ |
471 |
|
|
static forced_inline void mips64_exec_bdslot(cpu_mips_t *cpu) |
472 |
|
|
{ |
473 |
|
|
mips_insn_t insn; |
474 |
|
|
|
475 |
|
|
/* Fetch the instruction in delay slot */ |
476 |
|
|
mips64_exec_fetch(cpu,cpu->pc+4,&insn); |
477 |
|
|
|
478 |
|
|
/* Execute the instruction */ |
479 |
|
|
mips64_exec_single_instruction(cpu,insn); |
480 |
|
|
} |
481 |
|
|
|
482 |
|
|
/* ADD */ |
483 |
|
|
static fastcall int mips64_exec_ADD(cpu_mips_t *cpu,mips_insn_t insn) |
484 |
|
|
{ |
485 |
|
|
int rs = bits(insn,21,25); |
486 |
|
|
int rt = bits(insn,16,20); |
487 |
|
|
int rd = bits(insn,11,15); |
488 |
|
|
m_uint64_t res; |
489 |
|
|
|
490 |
|
|
/* TODO: Exception handling */ |
491 |
|
|
res = (m_uint32_t)cpu->gpr[rs] + (m_uint32_t)cpu->gpr[rt]; |
492 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
493 |
|
|
return(0); |
494 |
|
|
} |
495 |
|
|
|
496 |
|
|
/* ADDI */ |
497 |
|
|
static fastcall int mips64_exec_ADDI(cpu_mips_t *cpu,mips_insn_t insn) |
498 |
|
|
{ |
499 |
|
|
int rs = bits(insn,21,25); |
500 |
|
|
int rt = bits(insn,16,20); |
501 |
|
|
int imm = bits(insn,0,15); |
502 |
|
|
m_uint32_t res,val = sign_extend(imm,16); |
503 |
|
|
|
504 |
|
|
/* TODO: Exception handling */ |
505 |
|
|
res = (m_uint32_t)cpu->gpr[rs] + val; |
506 |
|
|
cpu->gpr[rt] = sign_extend(res,32); |
507 |
|
|
return(0); |
508 |
|
|
} |
509 |
|
|
|
510 |
|
|
/* ADDIU */ |
511 |
|
|
static fastcall int mips64_exec_ADDIU(cpu_mips_t *cpu,mips_insn_t insn) |
512 |
|
|
{ |
513 |
|
|
int rs = bits(insn,21,25); |
514 |
|
|
int rt = bits(insn,16,20); |
515 |
|
|
int imm = bits(insn,0,15); |
516 |
|
|
m_uint32_t res,val = sign_extend(imm,16); |
517 |
|
|
|
518 |
|
|
res = (m_uint32_t)cpu->gpr[rs] + val; |
519 |
|
|
cpu->gpr[rt] = sign_extend(res,32); |
520 |
|
|
return(0); |
521 |
|
|
} |
522 |
|
|
|
523 |
|
|
/* ADDU */ |
524 |
|
|
static fastcall int mips64_exec_ADDU(cpu_mips_t *cpu,mips_insn_t insn) |
525 |
|
|
{ |
526 |
|
|
int rs = bits(insn,21,25); |
527 |
|
|
int rt = bits(insn,16,20); |
528 |
|
|
int rd = bits(insn,11,15); |
529 |
|
|
m_uint32_t res; |
530 |
|
|
|
531 |
|
|
res = (m_uint32_t)cpu->gpr[rs] + (m_uint32_t)cpu->gpr[rt]; |
532 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
533 |
|
|
return(0); |
534 |
|
|
} |
535 |
|
|
|
536 |
|
|
/* AND */ |
537 |
|
|
static fastcall int mips64_exec_AND(cpu_mips_t *cpu,mips_insn_t insn) |
538 |
|
|
{ |
539 |
|
|
int rs = bits(insn,21,25); |
540 |
|
|
int rt = bits(insn,16,20); |
541 |
|
|
int rd = bits(insn,11,15); |
542 |
|
|
|
543 |
|
|
cpu->gpr[rd] = cpu->gpr[rs] & cpu->gpr[rt]; |
544 |
|
|
return(0); |
545 |
|
|
} |
546 |
|
|
|
547 |
|
|
/* ANDI */ |
548 |
|
|
static fastcall int mips64_exec_ANDI(cpu_mips_t *cpu,mips_insn_t insn) |
549 |
|
|
{ |
550 |
|
|
int rs = bits(insn,21,25); |
551 |
|
|
int rt = bits(insn,16,20); |
552 |
|
|
int imm = bits(insn,0,15); |
553 |
|
|
|
554 |
|
|
cpu->gpr[rt] = cpu->gpr[rs] & imm; |
555 |
|
|
return(0); |
556 |
|
|
} |
557 |
|
|
|
558 |
|
|
/* B (Branch, virtual instruction) */ |
559 |
|
|
static fastcall int mips64_exec_B(cpu_mips_t *cpu,mips_insn_t insn) |
560 |
|
|
{ |
561 |
|
|
int offset = bits(insn,0,15); |
562 |
|
|
m_uint64_t new_pc; |
563 |
|
|
|
564 |
|
|
/* compute the new pc */ |
565 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
566 |
|
|
|
567 |
|
|
/* exec the instruction in the delay slot */ |
568 |
|
|
mips64_exec_bdslot(cpu); |
569 |
|
|
|
570 |
|
|
/* set the new pc in cpu structure */ |
571 |
|
|
cpu->pc = new_pc; |
572 |
|
|
return(1); |
573 |
|
|
} |
574 |
|
|
|
575 |
|
|
/* BAL (Branch And Link, virtual instruction) */ |
576 |
|
|
static fastcall int mips64_exec_BAL(cpu_mips_t *cpu,mips_insn_t insn) |
577 |
|
|
{ |
578 |
|
|
int offset = bits(insn,0,15); |
579 |
|
|
m_uint64_t new_pc; |
580 |
|
|
|
581 |
|
|
/* compute the new pc */ |
582 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
583 |
|
|
|
584 |
|
|
/* set the return address (instruction after the delay slot) */ |
585 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
586 |
|
|
|
587 |
|
|
/* exec the instruction in the delay slot */ |
588 |
|
|
mips64_exec_bdslot(cpu); |
589 |
|
|
|
590 |
|
|
/* set the new pc in cpu structure */ |
591 |
|
|
cpu->pc = new_pc; |
592 |
|
|
return(1); |
593 |
|
|
} |
594 |
|
|
|
595 |
|
|
/* BEQ (Branch On Equal) */ |
596 |
|
|
static fastcall int mips64_exec_BEQ(cpu_mips_t *cpu,mips_insn_t insn) |
597 |
|
|
{ |
598 |
|
|
int rs = bits(insn,21,25); |
599 |
|
|
int rt = bits(insn,16,20); |
600 |
|
|
int offset = bits(insn,0,15); |
601 |
|
|
m_uint64_t new_pc; |
602 |
|
|
int res; |
603 |
|
|
|
604 |
|
|
/* compute the new pc */ |
605 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
606 |
|
|
|
607 |
|
|
/* take the branch if gpr[rs] == gpr[rt] */ |
608 |
|
|
res = (cpu->gpr[rs] == cpu->gpr[rt]); |
609 |
|
|
|
610 |
|
|
/* exec the instruction in the delay slot */ |
611 |
|
|
mips64_exec_bdslot(cpu); |
612 |
|
|
|
613 |
|
|
/* take the branch if the test result is true */ |
614 |
|
|
if (res) |
615 |
|
|
cpu->pc = new_pc; |
616 |
|
|
else |
617 |
|
|
cpu->pc += 8; |
618 |
|
|
|
619 |
|
|
return(1); |
620 |
|
|
} |
621 |
|
|
|
622 |
|
|
/* BEQL (Branch On Equal Likely) */ |
623 |
|
|
static fastcall int mips64_exec_BEQL(cpu_mips_t *cpu,mips_insn_t insn) |
624 |
|
|
{ |
625 |
|
|
int rs = bits(insn,21,25); |
626 |
|
|
int rt = bits(insn,16,20); |
627 |
|
|
int offset = bits(insn,0,15); |
628 |
|
|
m_uint64_t new_pc; |
629 |
|
|
int res; |
630 |
|
|
|
631 |
|
|
/* compute the new pc */ |
632 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
633 |
|
|
|
634 |
|
|
/* take the branch if gpr[rs] == gpr[rt] */ |
635 |
|
|
res = (cpu->gpr[rs] == cpu->gpr[rt]); |
636 |
|
|
|
637 |
|
|
/* take the branch if the test result is true */ |
638 |
|
|
if (res) { |
639 |
|
|
mips64_exec_bdslot(cpu); |
640 |
|
|
cpu->pc = new_pc; |
641 |
|
|
} else |
642 |
|
|
cpu->pc += 8; |
643 |
|
|
|
644 |
|
|
return(1); |
645 |
|
|
} |
646 |
|
|
|
647 |
|
|
/* BEQZ (Branch On Equal Zero) - Virtual Instruction */ |
648 |
|
|
static fastcall int mips64_exec_BEQZ(cpu_mips_t *cpu,mips_insn_t insn) |
649 |
|
|
{ |
650 |
|
|
int rs = bits(insn,21,25); |
651 |
|
|
int offset = bits(insn,0,15); |
652 |
|
|
m_uint64_t new_pc; |
653 |
|
|
int res; |
654 |
|
|
|
655 |
|
|
/* compute the new pc */ |
656 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
657 |
|
|
|
658 |
|
|
/* take the branch if gpr[rs] == 0 */ |
659 |
|
|
res = (cpu->gpr[rs] == 0); |
660 |
|
|
|
661 |
|
|
/* exec the instruction in the delay slot */ |
662 |
|
|
mips64_exec_bdslot(cpu); |
663 |
|
|
|
664 |
|
|
/* take the branch if the test result is true */ |
665 |
|
|
if (res) |
666 |
|
|
cpu->pc = new_pc; |
667 |
|
|
else |
668 |
|
|
cpu->pc += 8; |
669 |
|
|
|
670 |
|
|
return(1); |
671 |
|
|
} |
672 |
|
|
|
673 |
|
|
/* BNEZ (Branch On Not Equal Zero) - Virtual Instruction */ |
674 |
|
|
static fastcall int mips64_exec_BNEZ(cpu_mips_t *cpu,mips_insn_t insn) |
675 |
|
|
{ |
676 |
|
|
int rs = bits(insn,21,25); |
677 |
|
|
int offset = bits(insn,0,15); |
678 |
|
|
m_uint64_t new_pc; |
679 |
|
|
int res; |
680 |
|
|
|
681 |
|
|
/* compute the new pc */ |
682 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
683 |
|
|
|
684 |
|
|
/* take the branch if gpr[rs] != 0 */ |
685 |
|
|
res = (cpu->gpr[rs] != 0); |
686 |
|
|
|
687 |
|
|
/* exec the instruction in the delay slot */ |
688 |
|
|
mips64_exec_bdslot(cpu); |
689 |
|
|
|
690 |
|
|
/* take the branch if the test result is true */ |
691 |
|
|
if (res) |
692 |
|
|
cpu->pc = new_pc; |
693 |
|
|
else |
694 |
|
|
cpu->pc += 8; |
695 |
|
|
|
696 |
|
|
return(1); |
697 |
|
|
} |
698 |
|
|
|
699 |
|
|
/* BGEZ (Branch On Greater or Equal Than Zero) */ |
700 |
|
|
static fastcall int mips64_exec_BGEZ(cpu_mips_t *cpu,mips_insn_t insn) |
701 |
|
|
{ |
702 |
|
|
int rs = bits(insn,21,25); |
703 |
|
|
int offset = bits(insn,0,15); |
704 |
|
|
m_uint64_t new_pc; |
705 |
|
|
int res; |
706 |
|
|
|
707 |
|
|
/* compute the new pc */ |
708 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
709 |
|
|
|
710 |
|
|
/* take the branch if gpr[rs] >= 0 */ |
711 |
|
|
res = ((m_int64_t)cpu->gpr[rs] >= 0); |
712 |
|
|
|
713 |
|
|
/* exec the instruction in the delay slot */ |
714 |
|
|
mips64_exec_bdslot(cpu); |
715 |
|
|
|
716 |
|
|
/* take the branch if the test result is true */ |
717 |
|
|
if (res) |
718 |
|
|
cpu->pc = new_pc; |
719 |
|
|
else |
720 |
|
|
cpu->pc += 8; |
721 |
|
|
|
722 |
|
|
return(1); |
723 |
|
|
} |
724 |
|
|
|
725 |
|
|
/* BGEZAL (Branch On Greater or Equal Than Zero And Link) */ |
726 |
|
|
static fastcall int mips64_exec_BGEZAL(cpu_mips_t *cpu,mips_insn_t insn) |
727 |
|
|
{ |
728 |
|
|
int rs = bits(insn,21,25); |
729 |
|
|
int offset = bits(insn,0,15); |
730 |
|
|
m_uint64_t new_pc; |
731 |
|
|
int res; |
732 |
|
|
|
733 |
|
|
/* compute the new pc */ |
734 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
735 |
|
|
|
736 |
|
|
/* set the return address (instruction after the delay slot) */ |
737 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
738 |
|
|
|
739 |
|
|
/* take the branch if gpr[rs] >= 0 */ |
740 |
|
|
res = ((m_int64_t)cpu->gpr[rs] >= 0); |
741 |
|
|
|
742 |
|
|
/* exec the instruction in the delay slot */ |
743 |
|
|
mips64_exec_bdslot(cpu); |
744 |
|
|
|
745 |
|
|
/* take the branch if the test result is true */ |
746 |
|
|
if (res) |
747 |
|
|
cpu->pc = new_pc; |
748 |
|
|
else |
749 |
|
|
cpu->pc += 8; |
750 |
|
|
|
751 |
|
|
return(1); |
752 |
|
|
} |
753 |
|
|
|
754 |
|
|
/* BGEZALL (Branch On Greater or Equal Than Zero And Link Likely) */ |
755 |
|
|
static fastcall int mips64_exec_BGEZALL(cpu_mips_t *cpu,mips_insn_t insn) |
756 |
|
|
{ |
757 |
|
|
int rs = bits(insn,21,25); |
758 |
|
|
int offset = bits(insn,0,15); |
759 |
|
|
m_uint64_t new_pc; |
760 |
|
|
int res; |
761 |
|
|
|
762 |
|
|
/* compute the new pc */ |
763 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
764 |
|
|
|
765 |
|
|
/* set the return address (instruction after the delay slot) */ |
766 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
767 |
|
|
|
768 |
|
|
/* take the branch if gpr[rs] >= 0 */ |
769 |
|
|
res = ((m_int64_t)cpu->gpr[rs] >= 0); |
770 |
|
|
|
771 |
|
|
/* take the branch if the test result is true */ |
772 |
|
|
if (res) { |
773 |
|
|
mips64_exec_bdslot(cpu); |
774 |
|
|
cpu->pc = new_pc; |
775 |
|
|
} else |
776 |
|
|
cpu->pc += 8; |
777 |
|
|
|
778 |
|
|
return(1); |
779 |
|
|
} |
780 |
|
|
|
781 |
|
|
/* BGEZL (Branch On Greater or Equal Than Zero Likely) */ |
782 |
|
|
static fastcall int mips64_exec_BGEZL(cpu_mips_t *cpu,mips_insn_t insn) |
783 |
|
|
{ |
784 |
|
|
int rs = bits(insn,21,25); |
785 |
|
|
int offset = bits(insn,0,15); |
786 |
|
|
m_uint64_t new_pc; |
787 |
|
|
int res; |
788 |
|
|
|
789 |
|
|
/* compute the new pc */ |
790 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
791 |
|
|
|
792 |
|
|
/* take the branch if gpr[rs] >= 0 */ |
793 |
|
|
res = ((m_int64_t)cpu->gpr[rs] >= 0); |
794 |
|
|
|
795 |
|
|
/* take the branch if the test result is true */ |
796 |
|
|
if (res) { |
797 |
|
|
mips64_exec_bdslot(cpu); |
798 |
|
|
cpu->pc = new_pc; |
799 |
|
|
} else |
800 |
|
|
cpu->pc += 8; |
801 |
|
|
|
802 |
|
|
return(1); |
803 |
|
|
} |
804 |
|
|
|
805 |
|
|
/* BGTZ (Branch On Greater Than Zero) */ |
806 |
|
|
static fastcall int mips64_exec_BGTZ(cpu_mips_t *cpu,mips_insn_t insn) |
807 |
|
|
{ |
808 |
|
|
int rs = bits(insn,21,25); |
809 |
|
|
int offset = bits(insn,0,15); |
810 |
|
|
m_uint64_t new_pc; |
811 |
|
|
int res; |
812 |
|
|
|
813 |
|
|
/* compute the new pc */ |
814 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
815 |
|
|
|
816 |
|
|
/* take the branch if gpr[rs] > 0 */ |
817 |
|
|
res = ((m_int64_t)cpu->gpr[rs] > 0); |
818 |
|
|
|
819 |
|
|
/* exec the instruction in the delay slot */ |
820 |
|
|
mips64_exec_bdslot(cpu); |
821 |
|
|
|
822 |
|
|
/* take the branch if the test result is true */ |
823 |
|
|
if (res) |
824 |
|
|
cpu->pc = new_pc; |
825 |
|
|
else |
826 |
|
|
cpu->pc += 8; |
827 |
|
|
|
828 |
|
|
return(1); |
829 |
|
|
} |
830 |
|
|
|
831 |
|
|
/* BGTZL (Branch On Greater Than Zero Likely) */ |
832 |
|
|
static fastcall int mips64_exec_BGTZL(cpu_mips_t *cpu,mips_insn_t insn) |
833 |
|
|
{ |
834 |
|
|
int rs = bits(insn,21,25); |
835 |
|
|
int offset = bits(insn,0,15); |
836 |
|
|
m_uint64_t new_pc; |
837 |
|
|
int res; |
838 |
|
|
|
839 |
|
|
/* compute the new pc */ |
840 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
841 |
|
|
|
842 |
|
|
/* take the branch if gpr[rs] > 0 */ |
843 |
|
|
res = ((m_int64_t)cpu->gpr[rs] > 0); |
844 |
|
|
|
845 |
|
|
/* take the branch if the test result is true */ |
846 |
|
|
if (res) { |
847 |
|
|
mips64_exec_bdslot(cpu); |
848 |
|
|
cpu->pc = new_pc; |
849 |
|
|
} else |
850 |
|
|
cpu->pc += 8; |
851 |
|
|
|
852 |
|
|
return(1); |
853 |
|
|
} |
854 |
|
|
|
855 |
|
|
/* BLEZ (Branch On Less or Equal Than Zero) */ |
856 |
|
|
static fastcall int mips64_exec_BLEZ(cpu_mips_t *cpu,mips_insn_t insn) |
857 |
|
|
{ |
858 |
|
|
int rs = bits(insn,21,25); |
859 |
|
|
int offset = bits(insn,0,15); |
860 |
|
|
m_uint64_t new_pc; |
861 |
|
|
int res; |
862 |
|
|
|
863 |
|
|
/* compute the new pc */ |
864 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
865 |
|
|
|
866 |
|
|
/* take the branch if gpr[rs] <= 0 */ |
867 |
|
|
res = ((m_int64_t)cpu->gpr[rs] <= 0); |
868 |
|
|
|
869 |
|
|
/* exec the instruction in the delay slot */ |
870 |
|
|
mips64_exec_bdslot(cpu); |
871 |
|
|
|
872 |
|
|
/* take the branch if the test result is true */ |
873 |
|
|
if (res) |
874 |
|
|
cpu->pc = new_pc; |
875 |
|
|
else |
876 |
|
|
cpu->pc += 8; |
877 |
|
|
|
878 |
|
|
return(1); |
879 |
|
|
} |
880 |
|
|
|
881 |
|
|
/* BLEZL (Branch On Less or Equal Than Zero Likely) */ |
882 |
|
|
static fastcall int mips64_exec_BLEZL(cpu_mips_t *cpu,mips_insn_t insn) |
883 |
|
|
{ |
884 |
|
|
int rs = bits(insn,21,25); |
885 |
|
|
int offset = bits(insn,0,15); |
886 |
|
|
m_uint64_t new_pc; |
887 |
|
|
int res; |
888 |
|
|
|
889 |
|
|
/* compute the new pc */ |
890 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
891 |
|
|
|
892 |
|
|
/* take the branch if gpr[rs] <= 0 */ |
893 |
|
|
res = ((m_int64_t)cpu->gpr[rs] <= 0); |
894 |
|
|
|
895 |
|
|
/* take the branch if the test result is true */ |
896 |
|
|
if (res) { |
897 |
|
|
mips64_exec_bdslot(cpu); |
898 |
|
|
cpu->pc = new_pc; |
899 |
|
|
} else |
900 |
|
|
cpu->pc += 8; |
901 |
|
|
|
902 |
|
|
return(1); |
903 |
|
|
} |
904 |
|
|
|
905 |
|
|
/* BLTZ (Branch On Less Than Zero) */ |
906 |
|
|
static fastcall int mips64_exec_BLTZ(cpu_mips_t *cpu,mips_insn_t insn) |
907 |
|
|
{ |
908 |
|
|
int rs = bits(insn,21,25); |
909 |
|
|
int offset = bits(insn,0,15); |
910 |
|
|
m_uint64_t new_pc; |
911 |
|
|
int res; |
912 |
|
|
|
913 |
|
|
/* compute the new pc */ |
914 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
915 |
|
|
|
916 |
|
|
/* take the branch if gpr[rs] < 0 */ |
917 |
|
|
res = ((m_int64_t)cpu->gpr[rs] < 0); |
918 |
|
|
|
919 |
|
|
/* exec the instruction in the delay slot */ |
920 |
|
|
mips64_exec_bdslot(cpu); |
921 |
|
|
|
922 |
|
|
/* take the branch if the test result is true */ |
923 |
|
|
if (res) |
924 |
|
|
cpu->pc = new_pc; |
925 |
|
|
else |
926 |
|
|
cpu->pc += 8; |
927 |
|
|
|
928 |
|
|
return(1); |
929 |
|
|
} |
930 |
|
|
|
931 |
|
|
/* BLTZAL (Branch On Less Than Zero And Link) */ |
932 |
|
|
static fastcall int mips64_exec_BLTZAL(cpu_mips_t *cpu,mips_insn_t insn) |
933 |
|
|
{ |
934 |
|
|
int rs = bits(insn,21,25); |
935 |
|
|
int offset = bits(insn,0,15); |
936 |
|
|
m_uint64_t new_pc; |
937 |
|
|
int res; |
938 |
|
|
|
939 |
|
|
/* compute the new pc */ |
940 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
941 |
|
|
|
942 |
|
|
/* set the return address (instruction after the delay slot) */ |
943 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
944 |
|
|
|
945 |
|
|
/* take the branch if gpr[rs] < 0 */ |
946 |
|
|
res = ((m_int64_t)cpu->gpr[rs] < 0); |
947 |
|
|
|
948 |
|
|
/* exec the instruction in the delay slot */ |
949 |
|
|
mips64_exec_bdslot(cpu); |
950 |
|
|
|
951 |
|
|
/* take the branch if the test result is true */ |
952 |
|
|
if (res) |
953 |
|
|
cpu->pc = new_pc; |
954 |
|
|
else |
955 |
|
|
cpu->pc += 8; |
956 |
|
|
|
957 |
|
|
return(1); |
958 |
|
|
} |
959 |
|
|
|
960 |
|
|
/* BLTZALL (Branch On Less Than Zero And Link Likely) */ |
961 |
|
|
static fastcall int mips64_exec_BLTZALL(cpu_mips_t *cpu,mips_insn_t insn) |
962 |
|
|
{ |
963 |
|
|
int rs = bits(insn,21,25); |
964 |
|
|
int offset = bits(insn,0,15); |
965 |
|
|
m_uint64_t new_pc; |
966 |
|
|
int res; |
967 |
|
|
|
968 |
|
|
/* compute the new pc */ |
969 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
970 |
|
|
|
971 |
|
|
/* set the return address (instruction after the delay slot) */ |
972 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
973 |
|
|
|
974 |
|
|
/* take the branch if gpr[rs] < 0 */ |
975 |
|
|
res = ((m_int64_t)cpu->gpr[rs] < 0); |
976 |
|
|
|
977 |
|
|
/* take the branch if the test result is true */ |
978 |
|
|
if (res) { |
979 |
|
|
mips64_exec_bdslot(cpu); |
980 |
|
|
cpu->pc = new_pc; |
981 |
|
|
} else |
982 |
|
|
cpu->pc += 8; |
983 |
|
|
|
984 |
|
|
return(1); |
985 |
|
|
} |
986 |
|
|
|
987 |
|
|
/* BLTZL (Branch On Less Than Zero Likely) */ |
988 |
|
|
static fastcall int mips64_exec_BLTZL(cpu_mips_t *cpu,mips_insn_t insn) |
989 |
|
|
{ |
990 |
|
|
int rs = bits(insn,21,25); |
991 |
|
|
int offset = bits(insn,0,15); |
992 |
|
|
m_uint64_t new_pc; |
993 |
|
|
int res; |
994 |
|
|
|
995 |
|
|
/* compute the new pc */ |
996 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
997 |
|
|
|
998 |
|
|
/* take the branch if gpr[rs] < 0 */ |
999 |
|
|
res = ((m_int64_t)cpu->gpr[rs] < 0); |
1000 |
|
|
|
1001 |
|
|
/* take the branch if the test result is true */ |
1002 |
|
|
if (res) { |
1003 |
|
|
mips64_exec_bdslot(cpu); |
1004 |
|
|
cpu->pc = new_pc; |
1005 |
|
|
} else |
1006 |
|
|
cpu->pc += 8; |
1007 |
|
|
|
1008 |
|
|
return(1); |
1009 |
|
|
} |
1010 |
|
|
|
1011 |
|
|
/* BNE (Branch On Not Equal) */ |
1012 |
|
|
static fastcall int mips64_exec_BNE(cpu_mips_t *cpu,mips_insn_t insn) |
1013 |
|
|
{ |
1014 |
|
|
int rs = bits(insn,21,25); |
1015 |
|
|
int rt = bits(insn,16,20); |
1016 |
|
|
int offset = bits(insn,0,15); |
1017 |
|
|
m_uint64_t new_pc; |
1018 |
|
|
int res; |
1019 |
|
|
|
1020 |
|
|
/* compute the new pc */ |
1021 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
1022 |
|
|
|
1023 |
|
|
/* take the branch if gpr[rs] != gpr[rt] */ |
1024 |
|
|
res = (cpu->gpr[rs] != cpu->gpr[rt]); |
1025 |
|
|
|
1026 |
|
|
/* exec the instruction in the delay slot */ |
1027 |
|
|
mips64_exec_bdslot(cpu); |
1028 |
|
|
|
1029 |
|
|
/* take the branch if the test result is true */ |
1030 |
|
|
if (res) |
1031 |
|
|
cpu->pc = new_pc; |
1032 |
|
|
else |
1033 |
|
|
cpu->pc += 8; |
1034 |
|
|
|
1035 |
|
|
return(1); |
1036 |
|
|
} |
1037 |
|
|
|
1038 |
|
|
/* BNEL (Branch On Not Equal Likely) */ |
1039 |
|
|
static fastcall int mips64_exec_BNEL(cpu_mips_t *cpu,mips_insn_t insn) |
1040 |
|
|
{ |
1041 |
|
|
int rs = bits(insn,21,25); |
1042 |
|
|
int rt = bits(insn,16,20); |
1043 |
|
|
int offset = bits(insn,0,15); |
1044 |
|
|
m_uint64_t new_pc; |
1045 |
|
|
int res; |
1046 |
|
|
|
1047 |
|
|
/* compute the new pc */ |
1048 |
|
|
new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18); |
1049 |
|
|
|
1050 |
|
|
/* take the branch if gpr[rs] != gpr[rt] */ |
1051 |
|
|
res = (cpu->gpr[rs] != cpu->gpr[rt]); |
1052 |
|
|
|
1053 |
|
|
/* take the branch if the test result is true */ |
1054 |
|
|
if (res) { |
1055 |
|
|
mips64_exec_bdslot(cpu); |
1056 |
|
|
cpu->pc = new_pc; |
1057 |
|
|
} else |
1058 |
|
|
cpu->pc += 8; |
1059 |
|
|
|
1060 |
|
|
return(1); |
1061 |
|
|
} |
1062 |
|
|
|
1063 |
|
|
/* BREAK */ |
1064 |
|
|
static fastcall int mips64_exec_BREAK(cpu_mips_t *cpu,mips_insn_t insn) |
1065 |
|
|
{ |
1066 |
|
|
u_int code = bits(insn,6,25); |
1067 |
|
|
|
1068 |
|
|
mips64_exec_break(cpu,code); |
1069 |
|
|
return(1); |
1070 |
|
|
} |
1071 |
|
|
|
1072 |
|
|
/* CACHE */ |
1073 |
|
|
static fastcall int mips64_exec_CACHE(cpu_mips_t *cpu,mips_insn_t insn) |
1074 |
|
|
{ |
1075 |
|
|
int base = bits(insn,21,25); |
1076 |
|
|
int op = bits(insn,16,20); |
1077 |
|
|
int offset = bits(insn,0,15); |
1078 |
|
|
|
1079 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_CACHE,base,offset,op,FALSE)); |
1080 |
|
|
} |
1081 |
|
|
|
1082 |
|
|
/* CFC0 */ |
1083 |
|
|
static fastcall int mips64_exec_CFC0(cpu_mips_t *cpu,mips_insn_t insn) |
1084 |
|
|
{ |
1085 |
|
|
int rt = bits(insn,16,20); |
1086 |
|
|
int rd = bits(insn,11,15); |
1087 |
|
|
|
1088 |
dpavlin |
7 |
mips64_cp0_exec_cfc0(cpu,rt,rd); |
1089 |
dpavlin |
1 |
return(0); |
1090 |
|
|
} |
1091 |
|
|
|
1092 |
|
|
/* CTC0 */ |
1093 |
|
|
static fastcall int mips64_exec_CTC0(cpu_mips_t *cpu,mips_insn_t insn) |
1094 |
|
|
{ |
1095 |
|
|
int rt = bits(insn,16,20); |
1096 |
|
|
int rd = bits(insn,11,15); |
1097 |
|
|
|
1098 |
dpavlin |
7 |
mips64_cp0_exec_ctc0(cpu,rt,rd); |
1099 |
dpavlin |
1 |
return(0); |
1100 |
|
|
} |
1101 |
|
|
|
1102 |
|
|
/* DADDIU */ |
1103 |
|
|
static fastcall int mips64_exec_DADDIU(cpu_mips_t *cpu,mips_insn_t insn) |
1104 |
|
|
{ |
1105 |
|
|
int rs = bits(insn,21,25); |
1106 |
|
|
int rt = bits(insn,16,20); |
1107 |
|
|
int imm = bits(insn,0,15); |
1108 |
|
|
m_uint64_t val = sign_extend(imm,16); |
1109 |
|
|
|
1110 |
|
|
cpu->gpr[rt] = cpu->gpr[rs] + val; |
1111 |
|
|
return(0); |
1112 |
|
|
} |
1113 |
|
|
|
1114 |
|
|
/* DADDU: rd = rs + rt */ |
1115 |
|
|
static fastcall int mips64_exec_DADDU(cpu_mips_t *cpu,mips_insn_t insn) |
1116 |
|
|
{ |
1117 |
|
|
int rs = bits(insn,21,25); |
1118 |
|
|
int rt = bits(insn,16,20); |
1119 |
|
|
int rd = bits(insn,11,15); |
1120 |
|
|
|
1121 |
|
|
cpu->gpr[rd] = cpu->gpr[rs] + cpu->gpr[rt]; |
1122 |
|
|
return(0); |
1123 |
|
|
} |
1124 |
|
|
|
1125 |
|
|
/* DIV */ |
1126 |
|
|
static fastcall int mips64_exec_DIV(cpu_mips_t *cpu,mips_insn_t insn) |
1127 |
|
|
{ |
1128 |
|
|
int rs = bits(insn,21,25); |
1129 |
|
|
int rt = bits(insn,16,20); |
1130 |
|
|
|
1131 |
|
|
cpu->lo = (m_int32_t)cpu->gpr[rs] / (m_int32_t)cpu->gpr[rt]; |
1132 |
|
|
cpu->hi = (m_int32_t)cpu->gpr[rs] % (m_int32_t)cpu->gpr[rt]; |
1133 |
|
|
|
1134 |
|
|
cpu->lo = sign_extend(cpu->lo,32); |
1135 |
|
|
cpu->hi = sign_extend(cpu->hi,32); |
1136 |
|
|
return(0); |
1137 |
|
|
} |
1138 |
|
|
|
1139 |
|
|
/* DIVU */ |
1140 |
|
|
static fastcall int mips64_exec_DIVU(cpu_mips_t *cpu,mips_insn_t insn) |
1141 |
|
|
{ |
1142 |
|
|
int rs = bits(insn,21,25); |
1143 |
|
|
int rt = bits(insn,16,20); |
1144 |
|
|
|
1145 |
|
|
if (cpu->gpr[rt] == 0) |
1146 |
|
|
return(0); |
1147 |
|
|
|
1148 |
|
|
cpu->lo = (m_uint32_t)cpu->gpr[rs] / (m_uint32_t)cpu->gpr[rt]; |
1149 |
|
|
cpu->hi = (m_uint32_t)cpu->gpr[rs] % (m_uint32_t)cpu->gpr[rt]; |
1150 |
|
|
|
1151 |
|
|
cpu->lo = sign_extend(cpu->lo,32); |
1152 |
|
|
cpu->hi = sign_extend(cpu->hi,32); |
1153 |
|
|
return(0); |
1154 |
|
|
} |
1155 |
|
|
|
1156 |
|
|
/* DMFC0 */ |
1157 |
|
|
static fastcall int mips64_exec_DMFC0(cpu_mips_t *cpu,mips_insn_t insn) |
1158 |
|
|
{ |
1159 |
|
|
int rt = bits(insn,16,20); |
1160 |
|
|
int rd = bits(insn,11,15); |
1161 |
|
|
|
1162 |
dpavlin |
7 |
mips64_cp0_exec_dmfc0(cpu,rt,rd); |
1163 |
dpavlin |
1 |
return(0); |
1164 |
|
|
} |
1165 |
|
|
|
1166 |
|
|
/* DMFC1 */ |
1167 |
|
|
static fastcall int mips64_exec_DMFC1(cpu_mips_t *cpu,mips_insn_t insn) |
1168 |
|
|
{ |
1169 |
|
|
int rt = bits(insn,16,20); |
1170 |
|
|
int rd = bits(insn,11,15); |
1171 |
|
|
|
1172 |
|
|
mips64_exec_dmfc1(cpu,rt,rd); |
1173 |
|
|
return(0); |
1174 |
|
|
} |
1175 |
|
|
|
1176 |
|
|
/* DMTC0 */ |
1177 |
|
|
static fastcall int mips64_exec_DMTC0(cpu_mips_t *cpu,mips_insn_t insn) |
1178 |
|
|
{ |
1179 |
|
|
int rt = bits(insn,16,20); |
1180 |
|
|
int rd = bits(insn,11,15); |
1181 |
|
|
|
1182 |
dpavlin |
7 |
mips64_cp0_exec_dmtc0(cpu,rt,rd); |
1183 |
dpavlin |
1 |
return(0); |
1184 |
|
|
} |
1185 |
|
|
|
1186 |
|
|
/* DMTC1 */ |
1187 |
|
|
static fastcall int mips64_exec_DMTC1(cpu_mips_t *cpu,mips_insn_t insn) |
1188 |
|
|
{ |
1189 |
|
|
int rt = bits(insn,16,20); |
1190 |
|
|
int rd = bits(insn,11,15); |
1191 |
|
|
|
1192 |
|
|
mips64_exec_dmtc1(cpu,rt,rd); |
1193 |
|
|
return(0); |
1194 |
|
|
} |
1195 |
|
|
|
1196 |
|
|
/* DSLL */ |
1197 |
|
|
static fastcall int mips64_exec_DSLL(cpu_mips_t *cpu,mips_insn_t insn) |
1198 |
|
|
{ |
1199 |
|
|
int rt = bits(insn,16,20); |
1200 |
|
|
int rd = bits(insn,11,15); |
1201 |
|
|
int sa = bits(insn,6,10); |
1202 |
|
|
|
1203 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] << sa; |
1204 |
|
|
return(0); |
1205 |
|
|
} |
1206 |
|
|
|
1207 |
|
|
/* DSLL32 */ |
1208 |
|
|
static fastcall int mips64_exec_DSLL32(cpu_mips_t *cpu,mips_insn_t insn) |
1209 |
|
|
{ |
1210 |
|
|
int rt = bits(insn,16,20); |
1211 |
|
|
int rd = bits(insn,11,15); |
1212 |
|
|
int sa = bits(insn,6,10); |
1213 |
|
|
|
1214 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] << (32 + sa); |
1215 |
|
|
return(0); |
1216 |
|
|
} |
1217 |
|
|
|
1218 |
|
|
/* DSLLV */ |
1219 |
|
|
static fastcall int mips64_exec_DSLLV(cpu_mips_t *cpu,mips_insn_t insn) |
1220 |
|
|
{ |
1221 |
|
|
int rs = bits(insn,21,25); |
1222 |
|
|
int rt = bits(insn,16,20); |
1223 |
|
|
int rd = bits(insn,11,15); |
1224 |
|
|
|
1225 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] << (cpu->gpr[rs] & 0x3f); |
1226 |
|
|
return(0); |
1227 |
|
|
} |
1228 |
|
|
|
1229 |
|
|
/* DSRA */ |
1230 |
|
|
static fastcall int mips64_exec_DSRA(cpu_mips_t *cpu,mips_insn_t insn) |
1231 |
|
|
{ |
1232 |
|
|
int rt = bits(insn,16,20); |
1233 |
|
|
int rd = bits(insn,11,15); |
1234 |
|
|
int sa = bits(insn,6,10); |
1235 |
|
|
|
1236 |
|
|
cpu->gpr[rd] = (m_int64_t)cpu->gpr[rt] >> sa; |
1237 |
|
|
return(0); |
1238 |
|
|
} |
1239 |
|
|
|
1240 |
|
|
/* DSRA32 */ |
1241 |
|
|
static fastcall int mips64_exec_DSRA32(cpu_mips_t *cpu,mips_insn_t insn) |
1242 |
|
|
{ |
1243 |
|
|
int rt = bits(insn,16,20); |
1244 |
|
|
int rd = bits(insn,11,15); |
1245 |
|
|
int sa = bits(insn,6,10); |
1246 |
|
|
|
1247 |
|
|
cpu->gpr[rd] = (m_int64_t)cpu->gpr[rt] >> (32 + sa); |
1248 |
|
|
return(0); |
1249 |
|
|
} |
1250 |
|
|
|
1251 |
|
|
/* DSRAV */ |
1252 |
|
|
static fastcall int mips64_exec_DSRAV(cpu_mips_t *cpu,mips_insn_t insn) |
1253 |
|
|
{ |
1254 |
|
|
int rs = bits(insn,21,25); |
1255 |
|
|
int rt = bits(insn,16,20); |
1256 |
|
|
int rd = bits(insn,11,15); |
1257 |
|
|
|
1258 |
|
|
cpu->gpr[rd] = (m_int64_t)cpu->gpr[rt] >> (cpu->gpr[rs] & 0x3f); |
1259 |
|
|
return(0); |
1260 |
|
|
} |
1261 |
|
|
|
1262 |
|
|
/* DSRL */ |
1263 |
|
|
static fastcall int mips64_exec_DSRL(cpu_mips_t *cpu,mips_insn_t insn) |
1264 |
|
|
{ |
1265 |
|
|
int rt = bits(insn,16,20); |
1266 |
|
|
int rd = bits(insn,11,15); |
1267 |
|
|
int sa = bits(insn,6,10); |
1268 |
|
|
|
1269 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] >> sa; |
1270 |
|
|
return(0); |
1271 |
|
|
} |
1272 |
|
|
|
1273 |
|
|
/* DSRL32 */ |
1274 |
|
|
static fastcall int mips64_exec_DSRL32(cpu_mips_t *cpu,mips_insn_t insn) |
1275 |
|
|
{ |
1276 |
|
|
int rt = bits(insn,16,20); |
1277 |
|
|
int rd = bits(insn,11,15); |
1278 |
|
|
int sa = bits(insn,6,10); |
1279 |
|
|
|
1280 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] >> (32 + sa); |
1281 |
|
|
return(0); |
1282 |
|
|
} |
1283 |
|
|
|
1284 |
|
|
/* DSRLV */ |
1285 |
|
|
static fastcall int mips64_exec_DSRLV(cpu_mips_t *cpu,mips_insn_t insn) |
1286 |
|
|
{ |
1287 |
|
|
int rs = bits(insn,21,25); |
1288 |
|
|
int rt = bits(insn,16,20); |
1289 |
|
|
int rd = bits(insn,11,15); |
1290 |
|
|
|
1291 |
|
|
cpu->gpr[rd] = cpu->gpr[rt] >> (cpu->gpr[rs] & 0x3f); |
1292 |
|
|
return(0); |
1293 |
|
|
} |
1294 |
|
|
|
1295 |
|
|
/* DSUBU */ |
1296 |
|
|
static fastcall int mips64_exec_DSUBU(cpu_mips_t *cpu,mips_insn_t insn) |
1297 |
|
|
{ |
1298 |
|
|
int rs = bits(insn,21,25); |
1299 |
|
|
int rt = bits(insn,16,20); |
1300 |
|
|
int rd = bits(insn,11,15); |
1301 |
|
|
|
1302 |
|
|
cpu->gpr[rd] = cpu->gpr[rs] - cpu->gpr[rt]; |
1303 |
|
|
return(0); |
1304 |
|
|
} |
1305 |
|
|
|
1306 |
|
|
/* ERET */ |
1307 |
|
|
static fastcall int mips64_exec_ERET(cpu_mips_t *cpu,mips_insn_t insn) |
1308 |
|
|
{ |
1309 |
|
|
mips64_exec_eret(cpu); |
1310 |
|
|
return(1); |
1311 |
|
|
} |
1312 |
|
|
|
1313 |
|
|
/* J */ |
1314 |
|
|
static fastcall int mips64_exec_J(cpu_mips_t *cpu,mips_insn_t insn) |
1315 |
|
|
{ |
1316 |
|
|
u_int instr_index = bits(insn,0,25); |
1317 |
|
|
m_uint64_t new_pc; |
1318 |
|
|
|
1319 |
|
|
/* compute the new pc */ |
1320 |
|
|
new_pc = cpu->pc & ~((1 << 28) - 1); |
1321 |
|
|
new_pc |= instr_index << 2; |
1322 |
|
|
|
1323 |
|
|
/* exec the instruction in the delay slot */ |
1324 |
|
|
mips64_exec_bdslot(cpu); |
1325 |
|
|
|
1326 |
|
|
/* set the new pc */ |
1327 |
|
|
cpu->pc = new_pc; |
1328 |
|
|
return(1); |
1329 |
|
|
} |
1330 |
|
|
|
1331 |
|
|
/* JAL */ |
1332 |
|
|
static fastcall int mips64_exec_JAL(cpu_mips_t *cpu,mips_insn_t insn) |
1333 |
|
|
{ |
1334 |
|
|
u_int instr_index = bits(insn,0,25); |
1335 |
|
|
m_uint64_t new_pc; |
1336 |
|
|
|
1337 |
|
|
/* compute the new pc */ |
1338 |
|
|
new_pc = cpu->pc & ~((1 << 28) - 1); |
1339 |
|
|
new_pc |= instr_index << 2; |
1340 |
|
|
|
1341 |
|
|
/* set the return address (instruction after the delay slot) */ |
1342 |
|
|
cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8; |
1343 |
|
|
|
1344 |
|
|
/* exec the instruction in the delay slot */ |
1345 |
|
|
mips64_exec_bdslot(cpu); |
1346 |
|
|
|
1347 |
|
|
/* set the new pc */ |
1348 |
|
|
cpu->pc = new_pc; |
1349 |
|
|
return(1); |
1350 |
|
|
} |
1351 |
|
|
|
1352 |
|
|
/* JALR */ |
1353 |
|
|
static fastcall int mips64_exec_JALR(cpu_mips_t *cpu,mips_insn_t insn) |
1354 |
|
|
{ |
1355 |
|
|
int rs = bits(insn,21,25); |
1356 |
|
|
int rd = bits(insn,11,15); |
1357 |
|
|
m_uint64_t new_pc; |
1358 |
|
|
|
1359 |
|
|
/* set the return pc (instruction after the delay slot) in GPR[rd] */ |
1360 |
|
|
cpu->gpr[rd] = cpu->pc + 8; |
1361 |
|
|
|
1362 |
|
|
/* get the new pc */ |
1363 |
|
|
new_pc = cpu->gpr[rs]; |
1364 |
|
|
|
1365 |
|
|
/* exec the instruction in the delay slot */ |
1366 |
|
|
mips64_exec_bdslot(cpu); |
1367 |
|
|
|
1368 |
|
|
/* set the new pc */ |
1369 |
|
|
cpu->pc = new_pc; |
1370 |
|
|
return(1); |
1371 |
|
|
} |
1372 |
|
|
|
1373 |
|
|
/* JR */ |
1374 |
|
|
static fastcall int mips64_exec_JR(cpu_mips_t *cpu,mips_insn_t insn) |
1375 |
|
|
{ |
1376 |
|
|
int rs = bits(insn,21,25); |
1377 |
|
|
m_uint64_t new_pc; |
1378 |
|
|
|
1379 |
|
|
/* get the new pc */ |
1380 |
|
|
new_pc = cpu->gpr[rs]; |
1381 |
|
|
|
1382 |
|
|
/* exec the instruction in the delay slot */ |
1383 |
|
|
mips64_exec_bdslot(cpu); |
1384 |
|
|
|
1385 |
|
|
/* set the new pc */ |
1386 |
|
|
cpu->pc = new_pc; |
1387 |
|
|
return(1); |
1388 |
|
|
} |
1389 |
|
|
|
1390 |
|
|
/* LB (Load Byte) */ |
1391 |
|
|
static fastcall int mips64_exec_LB(cpu_mips_t *cpu,mips_insn_t insn) |
1392 |
|
|
{ |
1393 |
|
|
int base = bits(insn,21,25); |
1394 |
|
|
int rt = bits(insn,16,20); |
1395 |
|
|
int offset = bits(insn,0,15); |
1396 |
|
|
|
1397 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LB,base,offset,rt,TRUE)); |
1398 |
|
|
} |
1399 |
|
|
|
1400 |
|
|
/* LBU (Load Byte Unsigned) */ |
1401 |
|
|
static fastcall int mips64_exec_LBU(cpu_mips_t *cpu,mips_insn_t insn) |
1402 |
|
|
{ |
1403 |
|
|
int base = bits(insn,21,25); |
1404 |
|
|
int rt = bits(insn,16,20); |
1405 |
|
|
int offset = bits(insn,0,15); |
1406 |
|
|
|
1407 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LBU,base,offset,rt,TRUE)); |
1408 |
|
|
} |
1409 |
|
|
|
1410 |
|
|
/* LD (Load Double-Word) */ |
1411 |
|
|
static fastcall int mips64_exec_LD(cpu_mips_t *cpu,mips_insn_t insn) |
1412 |
|
|
{ |
1413 |
|
|
int base = bits(insn,21,25); |
1414 |
|
|
int rt = bits(insn,16,20); |
1415 |
|
|
int offset = bits(insn,0,15); |
1416 |
|
|
|
1417 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LD,base,offset,rt,TRUE)); |
1418 |
|
|
} |
1419 |
|
|
|
1420 |
|
|
/* LDC1 (Load Double-Word to Coprocessor 1) */ |
1421 |
|
|
static fastcall int mips64_exec_LDC1(cpu_mips_t *cpu,mips_insn_t insn) |
1422 |
|
|
{ |
1423 |
|
|
int base = bits(insn,21,25); |
1424 |
|
|
int ft = bits(insn,16,20); |
1425 |
|
|
int offset = bits(insn,0,15); |
1426 |
|
|
|
1427 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDC1,base,offset,ft,TRUE)); |
1428 |
|
|
} |
1429 |
|
|
|
1430 |
|
|
/* LDL (Load Double-Word Left) */ |
1431 |
|
|
static fastcall int mips64_exec_LDL(cpu_mips_t *cpu,mips_insn_t insn) |
1432 |
|
|
{ |
1433 |
|
|
int base = bits(insn,21,25); |
1434 |
|
|
int rt = bits(insn,16,20); |
1435 |
|
|
int offset = bits(insn,0,15); |
1436 |
|
|
|
1437 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDL,base,offset,rt,TRUE)); |
1438 |
|
|
} |
1439 |
|
|
|
1440 |
|
|
/* LDR (Load Double-Word Right) */ |
1441 |
|
|
static fastcall int mips64_exec_LDR(cpu_mips_t *cpu,mips_insn_t insn) |
1442 |
|
|
{ |
1443 |
|
|
int base = bits(insn,21,25); |
1444 |
|
|
int rt = bits(insn,16,20); |
1445 |
|
|
int offset = bits(insn,0,15); |
1446 |
|
|
|
1447 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDR,base,offset,rt,TRUE)); |
1448 |
|
|
} |
1449 |
|
|
|
1450 |
|
|
/* LH (Load Half-Word) */ |
1451 |
|
|
static fastcall int mips64_exec_LH(cpu_mips_t *cpu,mips_insn_t insn) |
1452 |
|
|
{ |
1453 |
|
|
int base = bits(insn,21,25); |
1454 |
|
|
int rt = bits(insn,16,20); |
1455 |
|
|
int offset = bits(insn,0,15); |
1456 |
|
|
|
1457 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LH,base,offset,rt,TRUE)); |
1458 |
|
|
} |
1459 |
|
|
|
1460 |
|
|
/* LHU (Load Half-Word Unsigned) */ |
1461 |
|
|
static fastcall int mips64_exec_LHU(cpu_mips_t *cpu,mips_insn_t insn) |
1462 |
|
|
{ |
1463 |
|
|
int base = bits(insn,21,25); |
1464 |
|
|
int rt = bits(insn,16,20); |
1465 |
|
|
int offset = bits(insn,0,15); |
1466 |
|
|
|
1467 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LHU,base,offset,rt,TRUE)); |
1468 |
|
|
} |
1469 |
|
|
|
1470 |
|
|
/* LI (virtual) */ |
1471 |
|
|
static fastcall int mips64_exec_LI(cpu_mips_t *cpu,mips_insn_t insn) |
1472 |
|
|
{ |
1473 |
|
|
int rt = bits(insn,16,20); |
1474 |
|
|
int imm = bits(insn,0,15); |
1475 |
|
|
|
1476 |
|
|
cpu->gpr[rt] = sign_extend(imm,16); |
1477 |
|
|
return(0); |
1478 |
|
|
} |
1479 |
|
|
|
1480 |
|
|
/* LL (Load Linked) */ |
1481 |
|
|
static fastcall int mips64_exec_LL(cpu_mips_t *cpu,mips_insn_t insn) |
1482 |
|
|
{ |
1483 |
|
|
int base = bits(insn,21,25); |
1484 |
|
|
int rt = bits(insn,16,20); |
1485 |
|
|
int offset = bits(insn,0,15); |
1486 |
|
|
|
1487 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LL,base,offset,rt,TRUE)); |
1488 |
|
|
} |
1489 |
|
|
|
1490 |
|
|
/* LUI */ |
1491 |
|
|
static fastcall int mips64_exec_LUI(cpu_mips_t *cpu,mips_insn_t insn) |
1492 |
|
|
{ |
1493 |
|
|
int rt = bits(insn,16,20); |
1494 |
|
|
int imm = bits(insn,0,15); |
1495 |
|
|
|
1496 |
|
|
cpu->gpr[rt] = sign_extend(imm,16) << 16; |
1497 |
|
|
return(0); |
1498 |
|
|
} |
1499 |
|
|
|
1500 |
|
|
/* LW (Load Word) */ |
1501 |
|
|
static fastcall int mips64_exec_LW(cpu_mips_t *cpu,mips_insn_t insn) |
1502 |
|
|
{ |
1503 |
|
|
int base = bits(insn,21,25); |
1504 |
|
|
int rt = bits(insn,16,20); |
1505 |
|
|
int offset = bits(insn,0,15); |
1506 |
|
|
|
1507 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LW,base,offset,rt,TRUE)); |
1508 |
|
|
} |
1509 |
|
|
|
1510 |
|
|
/* LWL (Load Word Left) */ |
1511 |
|
|
static fastcall int mips64_exec_LWL(cpu_mips_t *cpu,mips_insn_t insn) |
1512 |
|
|
{ |
1513 |
|
|
int base = bits(insn,21,25); |
1514 |
|
|
int rt = bits(insn,16,20); |
1515 |
|
|
int offset = bits(insn,0,15); |
1516 |
|
|
|
1517 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWL,base,offset,rt,TRUE)); |
1518 |
|
|
} |
1519 |
|
|
|
1520 |
|
|
/* LWR (Load Word Right) */ |
1521 |
|
|
static fastcall int mips64_exec_LWR(cpu_mips_t *cpu,mips_insn_t insn) |
1522 |
|
|
{ |
1523 |
|
|
int base = bits(insn,21,25); |
1524 |
|
|
int rt = bits(insn,16,20); |
1525 |
|
|
int offset = bits(insn,0,15); |
1526 |
|
|
|
1527 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWR,base,offset,rt,TRUE)); |
1528 |
|
|
} |
1529 |
|
|
|
1530 |
|
|
/* LWU (Load Word Unsigned) */ |
1531 |
|
|
static fastcall int mips64_exec_LWU(cpu_mips_t *cpu,mips_insn_t insn) |
1532 |
|
|
{ |
1533 |
|
|
int base = bits(insn,21,25); |
1534 |
|
|
int rt = bits(insn,16,20); |
1535 |
|
|
int offset = bits(insn,0,15); |
1536 |
|
|
|
1537 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWU,base,offset,rt,TRUE)); |
1538 |
|
|
} |
1539 |
|
|
|
1540 |
|
|
/* MFC0 */ |
1541 |
|
|
static fastcall int mips64_exec_MFC0(cpu_mips_t *cpu,mips_insn_t insn) |
1542 |
|
|
{ |
1543 |
|
|
int rt = bits(insn,16,20); |
1544 |
|
|
int rd = bits(insn,11,15); |
1545 |
|
|
|
1546 |
dpavlin |
7 |
mips64_cp0_exec_mfc0(cpu,rt,rd); |
1547 |
dpavlin |
1 |
return(0); |
1548 |
|
|
} |
1549 |
|
|
|
1550 |
|
|
/* MFC1 */ |
1551 |
|
|
static fastcall int mips64_exec_MFC1(cpu_mips_t *cpu,mips_insn_t insn) |
1552 |
|
|
{ |
1553 |
|
|
int rt = bits(insn,16,20); |
1554 |
|
|
int rd = bits(insn,11,15); |
1555 |
|
|
|
1556 |
|
|
mips64_exec_mfc1(cpu,rt,rd); |
1557 |
|
|
return(0); |
1558 |
|
|
} |
1559 |
|
|
|
1560 |
|
|
/* MFHI */ |
1561 |
|
|
static fastcall int mips64_exec_MFHI(cpu_mips_t *cpu,mips_insn_t insn) |
1562 |
|
|
{ |
1563 |
|
|
int rd = bits(insn,11,15); |
1564 |
|
|
|
1565 |
|
|
if (rd) cpu->gpr[rd] = cpu->hi; |
1566 |
|
|
return(0); |
1567 |
|
|
} |
1568 |
|
|
|
1569 |
|
|
/* MFLO */ |
1570 |
|
|
static fastcall int mips64_exec_MFLO(cpu_mips_t *cpu,mips_insn_t insn) |
1571 |
|
|
{ |
1572 |
|
|
int rd = bits(insn,11,15); |
1573 |
|
|
|
1574 |
|
|
if (rd) cpu->gpr[rd] = cpu->lo; |
1575 |
|
|
return(0); |
1576 |
|
|
} |
1577 |
|
|
|
1578 |
|
|
/* MOVE (virtual instruction, real: ADDU) */ |
1579 |
|
|
static fastcall int mips64_exec_MOVE(cpu_mips_t *cpu,mips_insn_t insn) |
1580 |
|
|
{ |
1581 |
|
|
int rs = bits(insn,21,25); |
1582 |
|
|
int rd = bits(insn,11,15); |
1583 |
|
|
|
1584 |
|
|
cpu->gpr[rd] = sign_extend(cpu->gpr[rs],32); |
1585 |
|
|
return(0); |
1586 |
|
|
} |
1587 |
|
|
|
1588 |
|
|
/* MTC0 */ |
1589 |
|
|
static fastcall int mips64_exec_MTC0(cpu_mips_t *cpu,mips_insn_t insn) |
1590 |
|
|
{ |
1591 |
|
|
int rt = bits(insn,16,20); |
1592 |
|
|
int rd = bits(insn,11,15); |
1593 |
|
|
|
1594 |
dpavlin |
7 |
mips64_cp0_exec_mtc0(cpu,rt,rd); |
1595 |
dpavlin |
1 |
return(0); |
1596 |
|
|
} |
1597 |
|
|
|
1598 |
|
|
/* MTC1 */ |
1599 |
|
|
static fastcall int mips64_exec_MTC1(cpu_mips_t *cpu,mips_insn_t insn) |
1600 |
|
|
{ |
1601 |
|
|
int rt = bits(insn,16,20); |
1602 |
|
|
int rd = bits(insn,11,15); |
1603 |
|
|
|
1604 |
|
|
mips64_exec_mtc1(cpu,rt,rd); |
1605 |
|
|
return(0); |
1606 |
|
|
} |
1607 |
|
|
|
1608 |
|
|
/* MTHI */ |
1609 |
|
|
static fastcall int mips64_exec_MTHI(cpu_mips_t *cpu,mips_insn_t insn) |
1610 |
|
|
{ |
1611 |
|
|
int rs = bits(insn,21,25); |
1612 |
|
|
|
1613 |
|
|
cpu->hi = cpu->gpr[rs]; |
1614 |
|
|
return(0); |
1615 |
|
|
} |
1616 |
|
|
|
1617 |
|
|
/* MTLO */ |
1618 |
|
|
static fastcall int mips64_exec_MTLO(cpu_mips_t *cpu,mips_insn_t insn) |
1619 |
|
|
{ |
1620 |
|
|
int rs = bits(insn,21,25); |
1621 |
|
|
|
1622 |
|
|
cpu->lo = cpu->gpr[rs]; |
1623 |
|
|
return(0); |
1624 |
|
|
} |
1625 |
|
|
|
1626 |
|
|
/* MUL */ |
1627 |
|
|
static fastcall int mips64_exec_MUL(cpu_mips_t *cpu,mips_insn_t insn) |
1628 |
|
|
{ |
1629 |
|
|
int rs = bits(insn,21,25); |
1630 |
|
|
int rt = bits(insn,16,20); |
1631 |
|
|
int rd = bits(insn,11,15); |
1632 |
|
|
m_int32_t val; |
1633 |
|
|
|
1634 |
|
|
/* note: after this instruction, HI/LO regs are undefined */ |
1635 |
|
|
val = (m_int32_t)cpu->gpr[rs] * (m_int32_t)cpu->gpr[rt]; |
1636 |
|
|
cpu->gpr[rd] = sign_extend(val,32); |
1637 |
|
|
return(0); |
1638 |
|
|
} |
1639 |
|
|
|
1640 |
|
|
/* MULT */ |
1641 |
|
|
static fastcall int mips64_exec_MULT(cpu_mips_t *cpu,mips_insn_t insn) |
1642 |
|
|
{ |
1643 |
|
|
int rs = bits(insn,21,25); |
1644 |
|
|
int rt = bits(insn,16,20); |
1645 |
|
|
m_int64_t val; |
1646 |
|
|
|
1647 |
|
|
val = (m_int64_t)(m_int32_t)cpu->gpr[rs]; |
1648 |
|
|
val *= (m_int64_t)(m_int32_t)cpu->gpr[rt]; |
1649 |
|
|
|
1650 |
|
|
cpu->lo = sign_extend(val,32); |
1651 |
|
|
cpu->hi = sign_extend(val >> 32,32); |
1652 |
|
|
return(0); |
1653 |
|
|
} |
1654 |
|
|
|
1655 |
|
|
/* MULTU */ |
1656 |
|
|
static fastcall int mips64_exec_MULTU(cpu_mips_t *cpu,mips_insn_t insn) |
1657 |
|
|
{ |
1658 |
|
|
int rs = bits(insn,21,25); |
1659 |
|
|
int rt = bits(insn,16,20); |
1660 |
|
|
m_uint64_t val; |
1661 |
|
|
|
1662 |
|
|
val = (m_uint64_t)(m_uint32_t)cpu->gpr[rs]; |
1663 |
|
|
val *= (m_uint64_t)(m_uint32_t)cpu->gpr[rt]; |
1664 |
|
|
cpu->lo = sign_extend(val,32); |
1665 |
|
|
cpu->hi = sign_extend(val >> 32,32); |
1666 |
|
|
return(0); |
1667 |
|
|
} |
1668 |
|
|
|
1669 |
|
|
/* NOP */ |
1670 |
|
|
static fastcall int mips64_exec_NOP(cpu_mips_t *cpu,mips_insn_t insn) |
1671 |
|
|
{ |
1672 |
|
|
return(0); |
1673 |
|
|
} |
1674 |
|
|
|
1675 |
|
|
/* NOR */ |
1676 |
|
|
static fastcall int mips64_exec_NOR(cpu_mips_t *cpu,mips_insn_t insn) |
1677 |
|
|
{ |
1678 |
|
|
int rs = bits(insn,21,25); |
1679 |
|
|
int rt = bits(insn,16,20); |
1680 |
|
|
int rd = bits(insn,11,15); |
1681 |
|
|
|
1682 |
|
|
cpu->gpr[rd] = ~(cpu->gpr[rs] | cpu->gpr[rt]); |
1683 |
|
|
return(0); |
1684 |
|
|
} |
1685 |
|
|
|
1686 |
|
|
/* OR */ |
1687 |
|
|
static fastcall int mips64_exec_OR(cpu_mips_t *cpu,mips_insn_t insn) |
1688 |
|
|
{ |
1689 |
|
|
int rs = bits(insn,21,25); |
1690 |
|
|
int rt = bits(insn,16,20); |
1691 |
|
|
int rd = bits(insn,11,15); |
1692 |
|
|
|
1693 |
|
|
cpu->gpr[rd] = cpu->gpr[rs] | cpu->gpr[rt]; |
1694 |
|
|
return(0); |
1695 |
|
|
} |
1696 |
|
|
|
1697 |
|
|
/* ORI */ |
1698 |
|
|
static fastcall int mips64_exec_ORI(cpu_mips_t *cpu,mips_insn_t insn) |
1699 |
|
|
{ |
1700 |
|
|
int rs = bits(insn,21,25); |
1701 |
|
|
int rt = bits(insn,16,20); |
1702 |
|
|
int imm = bits(insn,0,15); |
1703 |
|
|
|
1704 |
|
|
cpu->gpr[rt] = cpu->gpr[rs] | imm; |
1705 |
|
|
return(0); |
1706 |
|
|
} |
1707 |
|
|
|
1708 |
|
|
/* PREF */ |
1709 |
|
|
static fastcall int mips64_exec_PREF(cpu_mips_t *cpu,mips_insn_t insn) |
1710 |
|
|
{ |
1711 |
|
|
return(0); |
1712 |
|
|
} |
1713 |
|
|
|
1714 |
|
|
/* PREFI */ |
1715 |
|
|
static fastcall int mips64_exec_PREFI(cpu_mips_t *cpu,mips_insn_t insn) |
1716 |
|
|
{ |
1717 |
|
|
return(0); |
1718 |
|
|
} |
1719 |
|
|
|
1720 |
|
|
/* SB (Store Byte) */ |
1721 |
|
|
static fastcall int mips64_exec_SB(cpu_mips_t *cpu,mips_insn_t insn) |
1722 |
|
|
{ |
1723 |
|
|
int base = bits(insn,21,25); |
1724 |
|
|
int rt = bits(insn,16,20); |
1725 |
|
|
int offset = bits(insn,0,15); |
1726 |
|
|
|
1727 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SB,base,offset,rt,FALSE)); |
1728 |
|
|
} |
1729 |
|
|
|
1730 |
|
|
/* SC (Store Conditional) */ |
1731 |
|
|
static fastcall int mips64_exec_SC(cpu_mips_t *cpu,mips_insn_t insn) |
1732 |
|
|
{ |
1733 |
|
|
int base = bits(insn,21,25); |
1734 |
|
|
int rt = bits(insn,16,20); |
1735 |
|
|
int offset = bits(insn,0,15); |
1736 |
|
|
|
1737 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SC,base,offset,rt,TRUE)); |
1738 |
|
|
} |
1739 |
|
|
|
1740 |
|
|
/* SD (Store Double-Word) */ |
1741 |
|
|
static fastcall int mips64_exec_SD(cpu_mips_t *cpu,mips_insn_t insn) |
1742 |
|
|
{ |
1743 |
|
|
int base = bits(insn,21,25); |
1744 |
|
|
int rt = bits(insn,16,20); |
1745 |
|
|
int offset = bits(insn,0,15); |
1746 |
|
|
|
1747 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SD,base,offset,rt,FALSE)); |
1748 |
|
|
} |
1749 |
|
|
|
1750 |
|
|
/* SDL (Store Double-Word Left) */ |
1751 |
|
|
static fastcall int mips64_exec_SDL(cpu_mips_t *cpu,mips_insn_t insn) |
1752 |
|
|
{ |
1753 |
|
|
int base = bits(insn,21,25); |
1754 |
|
|
int rt = bits(insn,16,20); |
1755 |
|
|
int offset = bits(insn,0,15); |
1756 |
|
|
|
1757 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDL,base,offset,rt,FALSE)); |
1758 |
|
|
} |
1759 |
|
|
|
1760 |
|
|
/* SDR (Store Double-Word Right) */ |
1761 |
|
|
static fastcall int mips64_exec_SDR(cpu_mips_t *cpu,mips_insn_t insn) |
1762 |
|
|
{ |
1763 |
|
|
int base = bits(insn,21,25); |
1764 |
|
|
int rt = bits(insn,16,20); |
1765 |
|
|
int offset = bits(insn,0,15); |
1766 |
|
|
|
1767 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDR,base,offset,rt,FALSE)); |
1768 |
|
|
} |
1769 |
|
|
|
1770 |
|
|
/* SDC1 (Store Double-Word from Coprocessor 1) */ |
1771 |
|
|
static fastcall int mips64_exec_SDC1(cpu_mips_t *cpu,mips_insn_t insn) |
1772 |
|
|
{ |
1773 |
|
|
int base = bits(insn,21,25); |
1774 |
|
|
int ft = bits(insn,16,20); |
1775 |
|
|
int offset = bits(insn,0,15); |
1776 |
|
|
|
1777 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDC1,base,offset,ft,FALSE)); |
1778 |
|
|
} |
1779 |
|
|
|
1780 |
|
|
/* SH (Store Half-Word) */ |
1781 |
|
|
static fastcall int mips64_exec_SH(cpu_mips_t *cpu,mips_insn_t insn) |
1782 |
|
|
{ |
1783 |
|
|
int base = bits(insn,21,25); |
1784 |
|
|
int rt = bits(insn,16,20); |
1785 |
|
|
int offset = bits(insn,0,15); |
1786 |
|
|
|
1787 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SH,base,offset,rt,FALSE)); |
1788 |
|
|
} |
1789 |
|
|
|
1790 |
|
|
/* SLL */ |
1791 |
|
|
static fastcall int mips64_exec_SLL(cpu_mips_t *cpu,mips_insn_t insn) |
1792 |
|
|
{ |
1793 |
|
|
int rt = bits(insn,16,20); |
1794 |
|
|
int rd = bits(insn,11,15); |
1795 |
|
|
int sa = bits(insn,6,10); |
1796 |
|
|
m_uint32_t res; |
1797 |
|
|
|
1798 |
|
|
res = (m_uint32_t)cpu->gpr[rt] << sa; |
1799 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1800 |
|
|
return(0); |
1801 |
|
|
} |
1802 |
|
|
|
1803 |
|
|
/* SLLV */ |
1804 |
|
|
static fastcall int mips64_exec_SLLV(cpu_mips_t *cpu,mips_insn_t insn) |
1805 |
|
|
{ |
1806 |
|
|
int rs = bits(insn,21,25); |
1807 |
|
|
int rt = bits(insn,16,20); |
1808 |
|
|
int rd = bits(insn,11,15); |
1809 |
|
|
m_uint32_t res; |
1810 |
|
|
|
1811 |
|
|
res = (m_uint32_t)cpu->gpr[rt] << (cpu->gpr[rs] & 0x1f); |
1812 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1813 |
|
|
return(0); |
1814 |
|
|
} |
1815 |
|
|
|
1816 |
|
|
/* SLT */ |
1817 |
|
|
static fastcall int mips64_exec_SLT(cpu_mips_t *cpu,mips_insn_t insn) |
1818 |
|
|
{ |
1819 |
|
|
int rs = bits(insn,21,25); |
1820 |
|
|
int rt = bits(insn,16,20); |
1821 |
|
|
int rd = bits(insn,11,15); |
1822 |
|
|
|
1823 |
|
|
if ((m_int64_t)cpu->gpr[rs] < (m_int64_t)cpu->gpr[rt]) |
1824 |
|
|
cpu->gpr[rd] = 1; |
1825 |
|
|
else |
1826 |
|
|
cpu->gpr[rd] = 0; |
1827 |
|
|
|
1828 |
|
|
return(0); |
1829 |
|
|
} |
1830 |
|
|
|
1831 |
|
|
/* SLTI */ |
1832 |
|
|
static fastcall int mips64_exec_SLTI(cpu_mips_t *cpu,mips_insn_t insn) |
1833 |
|
|
{ |
1834 |
|
|
int rs = bits(insn,21,25); |
1835 |
|
|
int rt = bits(insn,16,20); |
1836 |
|
|
int imm = bits(insn,0,15); |
1837 |
|
|
m_int64_t val = sign_extend(imm,16); |
1838 |
|
|
|
1839 |
|
|
if ((m_int64_t)cpu->gpr[rs] < val) |
1840 |
|
|
cpu->gpr[rt] = 1; |
1841 |
|
|
else |
1842 |
|
|
cpu->gpr[rt] = 0; |
1843 |
|
|
|
1844 |
|
|
return(0); |
1845 |
|
|
} |
1846 |
|
|
|
1847 |
|
|
/* SLTIU */ |
1848 |
|
|
static fastcall int mips64_exec_SLTIU(cpu_mips_t *cpu,mips_insn_t insn) |
1849 |
|
|
{ |
1850 |
|
|
int rs = bits(insn,21,25); |
1851 |
|
|
int rt = bits(insn,16,20); |
1852 |
|
|
int imm = bits(insn,0,15); |
1853 |
|
|
m_uint64_t val = sign_extend(imm,16); |
1854 |
|
|
|
1855 |
|
|
if (cpu->gpr[rs] < val) |
1856 |
|
|
cpu->gpr[rt] = 1; |
1857 |
|
|
else |
1858 |
|
|
cpu->gpr[rt] = 0; |
1859 |
|
|
|
1860 |
|
|
return(0); |
1861 |
|
|
} |
1862 |
|
|
|
1863 |
|
|
/* SLTU */ |
1864 |
|
|
static fastcall int mips64_exec_SLTU(cpu_mips_t *cpu,mips_insn_t insn) |
1865 |
|
|
{ |
1866 |
|
|
int rs = bits(insn,21,25); |
1867 |
|
|
int rt = bits(insn,16,20); |
1868 |
|
|
int rd = bits(insn,11,15); |
1869 |
|
|
|
1870 |
|
|
if (cpu->gpr[rs] < cpu->gpr[rt]) |
1871 |
|
|
cpu->gpr[rd] = 1; |
1872 |
|
|
else |
1873 |
|
|
cpu->gpr[rd] = 0; |
1874 |
|
|
|
1875 |
|
|
return(0); |
1876 |
|
|
} |
1877 |
|
|
|
1878 |
|
|
/* SRA */ |
1879 |
|
|
static fastcall int mips64_exec_SRA(cpu_mips_t *cpu,mips_insn_t insn) |
1880 |
|
|
{ |
1881 |
|
|
int rt = bits(insn,16,20); |
1882 |
|
|
int rd = bits(insn,11,15); |
1883 |
|
|
int sa = bits(insn,6,10); |
1884 |
|
|
m_int32_t res; |
1885 |
|
|
|
1886 |
|
|
res = (m_int32_t)cpu->gpr[rt] >> sa; |
1887 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1888 |
|
|
return(0); |
1889 |
|
|
} |
1890 |
|
|
|
1891 |
|
|
/* SRAV */ |
1892 |
|
|
static fastcall int mips64_exec_SRAV(cpu_mips_t *cpu,mips_insn_t insn) |
1893 |
|
|
{ |
1894 |
|
|
int rs = bits(insn,21,25); |
1895 |
|
|
int rt = bits(insn,16,20); |
1896 |
|
|
int rd = bits(insn,11,15); |
1897 |
|
|
m_int32_t res; |
1898 |
|
|
|
1899 |
|
|
res = (m_int32_t)cpu->gpr[rt] >> (cpu->gpr[rs] & 0x1f); |
1900 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1901 |
|
|
return(0); |
1902 |
|
|
} |
1903 |
|
|
|
1904 |
|
|
/* SRL */ |
1905 |
|
|
static fastcall int mips64_exec_SRL(cpu_mips_t *cpu,mips_insn_t insn) |
1906 |
|
|
{ |
1907 |
|
|
int rt = bits(insn,16,20); |
1908 |
|
|
int rd = bits(insn,11,15); |
1909 |
|
|
int sa = bits(insn,6,10); |
1910 |
|
|
m_uint32_t res; |
1911 |
|
|
|
1912 |
|
|
res = (m_uint32_t)cpu->gpr[rt] >> sa; |
1913 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1914 |
|
|
return(0); |
1915 |
|
|
} |
1916 |
|
|
|
1917 |
|
|
/* SRLV */ |
1918 |
|
|
static fastcall int mips64_exec_SRLV(cpu_mips_t *cpu,mips_insn_t insn) |
1919 |
|
|
{ |
1920 |
|
|
int rs = bits(insn,21,25); |
1921 |
|
|
int rt = bits(insn,16,20); |
1922 |
|
|
int rd = bits(insn,11,15); |
1923 |
|
|
m_uint32_t res; |
1924 |
|
|
|
1925 |
|
|
res = (m_uint32_t)cpu->gpr[rt] >> (cpu->gpr[rs] & 0x1f); |
1926 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1927 |
|
|
return(0); |
1928 |
|
|
} |
1929 |
|
|
|
1930 |
|
|
/* SUB */ |
1931 |
|
|
static fastcall int mips64_exec_SUB(cpu_mips_t *cpu,mips_insn_t insn) |
1932 |
|
|
{ |
1933 |
|
|
int rs = bits(insn,21,25); |
1934 |
|
|
int rt = bits(insn,16,20); |
1935 |
|
|
int rd = bits(insn,11,15); |
1936 |
|
|
m_uint32_t res; |
1937 |
|
|
|
1938 |
|
|
/* TODO: Exception handling */ |
1939 |
|
|
res = (m_uint32_t)cpu->gpr[rs] - (m_uint32_t)cpu->gpr[rt]; |
1940 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1941 |
|
|
return(0); |
1942 |
|
|
} |
1943 |
|
|
|
1944 |
|
|
/* SUBU */ |
1945 |
|
|
static fastcall int mips64_exec_SUBU(cpu_mips_t *cpu,mips_insn_t insn) |
1946 |
|
|
{ |
1947 |
|
|
int rs = bits(insn,21,25); |
1948 |
|
|
int rt = bits(insn,16,20); |
1949 |
|
|
int rd = bits(insn,11,15); |
1950 |
|
|
m_uint32_t res; |
1951 |
|
|
|
1952 |
|
|
res = (m_uint32_t)cpu->gpr[rs] - (m_uint32_t)cpu->gpr[rt]; |
1953 |
|
|
cpu->gpr[rd] = sign_extend(res,32); |
1954 |
|
|
return(0); |
1955 |
|
|
} |
1956 |
|
|
|
1957 |
|
|
/* SW (Store Word) */ |
1958 |
|
|
static fastcall int mips64_exec_SW(cpu_mips_t *cpu,mips_insn_t insn) |
1959 |
|
|
{ |
1960 |
|
|
int base = bits(insn,21,25); |
1961 |
|
|
int rt = bits(insn,16,20); |
1962 |
|
|
int offset = bits(insn,0,15); |
1963 |
|
|
|
1964 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SW,base,offset,rt,FALSE)); |
1965 |
|
|
} |
1966 |
|
|
|
1967 |
|
|
/* SWL (Store Word Left) */ |
1968 |
|
|
static fastcall int mips64_exec_SWL(cpu_mips_t *cpu,mips_insn_t insn) |
1969 |
|
|
{ |
1970 |
|
|
int base = bits(insn,21,25); |
1971 |
|
|
int rt = bits(insn,16,20); |
1972 |
|
|
int offset = bits(insn,0,15); |
1973 |
|
|
|
1974 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SWL,base,offset,rt,FALSE)); |
1975 |
|
|
} |
1976 |
|
|
|
1977 |
|
|
/* SWR (Store Word Right) */ |
1978 |
|
|
static fastcall int mips64_exec_SWR(cpu_mips_t *cpu,mips_insn_t insn) |
1979 |
|
|
{ |
1980 |
|
|
int base = bits(insn,21,25); |
1981 |
|
|
int rt = bits(insn,16,20); |
1982 |
|
|
int offset = bits(insn,0,15); |
1983 |
|
|
|
1984 |
|
|
return(mips64_exec_memop2(cpu,MIPS_MEMOP_SWR,base,offset,rt,FALSE)); |
1985 |
|
|
} |
1986 |
|
|
|
1987 |
|
|
/* SYNC */ |
1988 |
|
|
static fastcall int mips64_exec_SYNC(cpu_mips_t *cpu,mips_insn_t insn) |
1989 |
|
|
{ |
1990 |
|
|
return(0); |
1991 |
|
|
} |
1992 |
|
|
|
1993 |
|
|
/* SYSCALL */ |
1994 |
|
|
static fastcall int mips64_exec_SYSCALL(cpu_mips_t *cpu,mips_insn_t insn) |
1995 |
|
|
{ |
1996 |
|
|
mips64_exec_syscall(cpu); |
1997 |
|
|
return(1); |
1998 |
|
|
} |
1999 |
|
|
|
2000 |
|
|
/* TEQ (Trap if Equal) */ |
2001 |
|
|
static fastcall int mips64_exec_TEQ(cpu_mips_t *cpu,mips_insn_t insn) |
2002 |
|
|
{ |
2003 |
|
|
int rs = bits(insn,21,25); |
2004 |
|
|
int rt = bits(insn,16,20); |
2005 |
|
|
|
2006 |
|
|
if (unlikely(cpu->gpr[rs] == cpu->gpr[rt])) { |
2007 |
|
|
mips64_trigger_trap_exception(cpu); |
2008 |
|
|
return(1); |
2009 |
|
|
} |
2010 |
|
|
|
2011 |
|
|
return(0); |
2012 |
|
|
} |
2013 |
|
|
|
2014 |
|
|
/* TEQI (Trap if Equal Immediate) */ |
2015 |
|
|
static fastcall int mips64_exec_TEQI(cpu_mips_t *cpu,mips_insn_t insn) |
2016 |
|
|
{ |
2017 |
|
|
int rs = bits(insn,21,25); |
2018 |
|
|
int imm = bits(insn,0,15); |
2019 |
|
|
m_uint64_t val = sign_extend(imm,16); |
2020 |
|
|
|
2021 |
|
|
if (unlikely(cpu->gpr[rs] == val)) { |
2022 |
|
|
mips64_trigger_trap_exception(cpu); |
2023 |
|
|
return(1); |
2024 |
|
|
} |
2025 |
|
|
|
2026 |
|
|
return(0); |
2027 |
|
|
} |
2028 |
|
|
|
2029 |
|
|
/* TLBP */ |
2030 |
|
|
static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn) |
2031 |
|
|
{ |
2032 |
dpavlin |
7 |
mips64_cp0_exec_tlbp(cpu); |
2033 |
dpavlin |
1 |
return(0); |
2034 |
|
|
} |
2035 |
|
|
|
2036 |
|
|
/* TLBR */ |
2037 |
|
|
static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn) |
2038 |
|
|
{ |
2039 |
dpavlin |
7 |
mips64_cp0_exec_tlbr(cpu); |
2040 |
dpavlin |
1 |
return(0); |
2041 |
|
|
} |
2042 |
|
|
|
2043 |
|
|
/* TLBWI */ |
2044 |
|
|
static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn) |
2045 |
|
|
{ |
2046 |
dpavlin |
7 |
mips64_cp0_exec_tlbwi(cpu); |
2047 |
dpavlin |
1 |
return(0); |
2048 |
|
|
} |
2049 |
|
|
|
2050 |
|
|
/* TLBWR */ |
2051 |
|
|
static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn) |
2052 |
|
|
{ |
2053 |
dpavlin |
7 |
mips64_cp0_exec_tlbwr(cpu); |
2054 |
dpavlin |
1 |
return(0); |
2055 |
|
|
} |
2056 |
|
|
|
2057 |
|
|
/* XOR */ |
2058 |
|
|
static fastcall int mips64_exec_XOR(cpu_mips_t *cpu,mips_insn_t insn) |
2059 |
|
|
{ |
2060 |
|
|
int rs = bits(insn,21,25); |
2061 |
|
|
int rt = bits(insn,16,20); |
2062 |
|
|
int rd = bits(insn,11,15); |
2063 |
|
|
|
2064 |
|
|
cpu->gpr[rd] = cpu->gpr[rs] ^ cpu->gpr[rt]; |
2065 |
|
|
return(0); |
2066 |
|
|
} |
2067 |
|
|
|
2068 |
|
|
/* XORI */ |
2069 |
|
|
static fastcall int mips64_exec_XORI(cpu_mips_t *cpu,mips_insn_t insn) |
2070 |
|
|
{ |
2071 |
|
|
int rs = bits(insn,21,25); |
2072 |
|
|
int rt = bits(insn,16,20); |
2073 |
|
|
int imm = bits(insn,0,15); |
2074 |
|
|
|
2075 |
|
|
cpu->gpr[rt] = cpu->gpr[rs] ^ imm; |
2076 |
|
|
return(0); |
2077 |
|
|
} |
2078 |
|
|
|
2079 |
|
|
/* MIPS instruction array */ |
2080 |
dpavlin |
7 |
static struct mips64_insn_exec_tag mips64_exec_tags[] = { |
2081 |
dpavlin |
1 |
{ "li" , mips64_exec_LI , 0xffe00000 , 0x24000000, 1, 16 }, |
2082 |
|
|
{ "move" , mips64_exec_MOVE , 0xfc1f07ff , 0x00000021, 1, 15 }, |
2083 |
|
|
{ "b" , mips64_exec_B , 0xffff0000 , 0x10000000, 0, 10 }, |
2084 |
|
|
{ "bal" , mips64_exec_BAL , 0xffff0000 , 0x04110000, 0, 10 }, |
2085 |
|
|
{ "beqz" , mips64_exec_BEQZ , 0xfc1f0000 , 0x10000000, 0, 9 }, |
2086 |
|
|
{ "bnez" , mips64_exec_BNEZ , 0xfc1f0000 , 0x14000000, 0, 9 }, |
2087 |
|
|
{ "add" , mips64_exec_ADD , 0xfc0007ff , 0x00000020, 1, 3 }, |
2088 |
|
|
{ "addi" , mips64_exec_ADDI , 0xfc000000 , 0x20000000, 1, 6 }, |
2089 |
|
|
{ "addiu" , mips64_exec_ADDIU , 0xfc000000 , 0x24000000, 1, 6 }, |
2090 |
|
|
{ "addu" , mips64_exec_ADDU , 0xfc0007ff , 0x00000021, 1, 3 }, |
2091 |
|
|
{ "and" , mips64_exec_AND , 0xfc0007ff , 0x00000024, 1, 3 }, |
2092 |
|
|
{ "andi" , mips64_exec_ANDI , 0xfc000000 , 0x30000000, 1, 5 }, |
2093 |
|
|
{ "beq" , mips64_exec_BEQ , 0xfc000000 , 0x10000000, 0, 8 }, |
2094 |
|
|
{ "beql" , mips64_exec_BEQL , 0xfc000000 , 0x50000000, 0, 8 }, |
2095 |
|
|
{ "bgez" , mips64_exec_BGEZ , 0xfc1f0000 , 0x04010000, 0, 9 }, |
2096 |
|
|
{ "bgezal" , mips64_exec_BGEZAL , 0xfc1f0000 , 0x04110000, 0, 9 }, |
2097 |
|
|
{ "bgezall", mips64_exec_BGEZALL , 0xfc1f0000 , 0x04130000, 0, 9 }, |
2098 |
|
|
{ "bgezl" , mips64_exec_BGEZL , 0xfc1f0000 , 0x04030000, 0, 9 }, |
2099 |
|
|
{ "bgtz" , mips64_exec_BGTZ , 0xfc1f0000 , 0x1c000000, 0, 9 }, |
2100 |
|
|
{ "bgtzl" , mips64_exec_BGTZL , 0xfc1f0000 , 0x5c000000, 0, 9 }, |
2101 |
|
|
{ "blez" , mips64_exec_BLEZ , 0xfc1f0000 , 0x18000000, 0, 9 }, |
2102 |
|
|
{ "blezl" , mips64_exec_BLEZL , 0xfc1f0000 , 0x58000000, 0, 9 }, |
2103 |
|
|
{ "bltz" , mips64_exec_BLTZ , 0xfc1f0000 , 0x04000000, 0, 9 }, |
2104 |
|
|
{ "bltzal" , mips64_exec_BLTZAL , 0xfc1f0000 , 0x04100000, 0, 9 }, |
2105 |
|
|
{ "bltzall", mips64_exec_BLTZALL , 0xfc1f0000 , 0x04120000, 0, 9 }, |
2106 |
|
|
{ "bltzl" , mips64_exec_BLTZL , 0xfc1f0000 , 0x04020000, 0, 9 }, |
2107 |
|
|
{ "bne" , mips64_exec_BNE , 0xfc000000 , 0x14000000, 0, 8 }, |
2108 |
|
|
{ "bnel" , mips64_exec_BNEL , 0xfc000000 , 0x54000000, 0, 8 }, |
2109 |
|
|
{ "break" , mips64_exec_BREAK , 0xfc00003f , 0x0000000d, 1, 0 }, |
2110 |
|
|
{ "cache" , mips64_exec_CACHE , 0xfc000000 , 0xbc000000, 1, 2 }, |
2111 |
|
|
{ "cfc0" , mips64_exec_CFC0 , 0xffe007ff , 0x40400000, 1, 18 }, |
2112 |
|
|
{ "ctc0" , mips64_exec_CTC0 , 0xffe007ff , 0x40600000, 1, 18 }, |
2113 |
|
|
{ "daddiu" , mips64_exec_DADDIU , 0xfc000000 , 0x64000000, 1, 5 }, |
2114 |
|
|
{ "daddu" , mips64_exec_DADDU , 0xfc0007ff , 0x0000002d, 1, 3 }, |
2115 |
|
|
{ "div" , mips64_exec_DIV , 0xfc00ffff , 0x0000001a, 1, 17 }, |
2116 |
|
|
{ "divu" , mips64_exec_DIVU , 0xfc00ffff , 0x0000001b, 1, 17 }, |
2117 |
|
|
{ "dmfc0" , mips64_exec_DMFC0 , 0xffe007f8 , 0x40200000, 1, 18 }, |
2118 |
|
|
{ "dmfc1" , mips64_exec_DMFC1 , 0xffe007ff , 0x44200000, 1, 19 }, |
2119 |
|
|
{ "dmtc0" , mips64_exec_DMTC0 , 0xffe007f8 , 0x40a00000, 1, 18 }, |
2120 |
|
|
{ "dmtc1" , mips64_exec_DMTC1 , 0xffe007ff , 0x44a00000, 1, 19 }, |
2121 |
|
|
{ "dsll" , mips64_exec_DSLL , 0xffe0003f , 0x00000038, 1, 7 }, |
2122 |
|
|
{ "dsll32" , mips64_exec_DSLL32 , 0xffe0003f , 0x0000003c, 1, 7 }, |
2123 |
|
|
{ "dsllv" , mips64_exec_DSLLV , 0xfc0007ff , 0x00000014, 1, 4 }, |
2124 |
|
|
{ "dsra" , mips64_exec_DSRA , 0xffe0003f , 0x0000003b, 1, 7 }, |
2125 |
|
|
{ "dsra32" , mips64_exec_DSRA32 , 0xffe0003f , 0x0000003f, 1, 7 }, |
2126 |
|
|
{ "dsrav" , mips64_exec_DSRAV , 0xfc0007ff , 0x00000017, 1, 4 }, |
2127 |
|
|
{ "dsrl" , mips64_exec_DSRL , 0xffe0003f , 0x0000003a, 1, 7 }, |
2128 |
|
|
{ "dsrl32" , mips64_exec_DSRL32 , 0xffe0003f , 0x0000003e, 1, 7 }, |
2129 |
|
|
{ "dsrlv" , mips64_exec_DSRLV , 0xfc0007ff , 0x00000016, 1, 4 }, |
2130 |
|
|
{ "dsubu" , mips64_exec_DSUBU , 0xfc0007ff , 0x0000002f, 1, 3 }, |
2131 |
|
|
{ "eret" , mips64_exec_ERET , 0xffffffff , 0x42000018, 0, 1 }, |
2132 |
|
|
{ "j" , mips64_exec_J , 0xfc000000 , 0x08000000, 0, 11 }, |
2133 |
|
|
{ "jal" , mips64_exec_JAL , 0xfc000000 , 0x0c000000, 0, 11 }, |
2134 |
|
|
{ "jalr" , mips64_exec_JALR , 0xfc1f003f , 0x00000009, 0, 15 }, |
2135 |
|
|
{ "jr" , mips64_exec_JR , 0xfc1ff83f , 0x00000008, 0, 13 }, |
2136 |
|
|
{ "lb" , mips64_exec_LB , 0xfc000000 , 0x80000000, 1, 2 }, |
2137 |
|
|
{ "lbu" , mips64_exec_LBU , 0xfc000000 , 0x90000000, 1, 2 }, |
2138 |
|
|
{ "ld" , mips64_exec_LD , 0xfc000000 , 0xdc000000, 1, 2 }, |
2139 |
|
|
{ "ldc1" , mips64_exec_LDC1 , 0xfc000000 , 0xd4000000, 1, 3 }, |
2140 |
|
|
{ "ldl" , mips64_exec_LDL , 0xfc000000 , 0x68000000, 1, 2 }, |
2141 |
|
|
{ "ldr" , mips64_exec_LDR , 0xfc000000 , 0x6c000000, 1, 2 }, |
2142 |
|
|
{ "lh" , mips64_exec_LH , 0xfc000000 , 0x84000000, 1, 2 }, |
2143 |
|
|
{ "lhu" , mips64_exec_LHU , 0xfc000000 , 0x94000000, 1, 2 }, |
2144 |
|
|
{ "ll" , mips64_exec_LL , 0xfc000000 , 0xc0000000, 1, 2 }, |
2145 |
|
|
{ "lui" , mips64_exec_LUI , 0xffe00000 , 0x3c000000, 1, 16 }, |
2146 |
|
|
{ "lw" , mips64_exec_LW , 0xfc000000 , 0x8c000000, 1, 2 }, |
2147 |
|
|
{ "lwl" , mips64_exec_LWL , 0xfc000000 , 0x88000000, 1, 2 }, |
2148 |
|
|
{ "lwr" , mips64_exec_LWR , 0xfc000000 , 0x98000000, 1, 2 }, |
2149 |
|
|
{ "lwu" , mips64_exec_LWU , 0xfc000000 , 0x9c000000, 1, 2 }, |
2150 |
|
|
{ "mfc0" , mips64_exec_MFC0 , 0xffe007ff , 0x40000000, 1, 18 }, |
2151 |
|
|
{ "mfc0_1" , mips64_exec_CFC0 , 0xffe007ff , 0x40000001, 1, 19 }, |
2152 |
|
|
{ "mfc1" , mips64_exec_MFC1 , 0xffe007ff , 0x44000000, 1, 19 }, |
2153 |
|
|
{ "mfhi" , mips64_exec_MFHI , 0xffff07ff , 0x00000010, 1, 14 }, |
2154 |
|
|
{ "mflo" , mips64_exec_MFLO , 0xffff07ff , 0x00000012, 1, 14 }, |
2155 |
|
|
{ "mtc0" , mips64_exec_MTC0 , 0xffe007ff , 0x40800000, 1, 18 }, |
2156 |
|
|
{ "mtc1" , mips64_exec_MTC1 , 0xffe007ff , 0x44800000, 1, 19 }, |
2157 |
|
|
{ "mthi" , mips64_exec_MTHI , 0xfc1fffff , 0x00000011, 1, 13 }, |
2158 |
|
|
{ "mtlo" , mips64_exec_MTLO , 0xfc1fffff , 0x00000013, 1, 13 }, |
2159 |
|
|
{ "mul" , mips64_exec_MUL , 0xfc0007ff , 0x70000002, 1, 4 }, |
2160 |
|
|
{ "mult" , mips64_exec_MULT , 0xfc00ffff , 0x00000018, 1, 17 }, |
2161 |
|
|
{ "multu" , mips64_exec_MULTU , 0xfc00ffff , 0x00000019, 1, 17 }, |
2162 |
|
|
{ "nop" , mips64_exec_NOP , 0xffffffff , 0x00000000, 1, 1 }, |
2163 |
|
|
{ "nor" , mips64_exec_NOR , 0xfc0007ff , 0x00000027, 1, 3 }, |
2164 |
|
|
{ "or" , mips64_exec_OR , 0xfc0007ff , 0x00000025, 1, 3 }, |
2165 |
|
|
{ "ori" , mips64_exec_ORI , 0xfc000000 , 0x34000000, 1, 5 }, |
2166 |
|
|
{ "pref" , mips64_exec_PREF , 0xfc000000 , 0xcc000000, 1, 0 }, |
2167 |
|
|
{ "prefi" , mips64_exec_PREFI , 0xfc0007ff , 0x4c00000f, 1, 0 }, |
2168 |
|
|
{ "sb" , mips64_exec_SB , 0xfc000000 , 0xa0000000, 1, 2 }, |
2169 |
|
|
{ "sc" , mips64_exec_SC , 0xfc000000 , 0xe0000000, 1, 2 }, |
2170 |
|
|
{ "sd" , mips64_exec_SD , 0xfc000000 , 0xfc000000, 1, 2 }, |
2171 |
|
|
{ "sdc1" , mips64_exec_SDC1 , 0xfc000000 , 0xf4000000, 1, 3 }, |
2172 |
|
|
{ "sdl" , mips64_exec_SDL , 0xfc000000 , 0xb0000000, 1, 2 }, |
2173 |
|
|
{ "sdr" , mips64_exec_SDR , 0xfc000000 , 0xb4000000, 1, 2 }, |
2174 |
|
|
{ "sh" , mips64_exec_SH , 0xfc000000 , 0xa4000000, 1, 2 }, |
2175 |
|
|
{ "sll" , mips64_exec_SLL , 0xffe0003f , 0x00000000, 1, 7 }, |
2176 |
|
|
{ "sllv" , mips64_exec_SLLV , 0xfc0007ff , 0x00000004, 1, 4 }, |
2177 |
|
|
{ "slt" , mips64_exec_SLT , 0xfc0007ff , 0x0000002a, 1, 3 }, |
2178 |
|
|
{ "slti" , mips64_exec_SLTI , 0xfc000000 , 0x28000000, 1, 5 }, |
2179 |
|
|
{ "sltiu" , mips64_exec_SLTIU , 0xfc000000 , 0x2c000000, 1, 5 }, |
2180 |
|
|
{ "sltu" , mips64_exec_SLTU , 0xfc0007ff , 0x0000002b, 1, 3 }, |
2181 |
|
|
{ "sra" , mips64_exec_SRA , 0xffe0003f , 0x00000003, 1, 7 }, |
2182 |
|
|
{ "srav" , mips64_exec_SRAV , 0xfc0007ff , 0x00000007, 1, 4 }, |
2183 |
|
|
{ "srl" , mips64_exec_SRL , 0xffe0003f , 0x00000002, 1, 7 }, |
2184 |
|
|
{ "srlv" , mips64_exec_SRLV , 0xfc0007ff , 0x00000006, 1, 4 }, |
2185 |
|
|
{ "sub" , mips64_exec_SUB , 0xfc0007ff , 0x00000022, 1, 3 }, |
2186 |
|
|
{ "subu" , mips64_exec_SUBU , 0xfc0007ff , 0x00000023, 1, 3 }, |
2187 |
|
|
{ "sw" , mips64_exec_SW , 0xfc000000 , 0xac000000, 1, 2 }, |
2188 |
|
|
{ "swl" , mips64_exec_SWL , 0xfc000000 , 0xa8000000, 1, 2 }, |
2189 |
|
|
{ "swr" , mips64_exec_SWR , 0xfc000000 , 0xb8000000, 1, 2 }, |
2190 |
|
|
{ "sync" , mips64_exec_SYNC , 0xfffff83f , 0x0000000f, 1, 1 }, |
2191 |
|
|
{ "syscall", mips64_exec_SYSCALL , 0xfc00003f , 0x0000000c, 1, 1 }, |
2192 |
|
|
{ "teq" , mips64_exec_TEQ , 0xfc00003f , 0x00000034, 1, 17 }, |
2193 |
|
|
{ "teqi" , mips64_exec_TEQI , 0xfc1f0000 , 0x040c0000, 1, 20 }, |
2194 |
|
|
{ "tlbp" , mips64_exec_TLBP , 0xffffffff , 0x42000008, 1, 1 }, |
2195 |
|
|
{ "tlbr" , mips64_exec_TLBR , 0xffffffff , 0x42000001, 1, 1 }, |
2196 |
|
|
{ "tlbwi" , mips64_exec_TLBWI , 0xffffffff , 0x42000002, 1, 1 }, |
2197 |
|
|
{ "tlbwr" , mips64_exec_TLBWR , 0xffffffff , 0x42000006, 1, 1 }, |
2198 |
|
|
{ "xor" , mips64_exec_XOR , 0xfc0007ff , 0x00000026, 1, 3 }, |
2199 |
|
|
{ "xori" , mips64_exec_XORI , 0xfc000000 , 0x38000000, 1, 5 }, |
2200 |
dpavlin |
8 |
{ "unknown", mips64_exec_unknown , 0x00000000 , 0x00000000, 1, 0 }, |
2201 |
dpavlin |
1 |
{ NULL , NULL , 0x00000000 , 0x00000000, 1, 0 }, |
2202 |
|
|
}; |
2203 |
|
|
|
2204 |
|
|
#endif |