175 |
/* TLB masks and shifts */ |
/* TLB masks and shifts */ |
176 |
#define MIPS_TLB_PAGE_MASK 0x01ffe000 |
#define MIPS_TLB_PAGE_MASK 0x01ffe000 |
177 |
#define MIPS_TLB_PAGE_SHIFT 13 |
#define MIPS_TLB_PAGE_SHIFT 13 |
178 |
#define MIPS_TLB_VPN2_MASK 0xffffffffffffe000ULL |
#define MIPS_TLB_VPN2_MASK_32 0xffffe000ULL |
179 |
|
#define MIPS_TLB_VPN2_MASK_64 0xc00000ffffffe000ULL |
180 |
#define MIPS_TLB_PFN_MASK 0x3fffffc0 |
#define MIPS_TLB_PFN_MASK 0x3fffffc0 |
181 |
#define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */ |
#define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */ |
182 |
#define MIPS_TLB_G_MASK 0x00001000 /* "Global" in EntryHi */ |
#define MIPS_TLB_G_MASK 0x00001000 /* "Global" in EntryHi */ |
372 |
mts64_entry_t *next,**pprev; |
mts64_entry_t *next,**pprev; |
373 |
}; |
}; |
374 |
|
|
375 |
/* MTS64 chunk forward declaration */ |
/* MTS32 entry */ |
376 |
|
typedef struct mts32_entry mts32_entry_t; |
377 |
|
struct mts32_entry { |
378 |
|
m_uint32_t start; |
379 |
|
m_iptr_t action; |
380 |
|
m_uint32_t mask; |
381 |
|
m_uint32_t phys_page; |
382 |
|
mts32_entry_t **pself; |
383 |
|
mts32_entry_t *next,**pprev; |
384 |
|
}; |
385 |
|
|
386 |
|
/* MTS chunk forward declaration */ |
387 |
typedef struct mts64_chunk mts64_chunk_t; |
typedef struct mts64_chunk mts64_chunk_t; |
388 |
|
typedef struct mts32_chunk mts32_chunk_t; |
389 |
|
|
390 |
|
/* Maximum results for idle pc */ |
391 |
|
#define MIPS64_IDLE_PC_MAX_RES 10 |
392 |
|
|
393 |
|
/* Idle PC hash item */ |
394 |
|
struct mips64_idle_pc { |
395 |
|
m_uint64_t pc; |
396 |
|
u_int count; |
397 |
|
}; |
398 |
|
|
399 |
/* MIPS CPU definition */ |
/* MIPS CPU definition */ |
400 |
struct cpu_mips { |
struct cpu_mips { |
401 |
/* MTS 1st level array */ |
/* MTS 1st level array */ |
402 |
void *mts_l1_ptr; |
void *mts_l1_ptr; |
403 |
|
|
404 |
/* MTS64 cache */ |
/* MTS32/MTS64 caches */ |
405 |
mts64_entry_t **mts64_cache; |
void **mts_cache; |
406 |
|
|
407 |
/* Virtual version of CP0 Compare Register */ |
/* Virtual version of CP0 Compare Register */ |
408 |
m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg; |
m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg; |
431 |
/* FPU (CP1) */ |
/* FPU (CP1) */ |
432 |
mips_cp1_t fpu; |
mips_cp1_t fpu; |
433 |
|
|
434 |
/* MTS32 array free list */ |
/* Address bus mask for physical addresses */ |
|
void *mts32_l2_free_list; |
|
|
|
|
|
/* Address bus mask */ |
|
435 |
m_uint64_t addr_bus_mask; |
m_uint64_t addr_bus_mask; |
436 |
|
|
437 |
/* IRQ counters and cause */ |
/* IRQ counters and cause */ |
451 |
|
|
452 |
/* "Idle" loop management */ |
/* "Idle" loop management */ |
453 |
volatile m_uint64_t idle_pc; |
volatile m_uint64_t idle_pc; |
454 |
u_int idle_max,idle_sleep_time; |
u_int idle_count,idle_max,idle_sleep_time; |
455 |
pthread_mutex_t idle_mutex; |
pthread_mutex_t idle_mutex; |
456 |
pthread_cond_t idle_cond; |
pthread_cond_t idle_cond; |
457 |
|
|
494 |
|
|
495 |
void (*mts_rebuild)(cpu_mips_t *cpu); |
void (*mts_rebuild)(cpu_mips_t *cpu); |
496 |
|
|
497 |
/* MTS64 chunk list */ |
void (*mts_shutdown)(cpu_mips_t *cpu); |
498 |
mts64_chunk_t *mts64_chunk_list; |
|
499 |
mts64_chunk_t *mts64_chunk_free_list; |
/* Show MTS statistics */ |
500 |
mts64_entry_t *mts64_entry_free_list; |
void (*mts_show_stats)(cpu_mips_t *cpu); |
501 |
|
|
502 |
|
/* MTS chunk list */ |
503 |
|
void *mts_chunk_list; |
504 |
|
void *mts_chunk_free_list; |
505 |
|
void *mts_entry_free_list; |
506 |
|
|
507 |
/* MTS64 cache statistics */ |
/* MTS cache statistics */ |
508 |
m_uint64_t mts64_misses,mts64_lookups; |
m_uint64_t mts_misses,mts_lookups; |
509 |
|
|
510 |
/* Reverse map for MTS64 */ |
/* Reverse map for MTS64 */ |
511 |
mts64_entry_t *mts64_rmap[MIPS64_TLB_MAX_ENTRIES]; |
void *mts_rmap[MIPS64_TLB_MAX_ENTRIES]; |
512 |
|
|
513 |
/* JIT flush method */ |
/* JIT flush method */ |
514 |
u_int jit_flush_method; |
u_int jit_flush_method; |
519 |
/* Fast memory operations use */ |
/* Fast memory operations use */ |
520 |
u_int fast_memop; |
u_int fast_memop; |
521 |
|
|
522 |
|
/* Address mode (32 or 64 bits) */ |
523 |
|
u_int addr_mode; |
524 |
|
|
525 |
/* Current exec page (non-JIT) info */ |
/* Current exec page (non-JIT) info */ |
526 |
m_uint64_t njm_exec_page; |
m_uint64_t njm_exec_page; |
527 |
mips_insn_t *njm_exec_ptr; |
mips_insn_t *njm_exec_ptr; |
537 |
m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS]; |
m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS]; |
538 |
u_int breakpoints_enabled; |
u_int breakpoints_enabled; |
539 |
|
|
540 |
|
/* Idle PC proposal */ |
541 |
|
struct mips64_idle_pc idle_pc_prop[MIPS64_IDLE_PC_MAX_RES]; |
542 |
|
u_int idle_pc_prop_count; |
543 |
|
|
544 |
/* Symtrace */ |
/* Symtrace */ |
545 |
int sym_trace; |
int sym_trace; |
546 |
rbtree_tree *sym_tree; |
rbtree_tree *sym_tree; |
633 |
/* Virtual breakpoint */ |
/* Virtual breakpoint */ |
634 |
fastcall void mips64_run_breakpoint(cpu_mips_t *cpu); |
fastcall void mips64_run_breakpoint(cpu_mips_t *cpu); |
635 |
|
|
636 |
|
/* Add a virtual breakpoint */ |
637 |
|
int mips64_add_breakpoint(cpu_mips_t *cpu,m_uint64_t pc); |
638 |
|
|
639 |
|
/* Remove a virtual breakpoint */ |
640 |
|
void mips64_remove_breakpoint(cpu_mips_t *cpu,m_uint64_t pc); |
641 |
|
|
642 |
/* Debugging for register-jump to address 0 */ |
/* Debugging for register-jump to address 0 */ |
643 |
fastcall void mips64_debug_jr0(cpu_mips_t *cpu); |
fastcall void mips64_debug_jr0(cpu_mips_t *cpu); |
644 |
|
|
658 |
int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr); |
int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr); |
659 |
|
|
660 |
/* Load an ELF image into the simulated memory */ |
/* Load an ELF image into the simulated memory */ |
661 |
int mips64_load_elf_image(cpu_mips_t *cpu,char *filename, |
int mips64_load_elf_image(cpu_mips_t *cpu,char *filename,int skip_load, |
662 |
m_uint32_t *entry_point); |
m_uint32_t *entry_point); |
663 |
|
|
664 |
/* Symbol lookup */ |
/* Symbol lookup */ |