/[dynamips]/upstream/dynamips-0.2.8-RC1/dev_mueslix.c
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upstream/dynamips-0.2.7/dev_mueslix.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/dev_mueslix.c revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 144  struct mueslix_channel { Line 144  struct mueslix_channel {
144     /* Channel status (0=disabled) */     /* Channel status (0=disabled) */
145     u_int status;     u_int status;
146    
147       /* CRC control register */
148       u_int crc_ctrl_reg;
149    
150       /* CRC size */
151       u_int crc_size;
152    
153     /* NetIO descriptor */     /* NetIO descriptor */
154     netio_desc_t *nio;     netio_desc_t *nio;
155    
# Line 243  void dev_mueslix_chan_access(cpu_gen_t * Line 249  void dev_mueslix_chan_access(cpu_gen_t *
249                               m_uint64_t *data)                               m_uint64_t *data)
250  {  {
251     switch(offset) {     switch(offset) {
252          case 0x00: /* CRC control register ? */
253             if (op_type == MTS_READ) {
254                *data = channel->crc_ctrl_reg;
255             } else {
256                channel->crc_ctrl_reg = *data;
257                
258                switch(channel->crc_ctrl_reg) {
259                   case 0x08:
260                   case 0x0a:
261                      channel->crc_size = channel->crc_ctrl_reg - 0x06;
262                      break;
263    
264                   default:
265                      MUESLIX_LOG(channel->parent,"channel %u: unknown value "
266                                  "for CRC ctrl reg 0x%4.4x\n",
267                                  channel->id,channel->crc_ctrl_reg);
268    
269                      channel->crc_size = 2;
270                }
271                MUESLIX_LOG(channel->parent,
272                            "channel %u: CRC size set to 0x%4.4x\n",
273                            channel->id,channel->crc_size);
274             }
275             break;
276    
277        case 0x60: /* signals ? */        case 0x60: /* signals ? */
278           if ((op_type == MTS_READ) && (channel->nio != NULL))           if ((op_type == MTS_READ) && (channel->nio != NULL))
279              *data = 0xFFFFFFFF;              *data = 0xFFFFFFFF;
# Line 613  static void dev_mueslix_receive_pkt(stru Line 644  static void dev_mueslix_receive_pkt(stru
644        /* We have finished if the complete packet has been stored */        /* We have finished if the complete packet has been stored */
645        if (tot_len == 0) {        if (tot_len == 0) {
646           rxdc->rdes[0] = MUESLIX_RXDESC_LS;           rxdc->rdes[0] = MUESLIX_RXDESC_LS;
647           rxdc->rdes[0] |= cp_len;           rxdc->rdes[0] |= cp_len + channel->crc_size + 1;
648    
649           if (i != 0)           if (i != 0)
650              physmem_copy_u32_to_vm(d->vm,channel->rx_current,rxdc->rdes[0]);              physmem_copy_u32_to_vm(d->vm,channel->rx_current,rxdc->rdes[0]);
# Line 775  static int dev_mueslix_handle_txring_sin Line 806  static int dev_mueslix_handle_txring_sin
806        /* Be sure that we have length not null */        /* Be sure that we have length not null */
807        if (clen != 0) {        if (clen != 0) {
808           //printf("pkt_ptr = %p, ptxd->tdes[1] = 0x%x, clen = %d\n",           //printf("pkt_ptr = %p, ptxd->tdes[1] = 0x%x, clen = %d\n",
809           //pkt_ptr, ptxd->tdes[1], clen);           //       pkt_ptr, ptxd->tdes[1], clen);
810           physmem_copy_from_vm(d->vm,pkt_ptr,ptxd->tdes[1],clen);           physmem_copy_from_vm(d->vm,pkt_ptr,ptxd->tdes[1],clen);
811        }        }
812    
# Line 806  static int dev_mueslix_handle_txring_sin Line 837  static int dev_mueslix_handle_txring_sin
837    
838        pad = ptxd->tdes[0] & MUESLIX_TXDESC_PAD;        pad = ptxd->tdes[0] & MUESLIX_TXDESC_PAD;
839        pad >>= MUESLIX_TXDESC_PAD_SHIFT;        pad >>= MUESLIX_TXDESC_PAD_SHIFT;
840        tot_len += (pad - 1) & 0x03;        tot_len -= (4 - pad) & 0x03;
841    
842        /* send it on wire */        /* send it on wire */
843        netio_send(channel->nio,pkt,tot_len);        netio_send(channel->nio,pkt,tot_len);
844     }     }
# Line 892  dev_mueslix_init(vm_instance_t *vm,char Line 923  dev_mueslix_init(vm_instance_t *vm,char
923     pthread_mutex_init(&d->lock,NULL);     pthread_mutex_init(&d->lock,NULL);
924     d->chip_mode = chip_mode;     d->chip_mode = chip_mode;
925    
926     for(i=0;i<MUESLIX_NR_CHANNELS;i++)     for(i=0;i<MUESLIX_NR_CHANNELS;i++) {
927        d->channel[i].id = i;        d->channel[i].id = i;
928          d->channel[i].parent = d;
929       }
930    
931     /* Add as PCI device */     /* Add as PCI device */
932     pci_dev = pci_dev_add(pci_bus,name,     pci_dev = pci_dev_add(pci_bus,name,
# Line 956  int dev_mueslix_set_nio(struct mueslix_d Line 989  int dev_mueslix_set_nio(struct mueslix_d
989    
990     /* define the new NIO */     /* define the new NIO */
991     channel->nio = nio;     channel->nio = nio;
    channel->parent = d;  
992     channel->tx_tid = ptask_add((ptask_callback)dev_mueslix_handle_txring,     channel->tx_tid = ptask_add((ptask_callback)dev_mueslix_handle_txring,
993                                 channel,NULL);                                 channel,NULL);
994     netio_rxl_add(nio,(netio_rx_handler_t)dev_mueslix_handle_rxring,     netio_rxl_add(nio,(netio_rx_handler_t)dev_mueslix_handle_rxring,

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