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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2007 Christophe Fillot (cf@utc.fr) |
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* |
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* Cisco C6k-MSFC1 I/O FPGA: |
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* - Simulates a NMC93C56 Serial EEPROM. |
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* - Simulates a DALLAS DS1620 for Temperature Sensors. |
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* - Simulates console and AUX ports (SCN2681). |
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* |
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* This is very similar to c7200 platform. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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#include "nmc93cX6.h" |
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#include "ds1620.h" |
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#include "dev_msfc1.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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#define DEBUG_LED 0 |
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#define DEBUG_IO_CTL 0 |
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#define DEBUG_ENVM 0 |
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/* DUART RX/TX status (SRA/SRB) */ |
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#define DUART_RX_READY 0x01 |
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#define DUART_TX_READY 0x04 |
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/* DUART RX/TX Interrupt Status/Mask */ |
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#define DUART_TXRDYA 0x01 |
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#define DUART_RXRDYA 0x02 |
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#define DUART_TXRDYB 0x10 |
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#define DUART_RXRDYB 0x20 |
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/* Definitions for CPU and Midplane Serial EEPROMs */ |
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#define DO2_DATA_OUT_MIDPLANE 7 |
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#define DO1_DATA_OUT_CPU 6 |
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#define CS2_CHIP_SEL_MIDPLANE 5 |
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#define SK2_CLOCK_MIDPLANE 4 |
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#define DI2_DATA_IN_MIDPLANE 3 |
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#define CS1_CHIP_SEL_CPU 2 |
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#define SK1_CLOCK_CPU 1 |
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#define DI1_DATA_IN_CPU 0 |
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/* Pack the NVRAM */ |
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#define NVRAM_PACKED 0x04 |
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/* 2 temperature sensors in a MSFC1: chassis inlet and oulet */ |
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#define MSFC1_TEMP_SENSORS 2 |
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#define MSFC1_DEFAULT_TEMP 22 /* default temperature: 22°C */ |
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/* IO FPGA structure */ |
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struct iofpga_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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msfc1_t *router; |
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/* Lock test */ |
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pthread_mutex_t lock; |
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/* Periodic task to trigger dummy DUART IRQ */ |
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ptask_id_t duart_irq_tid; |
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/* DUART & Console Management */ |
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u_int duart_isr,duart_imr,duart_irq_seq; |
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/* IO control register */ |
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u_int io_ctrl_reg; |
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/* Temperature Control */ |
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u_int temp_cfg_reg[MSFC1_TEMP_SENSORS]; |
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u_int temp_deg_reg[MSFC1_TEMP_SENSORS]; |
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u_int temp_clk_low; |
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u_int temp_cmd; |
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u_int temp_cmd_pos; |
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u_int temp_data; |
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u_int temp_data_pos; |
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/* Voltages */ |
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u_int mux; |
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}; |
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#define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock) |
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#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
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/* CPU EEPROM definition */ |
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static const struct nmc93cX6_eeprom_def eeprom_cpu_def = { |
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SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
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DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
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}; |
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/* Midplane EEPROM definition */ |
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static const struct nmc93cX6_eeprom_def eeprom_midplane_def = { |
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SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
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DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
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}; |
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/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
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static const struct nmc93cX6_group eeprom_cpu_midplane = { |
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EEPROM_TYPE_NMC93C56, 2, 0, "CPU and Midplane EEPROM", 0, |
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{ &eeprom_cpu_def, &eeprom_midplane_def }, |
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}; |
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/* Reset DS1620 */ |
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static void temp_reset(struct iofpga_data *d) |
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{ |
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d->temp_cmd_pos = 0; |
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d->temp_cmd = 0; |
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d->temp_data_pos = 0; |
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d->temp_data = 0; |
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} |
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/* Write the temperature control data */ |
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static void temp_write_ctrl(struct iofpga_data *d,u_char val) |
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{ |
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switch(val) { |
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case DS1620_RESET_ON: |
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temp_reset(d); |
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break; |
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case DS1620_CLK_LOW: |
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d->temp_clk_low = 1; |
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break; |
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case DS1620_CLK_HIGH: |
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d->temp_clk_low = 0; |
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break; |
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} |
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} |
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/* Read a temperature control data */ |
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static u_int temp_read_data(struct iofpga_data *d) |
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{ |
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u_int i,data = 0; |
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switch(d->temp_cmd) { |
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case DS1620_READ_CONFIG: |
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for(i=0;i<MSFC1_TEMP_SENSORS;i++) |
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data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i; |
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d->temp_data_pos++; |
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if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE) |
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temp_reset(d); |
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break; |
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case DS1620_READ_TEMP: |
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for(i=0;i<MSFC1_TEMP_SENSORS;i++) |
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data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i; |
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d->temp_data_pos++; |
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if (d->temp_data_pos == DS1620_DATA_READ_SIZE) |
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temp_reset(d); |
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break; |
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default: |
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vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n", |
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d->temp_cmd); |
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} |
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return(data); |
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} |
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/* Write the temperature data write register */ |
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static void temp_write_data(struct iofpga_data *d,u_char val) |
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{ |
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if (val == DS1620_ENABLE_READ) { |
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d->temp_data_pos = 0; |
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return; |
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} |
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if (!d->temp_clk_low) |
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return; |
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/* Write a command */ |
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if (d->temp_cmd_pos < DS1620_WRITE_SIZE) |
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{ |
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if (val == DS1620_DATA_HIGH) |
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d->temp_cmd |= 1 << d->temp_cmd_pos; |
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d->temp_cmd_pos++; |
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if (d->temp_cmd_pos == DS1620_WRITE_SIZE) { |
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switch(d->temp_cmd) { |
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case DS1620_START_CONVT: |
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//printf("temp_sensors: IOS enabled continuous monitoring.\n"); |
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temp_reset(d); |
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break; |
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case DS1620_READ_CONFIG: |
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case DS1620_READ_TEMP: |
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break; |
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default: |
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vm_log(d->router->vm,"IO_FPGA", |
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"temp_sensors: IOS sent command 0x%x.\n", |
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d->temp_cmd); |
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} |
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} |
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} |
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else |
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{ |
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if (val == DS1620_DATA_HIGH) |
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d->temp_data |= 1 << d->temp_data_pos; |
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d->temp_data_pos++; |
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} |
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} |
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/* Console port input */ |
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static void tty_con_input(vtty_t *vtty) |
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{ |
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struct iofpga_data *d = vtty->priv_data; |
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IOFPGA_LOCK(d); |
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if (d->duart_imr & DUART_RXRDYA) { |
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d->duart_isr |= DUART_RXRDYA; |
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vm_set_irq(d->router->vm,MSFC1_DUART_IRQ); |
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} |
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IOFPGA_UNLOCK(d); |
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} |
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/* AUX port input */ |
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static void tty_aux_input(vtty_t *vtty) |
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{ |
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struct iofpga_data *d = vtty->priv_data; |
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IOFPGA_LOCK(d); |
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if (d->duart_imr & DUART_RXRDYB) { |
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d->duart_isr |= DUART_RXRDYB; |
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vm_set_irq(d->router->vm,MSFC1_DUART_IRQ); |
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} |
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IOFPGA_UNLOCK(d); |
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} |
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/* IRQ trickery for Console and AUX ports */ |
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static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg) |
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{ |
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u_int mask; |
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IOFPGA_LOCK(d); |
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d->duart_irq_seq++; |
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if (d->duart_irq_seq == 2) { |
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mask = DUART_TXRDYA|DUART_TXRDYB; |
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if (d->duart_imr & mask) { |
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d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB; |
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vm_set_irq(d->router->vm,MSFC1_DUART_IRQ); |
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} |
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d->duart_irq_seq = 0; |
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} |
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IOFPGA_UNLOCK(d); |
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return(0); |
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} |
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/* |
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* dev_msfc1_iofpga_access() |
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*/ |
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void *dev_msfc1_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct iofpga_data *d = dev->priv_data; |
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vm_instance_t *vm = d->router->vm; |
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u_char odata; |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n", |
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offset,cpu_get_pc(cpu)); |
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} else { |
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cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n", |
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offset,cpu_get_pc(cpu),*data); |
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} |
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#endif |
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IOFPGA_LOCK(d); |
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switch(offset) { |
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case 0x294: |
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/* |
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* Unknown, seen in 12.4(6)T, and seems to be read at each |
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* network interrupt. |
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*/ |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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break; |
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/* I/O control register */ |
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case 0x204: |
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if (op_type == MTS_WRITE) { |
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#if DEBUG_IO_CTL |
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vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data); |
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#endif |
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d->io_ctrl_reg = *data; |
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} else { |
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*data = d->io_ctrl_reg; |
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*data |= NVRAM_PACKED; /* Packed NVRAM */ |
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} |
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break; |
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/* CPU/Midplane EEPROMs */ |
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case 0x21c: |
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if (op_type == MTS_WRITE) |
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nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data)); |
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else |
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*data = nmc93cX6_read(&d->router->sys_eeprom_g1); |
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break; |
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/* Watchdog */ |
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case 0x234: |
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break; |
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340 |
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/* |
341 |
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* FPGA release/presence ? Flash SIMM size: |
342 |
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* 0x0001: 2048K Flash (2 banks) |
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* 0x0504: 8192K Flash (2 banks) |
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* 0x0704: 16384K Flash (2 banks) |
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* 0x0904: 32768K Flash (2 banks) |
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* 0x0B04: 65536K Flash (2 banks) |
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* 0x2001: 1024K Flash (1 bank) |
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* 0x2504: 4096K Flash (1 bank) |
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* 0x2704: 8192K Flash (1 bank) |
350 |
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* 0x2904: 16384K Flash (1 bank) |
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* 0x2B04: 32768K Flash (1 bank) |
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* |
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* Number of Flash SIMM banks + size. |
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* Touching some lower bits causes problems with environmental monitor. |
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* |
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* It is displayed by command "sh bootflash: chips" |
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*/ |
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case 0x23c: |
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if (op_type == MTS_READ) |
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*data = 0x2704; |
361 |
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break; |
362 |
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363 |
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/* LEDs */ |
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case 0x244: |
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#if DEBUG_LED |
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vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n", |
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*data,(~*data) & 0x0F); |
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#endif |
369 |
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break; |
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371 |
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/* ==== DUART SCN2681 (console/aux) ==== */ |
372 |
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case 0x404: /* Mode Register A (MRA) */ |
373 |
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break; |
374 |
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375 |
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case 0x40c: /* Status Register A (SRA) */ |
376 |
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if (op_type == MTS_READ) { |
377 |
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odata = 0; |
378 |
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379 |
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if (vtty_is_char_avail(vm->vtty_con)) |
380 |
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odata |= DUART_RX_READY; |
381 |
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382 |
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odata |= DUART_TX_READY; |
383 |
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384 |
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vm_clear_irq(vm,MSFC1_DUART_IRQ); |
385 |
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*data = odata; |
386 |
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} |
387 |
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break; |
388 |
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389 |
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case 0x414: /* Command Register A (CRA) */ |
390 |
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/* Disable TX = High */ |
391 |
|
|
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
392 |
|
|
vm->vtty_con->managed_flush = TRUE; |
393 |
|
|
vtty_flush(vm->vtty_con); |
394 |
|
|
} |
395 |
|
|
break; |
396 |
|
|
|
397 |
|
|
case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */ |
398 |
|
|
if (op_type == MTS_WRITE) { |
399 |
|
|
vtty_put_char(vm->vtty_con,(char)*data); |
400 |
|
|
d->duart_isr &= ~DUART_TXRDYA; |
401 |
|
|
} else { |
402 |
|
|
*data = vtty_get_char(vm->vtty_con); |
403 |
|
|
d->duart_isr &= ~DUART_RXRDYA; |
404 |
|
|
} |
405 |
|
|
break; |
406 |
|
|
|
407 |
|
|
case 0x424: /* WRITE: Aux Control Register (ACR) */ |
408 |
|
|
break; |
409 |
|
|
|
410 |
|
|
case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */ |
411 |
|
|
if (op_type == MTS_WRITE) { |
412 |
|
|
d->duart_imr = *data; |
413 |
|
|
} else |
414 |
|
|
*data = d->duart_isr; |
415 |
|
|
break; |
416 |
|
|
|
417 |
|
|
case 0x434: /* Counter/Timer Upper Value (CTU) */ |
418 |
|
|
case 0x43c: /* Counter/Timer Lower Value (CTL) */ |
419 |
|
|
case 0x444: /* Mode Register B (MRB) */ |
420 |
|
|
break; |
421 |
|
|
|
422 |
|
|
case 0x44c: /* Status Register B (SRB) */ |
423 |
|
|
if (op_type == MTS_READ) { |
424 |
|
|
odata = 0; |
425 |
|
|
|
426 |
|
|
if (vtty_is_char_avail(vm->vtty_aux)) |
427 |
|
|
odata |= DUART_RX_READY; |
428 |
|
|
|
429 |
|
|
odata |= DUART_TX_READY; |
430 |
|
|
|
431 |
|
|
//vm_clear_irq(vm,MSFC1_DUART_IRQ); |
432 |
|
|
*data = odata; |
433 |
|
|
} |
434 |
|
|
break; |
435 |
|
|
|
436 |
|
|
case 0x454: /* Command Register B (CRB) */ |
437 |
|
|
/* Disable TX = High */ |
438 |
|
|
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
439 |
|
|
vm->vtty_aux->managed_flush = TRUE; |
440 |
|
|
vtty_flush(vm->vtty_aux); |
441 |
|
|
} |
442 |
|
|
break; |
443 |
|
|
|
444 |
|
|
case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */ |
445 |
|
|
if (op_type == MTS_WRITE) { |
446 |
|
|
vtty_put_char(vm->vtty_aux,(char)*data); |
447 |
|
|
d->duart_isr &= ~DUART_TXRDYA; |
448 |
|
|
} else { |
449 |
|
|
*data = vtty_get_char(vm->vtty_aux); |
450 |
|
|
d->duart_isr &= ~DUART_RXRDYB; |
451 |
|
|
} |
452 |
|
|
break; |
453 |
|
|
|
454 |
|
|
case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */ |
455 |
|
|
case 0x474: /* READ: Start Counter Command; */ |
456 |
|
|
/* WRITE: Set Output Port Bits Command */ |
457 |
|
|
case 0x47c: /* WRITE: Reset Output Port Bits Command */ |
458 |
|
|
break; |
459 |
|
|
|
460 |
|
|
/* ==== DS 1620 (temp sensors) ==== */ |
461 |
|
|
case 0x20c: /* Temperature Control */ |
462 |
|
|
if (op_type == MTS_WRITE) |
463 |
|
|
temp_write_ctrl(d,*data); |
464 |
|
|
break; |
465 |
|
|
|
466 |
|
|
case 0x214: /* Temperature data write */ |
467 |
|
|
if (op_type == MTS_WRITE) { |
468 |
|
|
temp_write_data(d,*data); |
469 |
|
|
d->mux = *data; |
470 |
|
|
} |
471 |
|
|
break; |
472 |
|
|
|
473 |
|
|
case 0x22c: /* Temperature data read */ |
474 |
|
|
if (op_type == MTS_READ) |
475 |
|
|
*data = temp_read_data(d); |
476 |
|
|
break; |
477 |
|
|
|
478 |
|
|
#if DEBUG_UNKNOWN |
479 |
|
|
default: |
480 |
|
|
if (op_type == MTS_READ) { |
481 |
|
|
cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n", |
482 |
|
|
offset,cpu_get_pc(cpu),op_size); |
483 |
|
|
} else { |
484 |
|
|
cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, " |
485 |
|
|
"pc=0x%llx (size=%u)\n", |
486 |
|
|
offset,*data,cpu_get_pc(cpu),op_size); |
487 |
|
|
} |
488 |
|
|
#endif |
489 |
|
|
} |
490 |
|
|
|
491 |
|
|
IOFPGA_UNLOCK(d); |
492 |
|
|
return NULL; |
493 |
|
|
} |
494 |
|
|
|
495 |
|
|
/* Initialize EEPROM groups */ |
496 |
|
|
void msfc1_init_eeprom_groups(msfc1_t *router) |
497 |
|
|
{ |
498 |
|
|
router->sys_eeprom_g1 = eeprom_cpu_midplane; |
499 |
|
|
router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom; |
500 |
|
|
router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom; |
501 |
|
|
} |
502 |
|
|
|
503 |
|
|
/* Shutdown the IO FPGA device */ |
504 |
|
|
void dev_msfc1_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
505 |
|
|
{ |
506 |
|
|
if (d != NULL) { |
507 |
|
|
IOFPGA_LOCK(d); |
508 |
|
|
vm->vtty_con->read_notifier = NULL; |
509 |
|
|
vm->vtty_aux->read_notifier = NULL; |
510 |
|
|
IOFPGA_UNLOCK(d); |
511 |
|
|
|
512 |
|
|
/* Remove the dummy IRQ periodic task */ |
513 |
|
|
ptask_remove(d->duart_irq_tid); |
514 |
|
|
|
515 |
|
|
/* Remove the device */ |
516 |
|
|
dev_remove(vm,&d->dev); |
517 |
|
|
|
518 |
|
|
/* Free the structure itself */ |
519 |
|
|
free(d); |
520 |
|
|
} |
521 |
|
|
} |
522 |
|
|
|
523 |
|
|
/* |
524 |
|
|
* dev_msfc1_iofpga_init() |
525 |
|
|
*/ |
526 |
|
|
int dev_msfc1_iofpga_init(msfc1_t *router,m_uint64_t paddr,m_uint32_t len) |
527 |
|
|
{ |
528 |
|
|
vm_instance_t *vm = router->vm; |
529 |
|
|
struct iofpga_data *d; |
530 |
|
|
u_int i; |
531 |
|
|
|
532 |
|
|
/* Allocate private data structure */ |
533 |
|
|
if (!(d = malloc(sizeof(*d)))) { |
534 |
|
|
fprintf(stderr,"IO_FPGA: out of memory\n"); |
535 |
|
|
return(-1); |
536 |
|
|
} |
537 |
|
|
|
538 |
|
|
memset(d,0,sizeof(*d)); |
539 |
|
|
|
540 |
|
|
pthread_mutex_init(&d->lock,NULL); |
541 |
|
|
d->router = router; |
542 |
|
|
|
543 |
|
|
for(i=0;i<MSFC1_TEMP_SENSORS;i++) { |
544 |
|
|
d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU; |
545 |
|
|
d->temp_deg_reg[i] = MSFC1_DEFAULT_TEMP * 2; |
546 |
|
|
} |
547 |
|
|
|
548 |
|
|
vm_object_init(&d->vm_obj); |
549 |
|
|
d->vm_obj.name = "io_fpga"; |
550 |
|
|
d->vm_obj.data = d; |
551 |
|
|
d->vm_obj.shutdown = (vm_shutdown_t)dev_msfc1_iofpga_shutdown; |
552 |
|
|
|
553 |
|
|
/* Set device properties */ |
554 |
|
|
dev_init(&d->dev); |
555 |
|
|
d->dev.name = "io_fpga"; |
556 |
|
|
d->dev.phys_addr = paddr; |
557 |
|
|
d->dev.phys_len = len; |
558 |
|
|
d->dev.handler = dev_msfc1_iofpga_access; |
559 |
|
|
d->dev.priv_data = d; |
560 |
|
|
|
561 |
|
|
/* Set console and AUX port notifying functions */ |
562 |
|
|
vm->vtty_con->priv_data = d; |
563 |
|
|
vm->vtty_aux->priv_data = d; |
564 |
|
|
vm->vtty_con->read_notifier = tty_con_input; |
565 |
|
|
vm->vtty_aux->read_notifier = tty_aux_input; |
566 |
|
|
|
567 |
|
|
/* Trigger periodically a dummy IRQ to flush buffers */ |
568 |
|
|
d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq, |
569 |
|
|
d,NULL); |
570 |
|
|
|
571 |
|
|
/* Map this device to the VM */ |
572 |
|
|
vm_bind_device(vm,&d->dev); |
573 |
|
|
vm_object_add(vm,&d->vm_obj); |
574 |
|
|
return(0); |
575 |
|
|
} |