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/* |
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* Cisco router simulation platform. |
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dpavlin |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* Cisco c7200 Midplane FPGA. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "nmc93c46.h" |
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#include "dev_c7200.h" |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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#define DEBUG_OIR 1 |
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/* |
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* Definitions for Port Adapter Status. |
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*/ |
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#define PCI_BAY0_3V_OK 0x00000002 /* IO card 3V */ |
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#define PCI_BAY0_5V_OK 0x00000004 /* IO card 5V */ |
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#define PCI_BAY1_5V_OK 0x00000200 /* Bay 1 5V */ |
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#define PCI_BAY1_3V_OK 0x00000400 /* Bay 1 3V */ |
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#define PCI_BAY2_5V_OK 0x00002000 /* Bay 2 5V */ |
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#define PCI_BAY2_3V_OK 0x00004000 /* Bay 2 3V */ |
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#define PCI_BAY3_5V_OK 0x02000000 /* Bay 3 5V */ |
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#define PCI_BAY3_3V_OK 0x04000000 /* Bay 3 3V */ |
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#define PCI_BAY4_5V_OK 0x00020000 /* Bay 4 5V */ |
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#define PCI_BAY4_3V_OK 0x00040000 /* Bay 4 3V */ |
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#define PCI_BAY5_5V_OK 0x20000000 /* Bay 5 5V */ |
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#define PCI_BAY5_3V_OK 0x40000000 /* Bay 5 3V */ |
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#define PCI_BAY6_5V_OK 0x00200000 /* Bay 6 5V */ |
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#define PCI_BAY6_3V_OK 0x00400000 /* Bay 6 3V */ |
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/* |
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* Definitions for EEPROM access (slots 0,1,3,4) (0x60) |
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*/ |
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#define BAY0_EEPROM_SELECT_BIT 1 |
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#define BAY0_EEPROM_CLOCK_BIT 3 |
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#define BAY0_EEPROM_DIN_BIT 4 |
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#define BAY0_EEPROM_DOUT_BIT 6 |
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#define BAY1_EEPROM_SELECT_BIT 9 |
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#define BAY1_EEPROM_CLOCK_BIT 11 |
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#define BAY1_EEPROM_DIN_BIT 12 |
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#define BAY1_EEPROM_DOUT_BIT 14 |
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#define BAY3_EEPROM_SELECT_BIT 25 |
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#define BAY3_EEPROM_CLOCK_BIT 27 |
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#define BAY3_EEPROM_DIN_BIT 28 |
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#define BAY3_EEPROM_DOUT_BIT 30 |
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#define BAY4_EEPROM_SELECT_BIT 17 |
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#define BAY4_EEPROM_CLOCK_BIT 19 |
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#define BAY4_EEPROM_DIN_BIT 20 |
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#define BAY4_EEPROM_DOUT_BIT 22 |
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/* |
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* Definitions for EEPROM access (slots 2,5,6) (0x68) |
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*/ |
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#define BAY2_EEPROM_SELECT_BIT 9 |
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#define BAY2_EEPROM_CLOCK_BIT 11 |
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#define BAY2_EEPROM_DIN_BIT 12 |
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#define BAY2_EEPROM_DOUT_BIT 14 |
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#define BAY5_EEPROM_SELECT_BIT 25 |
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#define BAY5_EEPROM_CLOCK_BIT 27 |
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#define BAY5_EEPROM_DIN_BIT 28 |
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#define BAY5_EEPROM_DOUT_BIT 30 |
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#define BAY6_EEPROM_SELECT_BIT 17 |
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#define BAY6_EEPROM_CLOCK_BIT 19 |
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#define BAY6_EEPROM_DIN_BIT 20 |
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#define BAY6_EEPROM_DOUT_BIT 22 |
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/* PA Bay EEPROM definitions */ |
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static const struct nmc93c46_eeprom_def eeprom_bay_def[C7200_MAX_PA_BAYS] = { |
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/* Bay 0 */ |
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{ BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT, |
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BAY0_EEPROM_DIN_BIT , BAY0_EEPROM_DOUT_BIT, |
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}, |
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|
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/* Bay 1 */ |
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{ BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT, |
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BAY1_EEPROM_DIN_BIT , BAY1_EEPROM_DOUT_BIT, |
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}, |
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/* Bay 2 */ |
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{ BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT, |
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BAY2_EEPROM_DIN_BIT , BAY2_EEPROM_DOUT_BIT, |
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}, |
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/* Bay 3 */ |
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{ BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT, |
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BAY3_EEPROM_DIN_BIT , BAY3_EEPROM_DOUT_BIT, |
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}, |
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/* Bay 4 */ |
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{ BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT, |
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BAY4_EEPROM_DIN_BIT , BAY4_EEPROM_DOUT_BIT, |
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}, |
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/* Bay 5 */ |
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{ BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT, |
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BAY5_EEPROM_DIN_BIT , BAY5_EEPROM_DOUT_BIT, |
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}, |
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/* Bay 6 */ |
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{ BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT, |
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BAY6_EEPROM_DIN_BIT , BAY6_EEPROM_DOUT_BIT, |
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}, |
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}; |
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/* EEPROM group #1 (Bays 0, 1, 3, 4) */ |
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static const struct nmc93c46_group eeprom_bays_g1 = { |
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4, 0, "PA Bays (Group #1) EEPROM", FALSE, |
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{ &eeprom_bay_def[0], &eeprom_bay_def[1], |
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&eeprom_bay_def[3], &eeprom_bay_def[4], |
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}, |
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}; |
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/* EEPROM group #2 (Bays 2, 5, 6) */ |
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static const struct nmc93c46_group eeprom_bays_g2 = { |
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3, 0, "PA Bays (Group #2) EEPROM", FALSE, |
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|
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{ &eeprom_bay_def[2], &eeprom_bay_def[5], &eeprom_bay_def[6] }, |
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}; |
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/* Midplane FPGA private data */ |
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struct mpfpga_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c7200_t *router; |
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m_uint32_t pa_status_reg; |
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m_uint32_t pa_ctrl_reg; |
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}; |
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/* Update Port Adapter Status */ |
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static void pa_update_status_reg(struct mpfpga_data *d) |
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{ |
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m_uint32_t res = 0; |
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/* PA Power. Bay 0 is always powered */ |
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res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; |
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/* We fake power on bays defined by the final user */ |
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if (c7200_pa_check_eeprom(d->router,1)) |
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res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; |
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if (c7200_pa_check_eeprom(d->router,2)) |
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res |= PCI_BAY2_5V_OK | PCI_BAY2_3V_OK; |
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if (c7200_pa_check_eeprom(d->router,3)) |
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res |= PCI_BAY3_5V_OK | PCI_BAY3_3V_OK; |
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if (c7200_pa_check_eeprom(d->router,4)) |
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res |= PCI_BAY4_5V_OK | PCI_BAY4_3V_OK; |
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if (c7200_pa_check_eeprom(d->router,5)) |
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res |= PCI_BAY5_5V_OK | PCI_BAY5_3V_OK; |
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if (c7200_pa_check_eeprom(d->router,6)) |
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res |= PCI_BAY6_5V_OK | PCI_BAY6_3V_OK; |
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d->pa_status_reg = res; |
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} |
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/* |
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* dev_mpfpga_access() |
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*/ |
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void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct mpfpga_data *d = dev->priv_data; |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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/* Optimization: this is written regularly */ |
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if (offset == 0x7b) |
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return NULL; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"MP_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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} |
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#endif |
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switch(offset) { |
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case 0x10: /* interrupt mask, should be done more efficiently */ |
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case 0x11: |
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case 0x12: |
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case 0x13: |
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if (op_type == MTS_READ) { |
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*data = 0xFFFFFFFF; |
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vm_clear_irq(d->router->vm,C7200_NETIO_IRQ); |
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} |
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break; |
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case 0x18: /* interrupt mask, should be done more efficiently */ |
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case 0x19: |
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case 0x1a: |
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if (op_type == MTS_READ) { |
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*data = 0xFFFFFFFF; |
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vm_clear_irq(d->router->vm,C7200_NETIO_IRQ); |
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} |
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break; |
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/* |
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* - PCI errors (seen with IRQ 6) |
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* - Used when PA Mgmt IRQ is triggered. |
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* |
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* If the PA Mgmt IRQ is triggered for an undefined slot, a crash |
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* occurs with "Error: Unexpected NM Interrupt received from slot: 6" |
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* So, we use the PA status reg as mask to return something safe |
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* (slot order is identical). |
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*/ |
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case 0x40: |
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if (op_type == MTS_READ) |
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*data = 0x66666600 & d->pa_status_reg; |
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dpavlin |
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vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ); |
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dpavlin |
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break; |
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case 0x48: /* ??? (test) */ |
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if (op_type == MTS_READ) |
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*data = 0xFFFFFFFF; |
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break; |
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/* |
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* This corresponds to err_stat in error message when IRQ 6 is |
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* triggered. |
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* |
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* Bit 7 => SRAM error. |
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* Bits 1-6 => OIR on slot 1-6 |
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*/ |
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case 0x70: |
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if (op_type == MTS_READ) { |
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#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", |
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dpavlin |
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offset,cpu_get_pc(cpu),d->router->oir_status); |
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dpavlin |
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#endif |
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*data = d->router->oir_status; |
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dpavlin |
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vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
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dpavlin |
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} else { |
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#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " |
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dpavlin |
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"(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data); |
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dpavlin |
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#endif |
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d->router->oir_status &= ~(*data); |
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vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
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} |
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break; |
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/* |
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* This corresponds to err_enable in error message when IRQ 6 is |
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* triggered. No idea of what it really means. |
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*/ |
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case 0x78: |
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if (op_type == MTS_READ) { |
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#if DEBUG_OIR |
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dpavlin |
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cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n", |
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cpu_get_pc(cpu)); |
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dpavlin |
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#endif |
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*data = 0x00; |
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} else { |
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#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " |
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dpavlin |
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"(data=0x%llx)\n",cpu_get_pc(cpu),*data); |
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dpavlin |
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#endif |
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} |
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break; |
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case 0x38: /* TDM status */ |
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break; |
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case 0x50: /* Port Adapter Status */ |
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if (op_type == MTS_READ) { |
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pa_update_status_reg(d); |
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*data = d->pa_status_reg; |
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} |
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break; |
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case 0x58: /* Port Adapter Control */ |
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if (op_type == MTS_WRITE) |
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d->pa_ctrl_reg = *data; |
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else |
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*data = d->pa_ctrl_reg; |
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break; |
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case 0x60: /* EEPROM for PA in slots 0,1,3,4 */ |
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if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->pa_eeprom_g1,*data); |
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else |
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*data = nmc93c46_read(&d->router->pa_eeprom_g1); |
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break; |
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case 0x68: /* EEPROM for PA in slots 2,5,6 */ |
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if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->pa_eeprom_g2,*data); |
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else |
323 |
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*data = nmc93c46_read(&d->router->pa_eeprom_g2); |
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break; |
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case 0x7b: /* ??? */ |
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break; |
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#if DEBUG_UNKNOWN |
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default: |
331 |
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if (op_type == MTS_READ) { |
332 |
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cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", |
333 |
dpavlin |
7 |
offset,cpu_get_pc(cpu)); |
334 |
dpavlin |
1 |
} else { |
335 |
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cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " |
336 |
dpavlin |
7 |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
337 |
dpavlin |
1 |
} |
338 |
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#endif |
339 |
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} |
340 |
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341 |
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return NULL; |
342 |
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} |
343 |
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344 |
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/* Initialize EEPROM groups */ |
345 |
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static void init_eeprom_groups(c7200_t *router) |
346 |
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{ |
347 |
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/* Group 1: bays 0, 1, 3, 4 */ |
348 |
dpavlin |
3 |
router->pa_eeprom_g1 = eeprom_bays_g1; |
349 |
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router->pa_eeprom_g1.eeprom[0] = &router->pa_bay[0].eeprom; |
350 |
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router->pa_eeprom_g1.eeprom[1] = &router->pa_bay[1].eeprom; |
351 |
|
|
router->pa_eeprom_g1.eeprom[2] = &router->pa_bay[3].eeprom; |
352 |
|
|
router->pa_eeprom_g1.eeprom[3] = &router->pa_bay[4].eeprom; |
353 |
dpavlin |
1 |
|
354 |
|
|
/* Group 2: bays 2, 5, 6 */ |
355 |
dpavlin |
3 |
router->pa_eeprom_g2 = eeprom_bays_g2; |
356 |
|
|
router->pa_eeprom_g2.eeprom[0] = &router->pa_bay[2].eeprom; |
357 |
|
|
router->pa_eeprom_g2.eeprom[1] = &router->pa_bay[5].eeprom; |
358 |
|
|
router->pa_eeprom_g2.eeprom[2] = &router->pa_bay[6].eeprom; |
359 |
dpavlin |
1 |
} |
360 |
|
|
|
361 |
|
|
/* Shutdown the MP FPGA device */ |
362 |
|
|
void dev_c7200_mpfpga_shutdown(vm_instance_t *vm,struct mpfpga_data *d) |
363 |
|
|
{ |
364 |
|
|
if (d != NULL) { |
365 |
|
|
/* Remove the device */ |
366 |
|
|
dev_remove(vm,&d->dev); |
367 |
|
|
|
368 |
|
|
/* Free the structure itself */ |
369 |
|
|
free(d); |
370 |
|
|
} |
371 |
|
|
} |
372 |
|
|
|
373 |
|
|
/* |
374 |
|
|
* dev_c7200_mpfpga_init() |
375 |
|
|
*/ |
376 |
|
|
int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len) |
377 |
|
|
{ |
378 |
|
|
struct mpfpga_data *d; |
379 |
|
|
|
380 |
|
|
/* Allocate private data structure */ |
381 |
|
|
if (!(d = malloc(sizeof(*d)))) { |
382 |
|
|
fprintf(stderr,"MP_FPGA: out of memory\n"); |
383 |
|
|
return(-1); |
384 |
|
|
} |
385 |
|
|
|
386 |
|
|
memset(d,0,sizeof(*d)); |
387 |
|
|
d->router = router; |
388 |
|
|
|
389 |
|
|
/* Initialize EEPROMs */ |
390 |
|
|
init_eeprom_groups(router); |
391 |
|
|
|
392 |
|
|
vm_object_init(&d->vm_obj); |
393 |
|
|
d->vm_obj.name = "mp_fpga"; |
394 |
|
|
d->vm_obj.data = d; |
395 |
|
|
d->vm_obj.shutdown = (vm_shutdown_t)dev_c7200_mpfpga_shutdown; |
396 |
|
|
|
397 |
|
|
/* Set device properties */ |
398 |
|
|
dev_init(&d->dev); |
399 |
|
|
d->dev.name = "mp_fpga"; |
400 |
|
|
d->dev.phys_addr = paddr; |
401 |
|
|
d->dev.phys_len = len; |
402 |
|
|
d->dev.handler = dev_c7200_mpfpga_access; |
403 |
|
|
d->dev.priv_data = d; |
404 |
|
|
|
405 |
|
|
/* Map this device to the VM */ |
406 |
|
|
vm_bind_device(router->vm,&d->dev); |
407 |
|
|
vm_object_add(router->vm,&d->vm_obj); |
408 |
|
|
return(0); |
409 |
|
|
} |