26 |
#include "memory.h" |
#include "memory.h" |
27 |
#include "device.h" |
#include "device.h" |
28 |
#include "dev_vtty.h" |
#include "dev_vtty.h" |
29 |
#include "nmc93c46.h" |
#include "nmc93cX6.h" |
30 |
#include "ds1620.h" |
#include "ds1620.h" |
31 |
#include "dev_c7200.h" |
#include "dev_c7200.h" |
32 |
|
|
133 |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
134 |
|
|
135 |
/* CPU EEPROM definition */ |
/* CPU EEPROM definition */ |
136 |
static const struct nmc93c46_eeprom_def eeprom_cpu_def = { |
static const struct nmc93cX6_eeprom_def eeprom_cpu_def = { |
137 |
SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
138 |
DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
139 |
}; |
}; |
140 |
|
|
141 |
/* Midplane EEPROM definition */ |
/* Midplane EEPROM definition */ |
142 |
static const struct nmc93c46_eeprom_def eeprom_midplane_def = { |
static const struct nmc93cX6_eeprom_def eeprom_midplane_def = { |
143 |
SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
144 |
DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
145 |
}; |
}; |
146 |
|
|
147 |
/* PEM (NPE-B) EEPROM definition */ |
/* PEM (NPE-B) EEPROM definition */ |
148 |
static const struct nmc93c46_eeprom_def eeprom_pem_def = { |
static const struct nmc93cX6_eeprom_def eeprom_pem_def = { |
149 |
SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM, |
SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM, |
150 |
}; |
}; |
151 |
|
|
152 |
/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
153 |
static const struct nmc93c46_group eeprom_cpu_midplane = { |
static const struct nmc93cX6_group eeprom_cpu_midplane = { |
154 |
2, 0, "CPU and Midplane EEPROM", 0, |
EEPROM_TYPE_NMC93C46, 2, 0, |
155 |
|
EEPROM_DORD_NORMAL, |
156 |
|
EEPROM_DOUT_HIGH, |
157 |
|
EEPROM_DEBUG_DISABLED, |
158 |
|
"CPU and Midplane EEPROM", |
159 |
{ &eeprom_cpu_def, &eeprom_midplane_def }, |
{ &eeprom_cpu_def, &eeprom_midplane_def }, |
160 |
}; |
}; |
161 |
|
|
164 |
* PEM stands for "Power Entry Module": |
* PEM stands for "Power Entry Module": |
165 |
* http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml |
* http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml |
166 |
*/ |
*/ |
167 |
static const struct nmc93c46_group eeprom_pem_npeb = { |
static const struct nmc93cX6_group eeprom_pem_npeb = { |
168 |
1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
169 |
|
EEPROM_DORD_NORMAL, |
170 |
|
EEPROM_DOUT_HIGH, |
171 |
|
EEPROM_DEBUG_DISABLED, |
172 |
|
"PEM (NPE-B) EEPROM", |
173 |
|
{ &eeprom_pem_def }, |
174 |
}; |
}; |
175 |
|
|
176 |
/* Reset DS1620 */ |
/* Reset DS1620 */ |
442 |
*data = 0x0102; |
*data = 0x0102; |
443 |
|
|
444 |
/* If we have an I/O slot, we use the I/O slot DUART */ |
/* If we have an I/O slot, we use the I/O slot DUART */ |
445 |
if (c7200_pa_check_eeprom(d->router,0)) |
if (vm_slot_check_eeprom(d->router->vm,0,0)) |
446 |
*data |= 0x01000000; |
*data |= 0x01000000; |
447 |
} |
} |
448 |
break; |
break; |
463 |
/* CPU/Midplane EEPROMs */ |
/* CPU/Midplane EEPROMs */ |
464 |
case 0x21c: |
case 0x21c: |
465 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
466 |
nmc93c46_write(&d->router->sys_eeprom_g1,(u_int)(*data)); |
nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data)); |
467 |
else |
else |
468 |
*data = nmc93c46_read(&d->router->sys_eeprom_g1); |
*data = nmc93cX6_read(&d->router->sys_eeprom_g1); |
469 |
break; |
break; |
470 |
|
|
471 |
/* PEM (NPE-B) EEPROM */ |
/* PEM (NPE-B) EEPROM */ |
472 |
case 0x388: |
case 0x388: |
473 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
474 |
nmc93c46_write(&d->router->sys_eeprom_g2,(u_int)(*data)); |
nmc93cX6_write(&d->router->sys_eeprom_g2,(u_int)(*data)); |
475 |
else |
else |
476 |
*data = nmc93c46_read(&d->router->sys_eeprom_g2); |
*data = nmc93cX6_read(&d->router->sys_eeprom_g2); |
477 |
break; |
break; |
478 |
|
|
479 |
/* Watchdog */ |
/* Watchdog */ |
716 |
return NULL; |
return NULL; |
717 |
} |
} |
718 |
|
|
719 |
/* Initialize EEPROM groups */ |
/* Initialize system EEPROM groups */ |
720 |
void c7200_init_eeprom_groups(c7200_t *router) |
void c7200_init_sys_eeprom_groups(c7200_t *router) |
721 |
{ |
{ |
722 |
router->sys_eeprom_g1 = eeprom_cpu_midplane; |
router->sys_eeprom_g1 = eeprom_cpu_midplane; |
723 |
router->sys_eeprom_g2 = eeprom_pem_npeb; |
router->sys_eeprom_g2 = eeprom_pem_npeb; |
787 |
d->dev.priv_data = d; |
d->dev.priv_data = d; |
788 |
|
|
789 |
/* If we have an I/O slot, we use the I/O slot DUART */ |
/* If we have an I/O slot, we use the I/O slot DUART */ |
790 |
if (c7200_pa_check_eeprom(d->router,0)) { |
if (vm_slot_check_eeprom(vm,0,0)) { |
791 |
vm_log(vm,"CONSOLE","console managed by I/O board\n"); |
vm_log(vm,"CONSOLE","console managed by I/O board\n"); |
792 |
|
|
793 |
/* Set console and AUX port notifying functions */ |
/* Set console and AUX port notifying functions */ |