1 |
/* |
2 |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2007 Christophe Fillot (cf@utc.fr) |
4 |
* |
5 |
* Cisco C6k-MSFC1 I/O FPGA: |
6 |
* - Simulates a NMC93C56 Serial EEPROM. |
7 |
* - Simulates a DALLAS DS1620 for Temperature Sensors. |
8 |
* - Simulates console and AUX ports (SCN2681). |
9 |
* |
10 |
* This is very similar to c7200 platform. |
11 |
*/ |
12 |
|
13 |
#include <stdio.h> |
14 |
#include <stdlib.h> |
15 |
#include <string.h> |
16 |
#include <unistd.h> |
17 |
#include <sys/types.h> |
18 |
|
19 |
#include <termios.h> |
20 |
#include <fcntl.h> |
21 |
#include <pthread.h> |
22 |
|
23 |
#include "ptask.h" |
24 |
#include "cpu.h" |
25 |
#include "vm.h" |
26 |
#include "dynamips.h" |
27 |
#include "memory.h" |
28 |
#include "device.h" |
29 |
#include "dev_vtty.h" |
30 |
#include "nmc93cX6.h" |
31 |
#include "ds1620.h" |
32 |
#include "dev_c6msfc1.h" |
33 |
|
34 |
/* Debugging flags */ |
35 |
#define DEBUG_UNKNOWN 1 |
36 |
#define DEBUG_ACCESS 0 |
37 |
#define DEBUG_LED 0 |
38 |
#define DEBUG_IO_CTL 0 |
39 |
#define DEBUG_ENVM 0 |
40 |
|
41 |
/* DUART RX/TX status (SRA/SRB) */ |
42 |
#define DUART_RX_READY 0x01 |
43 |
#define DUART_TX_READY 0x04 |
44 |
|
45 |
/* DUART RX/TX Interrupt Status/Mask */ |
46 |
#define DUART_TXRDYA 0x01 |
47 |
#define DUART_RXRDYA 0x02 |
48 |
#define DUART_TXRDYB 0x10 |
49 |
#define DUART_RXRDYB 0x20 |
50 |
|
51 |
/* Definitions for CPU and Midplane Serial EEPROMs */ |
52 |
#define DO2_DATA_OUT_MIDPLANE 7 |
53 |
#define DO1_DATA_OUT_CPU 6 |
54 |
#define CS2_CHIP_SEL_MIDPLANE 5 |
55 |
#define SK2_CLOCK_MIDPLANE 4 |
56 |
#define DI2_DATA_IN_MIDPLANE 3 |
57 |
#define CS1_CHIP_SEL_CPU 2 |
58 |
#define SK1_CLOCK_CPU 1 |
59 |
#define DI1_DATA_IN_CPU 0 |
60 |
|
61 |
/* Pack the NVRAM */ |
62 |
#define NVRAM_PACKED 0x04 |
63 |
|
64 |
/* 2 temperature sensors in a MSFC1: chassis inlet and oulet */ |
65 |
#define C6MSFC1_TEMP_SENSORS 2 |
66 |
#define C6MSFC1_DEFAULT_TEMP 22 /* default temperature: 22°C */ |
67 |
|
68 |
/* IO FPGA structure */ |
69 |
struct iofpga_data { |
70 |
vm_obj_t vm_obj; |
71 |
struct vdevice dev; |
72 |
c6msfc1_t *router; |
73 |
|
74 |
/* Lock test */ |
75 |
pthread_mutex_t lock; |
76 |
|
77 |
/* Periodic task to trigger dummy DUART IRQ */ |
78 |
ptask_id_t duart_irq_tid; |
79 |
|
80 |
/* DUART & Console Management */ |
81 |
u_int duart_isr,duart_imr,duart_irq_seq; |
82 |
|
83 |
/* IO control register */ |
84 |
u_int io_ctrl_reg; |
85 |
|
86 |
/* Temperature Control */ |
87 |
u_int temp_cfg_reg[C6MSFC1_TEMP_SENSORS]; |
88 |
u_int temp_deg_reg[C6MSFC1_TEMP_SENSORS]; |
89 |
u_int temp_clk_low; |
90 |
|
91 |
u_int temp_cmd; |
92 |
u_int temp_cmd_pos; |
93 |
|
94 |
u_int temp_data; |
95 |
u_int temp_data_pos; |
96 |
|
97 |
/* Voltages */ |
98 |
u_int mux; |
99 |
}; |
100 |
|
101 |
#define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock) |
102 |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
103 |
|
104 |
/* CPU EEPROM definition */ |
105 |
static const struct nmc93cX6_eeprom_def eeprom_cpu_def = { |
106 |
SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
107 |
DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
108 |
}; |
109 |
|
110 |
/* Midplane EEPROM definition */ |
111 |
static const struct nmc93cX6_eeprom_def eeprom_midplane_def = { |
112 |
SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
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DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
114 |
}; |
115 |
|
116 |
|
117 |
/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
118 |
static const struct nmc93cX6_group eeprom_cpu_midplane = { |
119 |
EEPROM_TYPE_NMC93C56, 2, 0, |
120 |
EEPROM_DORD_NORMAL, |
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EEPROM_DOUT_HIGH, |
122 |
EEPROM_DEBUG_DISABLED, |
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"CPU and Midplane EEPROM", |
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{ &eeprom_cpu_def, &eeprom_midplane_def }, |
125 |
}; |
126 |
|
127 |
/* Reset DS1620 */ |
128 |
static void temp_reset(struct iofpga_data *d) |
129 |
{ |
130 |
d->temp_cmd_pos = 0; |
131 |
d->temp_cmd = 0; |
132 |
|
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d->temp_data_pos = 0; |
134 |
d->temp_data = 0; |
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} |
136 |
|
137 |
/* Write the temperature control data */ |
138 |
static void temp_write_ctrl(struct iofpga_data *d,u_char val) |
139 |
{ |
140 |
switch(val) { |
141 |
case DS1620_RESET_ON: |
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temp_reset(d); |
143 |
break; |
144 |
|
145 |
case DS1620_CLK_LOW: |
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d->temp_clk_low = 1; |
147 |
break; |
148 |
|
149 |
case DS1620_CLK_HIGH: |
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d->temp_clk_low = 0; |
151 |
break; |
152 |
} |
153 |
} |
154 |
|
155 |
/* Read a temperature control data */ |
156 |
static u_int temp_read_data(struct iofpga_data *d) |
157 |
{ |
158 |
u_int i,data = 0; |
159 |
|
160 |
switch(d->temp_cmd) { |
161 |
case DS1620_READ_CONFIG: |
162 |
for(i=0;i<C6MSFC1_TEMP_SENSORS;i++) |
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data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i; |
164 |
|
165 |
d->temp_data_pos++; |
166 |
|
167 |
if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE) |
168 |
temp_reset(d); |
169 |
|
170 |
break; |
171 |
|
172 |
case DS1620_READ_TEMP: |
173 |
for(i=0;i<C6MSFC1_TEMP_SENSORS;i++) |
174 |
data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i; |
175 |
|
176 |
d->temp_data_pos++; |
177 |
|
178 |
if (d->temp_data_pos == DS1620_DATA_READ_SIZE) |
179 |
temp_reset(d); |
180 |
|
181 |
break; |
182 |
|
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default: |
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vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n", |
185 |
d->temp_cmd); |
186 |
} |
187 |
|
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return(data); |
189 |
} |
190 |
|
191 |
/* Write the temperature data write register */ |
192 |
static void temp_write_data(struct iofpga_data *d,u_char val) |
193 |
{ |
194 |
if (val == DS1620_ENABLE_READ) { |
195 |
d->temp_data_pos = 0; |
196 |
return; |
197 |
} |
198 |
|
199 |
if (!d->temp_clk_low) |
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return; |
201 |
|
202 |
/* Write a command */ |
203 |
if (d->temp_cmd_pos < DS1620_WRITE_SIZE) |
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{ |
205 |
if (val == DS1620_DATA_HIGH) |
206 |
d->temp_cmd |= 1 << d->temp_cmd_pos; |
207 |
|
208 |
d->temp_cmd_pos++; |
209 |
|
210 |
if (d->temp_cmd_pos == DS1620_WRITE_SIZE) { |
211 |
switch(d->temp_cmd) { |
212 |
case DS1620_START_CONVT: |
213 |
//printf("temp_sensors: IOS enabled continuous monitoring.\n"); |
214 |
temp_reset(d); |
215 |
break; |
216 |
case DS1620_READ_CONFIG: |
217 |
case DS1620_READ_TEMP: |
218 |
break; |
219 |
default: |
220 |
vm_log(d->router->vm,"IO_FPGA", |
221 |
"temp_sensors: IOS sent command 0x%x.\n", |
222 |
d->temp_cmd); |
223 |
} |
224 |
} |
225 |
} |
226 |
else |
227 |
{ |
228 |
if (val == DS1620_DATA_HIGH) |
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d->temp_data |= 1 << d->temp_data_pos; |
230 |
|
231 |
d->temp_data_pos++; |
232 |
} |
233 |
} |
234 |
|
235 |
/* Console port input */ |
236 |
static void tty_con_input(vtty_t *vtty) |
237 |
{ |
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struct iofpga_data *d = vtty->priv_data; |
239 |
|
240 |
IOFPGA_LOCK(d); |
241 |
if (d->duart_imr & DUART_RXRDYA) { |
242 |
d->duart_isr |= DUART_RXRDYA; |
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vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ); |
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} |
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IOFPGA_UNLOCK(d); |
246 |
} |
247 |
|
248 |
/* AUX port input */ |
249 |
static void tty_aux_input(vtty_t *vtty) |
250 |
{ |
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struct iofpga_data *d = vtty->priv_data; |
252 |
|
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IOFPGA_LOCK(d); |
254 |
if (d->duart_imr & DUART_RXRDYB) { |
255 |
d->duart_isr |= DUART_RXRDYB; |
256 |
vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ); |
257 |
} |
258 |
IOFPGA_UNLOCK(d); |
259 |
} |
260 |
|
261 |
/* IRQ trickery for Console and AUX ports */ |
262 |
static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg) |
263 |
{ |
264 |
u_int mask; |
265 |
|
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IOFPGA_LOCK(d); |
267 |
d->duart_irq_seq++; |
268 |
|
269 |
if (d->duart_irq_seq == 2) { |
270 |
mask = DUART_TXRDYA|DUART_TXRDYB; |
271 |
if (d->duart_imr & mask) { |
272 |
d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB; |
273 |
vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ); |
274 |
} |
275 |
|
276 |
d->duart_irq_seq = 0; |
277 |
} |
278 |
|
279 |
IOFPGA_UNLOCK(d); |
280 |
return(0); |
281 |
} |
282 |
|
283 |
/* |
284 |
* dev_c6msfc1_iofpga_access() |
285 |
*/ |
286 |
void *dev_c6msfc1_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
287 |
m_uint32_t offset,u_int op_size,u_int op_type, |
288 |
m_uint64_t *data) |
289 |
{ |
290 |
struct iofpga_data *d = dev->priv_data; |
291 |
vm_instance_t *vm = d->router->vm; |
292 |
u_char odata; |
293 |
|
294 |
if (op_type == MTS_READ) |
295 |
*data = 0x0; |
296 |
|
297 |
#if DEBUG_ACCESS |
298 |
if (op_type == MTS_READ) { |
299 |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n", |
300 |
offset,cpu_get_pc(cpu)); |
301 |
} else { |
302 |
cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n", |
303 |
offset,cpu_get_pc(cpu),*data); |
304 |
} |
305 |
#endif |
306 |
|
307 |
IOFPGA_LOCK(d); |
308 |
|
309 |
switch(offset) { |
310 |
case 0x294: |
311 |
/* |
312 |
* Unknown, seen in 12.4(6)T, and seems to be read at each |
313 |
* network interrupt. |
314 |
*/ |
315 |
if (op_type == MTS_READ) |
316 |
*data = 0x0; |
317 |
break; |
318 |
|
319 |
/* I/O control register */ |
320 |
case 0x204: |
321 |
if (op_type == MTS_WRITE) { |
322 |
#if DEBUG_IO_CTL |
323 |
vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data); |
324 |
#endif |
325 |
d->io_ctrl_reg = *data; |
326 |
} else { |
327 |
*data = d->io_ctrl_reg; |
328 |
*data |= NVRAM_PACKED; /* Packed NVRAM */ |
329 |
} |
330 |
break; |
331 |
|
332 |
/* CPU/Midplane EEPROMs */ |
333 |
case 0x21c: |
334 |
if (op_type == MTS_WRITE) |
335 |
nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data)); |
336 |
else |
337 |
*data = nmc93cX6_read(&d->router->sys_eeprom_g1); |
338 |
break; |
339 |
|
340 |
/* Watchdog */ |
341 |
case 0x234: |
342 |
break; |
343 |
|
344 |
/* |
345 |
* FPGA release/presence ? Flash SIMM size: |
346 |
* 0x0001: 2048K Flash (2 banks) |
347 |
* 0x0504: 8192K Flash (2 banks) |
348 |
* 0x0704: 16384K Flash (2 banks) |
349 |
* 0x0904: 32768K Flash (2 banks) |
350 |
* 0x0B04: 65536K Flash (2 banks) |
351 |
* 0x2001: 1024K Flash (1 bank) |
352 |
* 0x2504: 4096K Flash (1 bank) |
353 |
* 0x2704: 8192K Flash (1 bank) |
354 |
* 0x2904: 16384K Flash (1 bank) |
355 |
* 0x2B04: 32768K Flash (1 bank) |
356 |
* |
357 |
* Number of Flash SIMM banks + size. |
358 |
* Touching some lower bits causes problems with environmental monitor. |
359 |
* |
360 |
* It is displayed by command "sh bootflash: chips" |
361 |
*/ |
362 |
case 0x23c: |
363 |
if (op_type == MTS_READ) |
364 |
*data = 0x2704; |
365 |
break; |
366 |
|
367 |
/* LEDs */ |
368 |
case 0x244: |
369 |
#if DEBUG_LED |
370 |
vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n", |
371 |
*data,(~*data) & 0x0F); |
372 |
#endif |
373 |
break; |
374 |
|
375 |
/* ==== DUART SCN2681 (console/aux) ==== */ |
376 |
case 0x404: /* Mode Register A (MRA) */ |
377 |
break; |
378 |
|
379 |
case 0x40c: /* Status Register A (SRA) */ |
380 |
if (op_type == MTS_READ) { |
381 |
odata = 0; |
382 |
|
383 |
if (vtty_is_char_avail(vm->vtty_con)) |
384 |
odata |= DUART_RX_READY; |
385 |
|
386 |
odata |= DUART_TX_READY; |
387 |
|
388 |
vm_clear_irq(vm,C6MSFC1_DUART_IRQ); |
389 |
*data = odata; |
390 |
} |
391 |
break; |
392 |
|
393 |
case 0x414: /* Command Register A (CRA) */ |
394 |
/* Disable TX = High */ |
395 |
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
396 |
vm->vtty_con->managed_flush = TRUE; |
397 |
vtty_flush(vm->vtty_con); |
398 |
} |
399 |
break; |
400 |
|
401 |
case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */ |
402 |
if (op_type == MTS_WRITE) { |
403 |
vtty_put_char(vm->vtty_con,(char)*data); |
404 |
d->duart_isr &= ~DUART_TXRDYA; |
405 |
} else { |
406 |
*data = vtty_get_char(vm->vtty_con); |
407 |
d->duart_isr &= ~DUART_RXRDYA; |
408 |
} |
409 |
break; |
410 |
|
411 |
case 0x424: /* WRITE: Aux Control Register (ACR) */ |
412 |
break; |
413 |
|
414 |
case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */ |
415 |
if (op_type == MTS_WRITE) { |
416 |
d->duart_imr = *data; |
417 |
} else |
418 |
*data = d->duart_isr; |
419 |
break; |
420 |
|
421 |
case 0x434: /* Counter/Timer Upper Value (CTU) */ |
422 |
case 0x43c: /* Counter/Timer Lower Value (CTL) */ |
423 |
case 0x444: /* Mode Register B (MRB) */ |
424 |
break; |
425 |
|
426 |
case 0x44c: /* Status Register B (SRB) */ |
427 |
if (op_type == MTS_READ) { |
428 |
odata = 0; |
429 |
|
430 |
if (vtty_is_char_avail(vm->vtty_aux)) |
431 |
odata |= DUART_RX_READY; |
432 |
|
433 |
odata |= DUART_TX_READY; |
434 |
|
435 |
//vm_clear_irq(vm,C6MSFC1_DUART_IRQ); |
436 |
*data = odata; |
437 |
} |
438 |
break; |
439 |
|
440 |
case 0x454: /* Command Register B (CRB) */ |
441 |
/* Disable TX = High */ |
442 |
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
443 |
vm->vtty_aux->managed_flush = TRUE; |
444 |
vtty_flush(vm->vtty_aux); |
445 |
} |
446 |
break; |
447 |
|
448 |
case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */ |
449 |
if (op_type == MTS_WRITE) { |
450 |
vtty_put_char(vm->vtty_aux,(char)*data); |
451 |
d->duart_isr &= ~DUART_TXRDYA; |
452 |
} else { |
453 |
*data = vtty_get_char(vm->vtty_aux); |
454 |
d->duart_isr &= ~DUART_RXRDYB; |
455 |
} |
456 |
break; |
457 |
|
458 |
case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */ |
459 |
case 0x474: /* READ: Start Counter Command; */ |
460 |
/* WRITE: Set Output Port Bits Command */ |
461 |
case 0x47c: /* WRITE: Reset Output Port Bits Command */ |
462 |
break; |
463 |
|
464 |
/* ==== DS 1620 (temp sensors) ==== */ |
465 |
case 0x20c: /* Temperature Control */ |
466 |
if (op_type == MTS_WRITE) |
467 |
temp_write_ctrl(d,*data); |
468 |
break; |
469 |
|
470 |
case 0x214: /* Temperature data write */ |
471 |
if (op_type == MTS_WRITE) { |
472 |
temp_write_data(d,*data); |
473 |
d->mux = *data; |
474 |
} |
475 |
break; |
476 |
|
477 |
case 0x22c: /* Temperature data read */ |
478 |
if (op_type == MTS_READ) |
479 |
*data = temp_read_data(d); |
480 |
break; |
481 |
|
482 |
#if DEBUG_UNKNOWN |
483 |
default: |
484 |
if (op_type == MTS_READ) { |
485 |
cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n", |
486 |
offset,cpu_get_pc(cpu),op_size); |
487 |
} else { |
488 |
cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, " |
489 |
"pc=0x%llx (size=%u)\n", |
490 |
offset,*data,cpu_get_pc(cpu),op_size); |
491 |
} |
492 |
#endif |
493 |
} |
494 |
|
495 |
IOFPGA_UNLOCK(d); |
496 |
return NULL; |
497 |
} |
498 |
|
499 |
/* Initialize EEPROM groups */ |
500 |
void c6msfc1_init_eeprom_groups(c6msfc1_t *router) |
501 |
{ |
502 |
router->sys_eeprom_g1 = eeprom_cpu_midplane; |
503 |
router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom; |
504 |
router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom; |
505 |
} |
506 |
|
507 |
/* Shutdown the IO FPGA device */ |
508 |
void dev_c6msfc1_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
509 |
{ |
510 |
if (d != NULL) { |
511 |
IOFPGA_LOCK(d); |
512 |
vm->vtty_con->read_notifier = NULL; |
513 |
vm->vtty_aux->read_notifier = NULL; |
514 |
IOFPGA_UNLOCK(d); |
515 |
|
516 |
/* Remove the dummy IRQ periodic task */ |
517 |
ptask_remove(d->duart_irq_tid); |
518 |
|
519 |
/* Remove the device */ |
520 |
dev_remove(vm,&d->dev); |
521 |
|
522 |
/* Free the structure itself */ |
523 |
free(d); |
524 |
} |
525 |
} |
526 |
|
527 |
/* |
528 |
* dev_c6msfc1_iofpga_init() |
529 |
*/ |
530 |
int dev_c6msfc1_iofpga_init(c6msfc1_t *router,m_uint64_t paddr,m_uint32_t len) |
531 |
{ |
532 |
vm_instance_t *vm = router->vm; |
533 |
struct iofpga_data *d; |
534 |
u_int i; |
535 |
|
536 |
/* Allocate private data structure */ |
537 |
if (!(d = malloc(sizeof(*d)))) { |
538 |
fprintf(stderr,"IO_FPGA: out of memory\n"); |
539 |
return(-1); |
540 |
} |
541 |
|
542 |
memset(d,0,sizeof(*d)); |
543 |
|
544 |
pthread_mutex_init(&d->lock,NULL); |
545 |
d->router = router; |
546 |
|
547 |
for(i=0;i<C6MSFC1_TEMP_SENSORS;i++) { |
548 |
d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU; |
549 |
d->temp_deg_reg[i] = C6MSFC1_DEFAULT_TEMP * 2; |
550 |
} |
551 |
|
552 |
vm_object_init(&d->vm_obj); |
553 |
d->vm_obj.name = "io_fpga"; |
554 |
d->vm_obj.data = d; |
555 |
d->vm_obj.shutdown = (vm_shutdown_t)dev_c6msfc1_iofpga_shutdown; |
556 |
|
557 |
/* Set device properties */ |
558 |
dev_init(&d->dev); |
559 |
d->dev.name = "io_fpga"; |
560 |
d->dev.phys_addr = paddr; |
561 |
d->dev.phys_len = len; |
562 |
d->dev.handler = dev_c6msfc1_iofpga_access; |
563 |
d->dev.priv_data = d; |
564 |
|
565 |
/* Set console and AUX port notifying functions */ |
566 |
vm->vtty_con->priv_data = d; |
567 |
vm->vtty_aux->priv_data = d; |
568 |
vm->vtty_con->read_notifier = tty_con_input; |
569 |
vm->vtty_aux->read_notifier = tty_aux_input; |
570 |
|
571 |
/* Trigger periodically a dummy IRQ to flush buffers */ |
572 |
d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq, |
573 |
d,NULL); |
574 |
|
575 |
/* Map this device to the VM */ |
576 |
vm_bind_device(vm,&d->dev); |
577 |
vm_object_add(vm,&d->vm_obj); |
578 |
return(0); |
579 |
} |