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#include <pthread.h> |
#include <pthread.h> |
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#include "ptask.h" |
#include "ptask.h" |
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#include "mips64.h" |
#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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#include "dev_vtty.h" |
#include "dev_vtty.h" |
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#include "nmc93c46.h" |
#include "nmc93cX6.h" |
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#include "dev_c3725.h" |
#include "dev_c3725.h" |
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/* Debugging flags */ |
/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
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#define DEBUG_NET_IRQ 0 |
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/* Definitions for Mainboard EEPROM */ |
/* Definitions for Mainboard EEPROM */ |
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#define EEPROM_MB_DOUT 3 |
#define EEPROM_MB_DOUT 3 |
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#define EEPROM_NM_CLK 2 |
#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
#define EEPROM_NM_CS 4 |
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#define C3725_NET_IRQ_CLEARING_DELAY 16 |
/* Network IRQ distribution */ |
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struct net_irq_distrib { |
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u_int reg; |
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u_int offset; |
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}; |
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static struct net_irq_distrib net_irq_dist[C3725_MAX_NM_BAYS] = { |
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{ 0, 0 }, /* Slot 0: reg 0x26, 0x000000XX */ |
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{ 1, 0 }, /* Slot 1: reg 0x28, 0x0000000X */ |
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{ 1, 4 }, /* Slot 2: reg 0x28, 0x000000X0 */ |
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}; |
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/* IO FPGA structure */ |
/* IO FPGA structure */ |
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struct iofpga_data { |
struct c3725_iofpga_data { |
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vm_obj_t vm_obj; |
vm_obj_t vm_obj; |
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struct vdevice dev; |
struct vdevice dev; |
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c3725_t *router; |
c3725_t *router; |
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/* |
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* Used to introduce a "delay" before clearing the network interrupt |
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* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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/* Interrupt mask*/ |
/* Network IRQ status */ |
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m_uint16_t net_irq_status[2]; |
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/* Interrupt mask */ |
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m_uint16_t intr_mask; |
m_uint16_t intr_mask; |
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}; |
}; |
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/* Mainboard EEPROM definition */ |
/* Mainboard EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
}; |
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/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
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static const struct nmc93c46_group eeprom_mb_group = { |
static const struct nmc93cX6_group eeprom_mb_group = { |
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1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
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}; |
}; |
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/* NM EEPROM definition */ |
/* NM EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
}; |
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/* NM EEPROM */ |
/* NM EEPROM */ |
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static const struct nmc93c46_group eeprom_nm_group = { |
static const struct nmc93cX6_group eeprom_nm_group = { |
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1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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}; |
}; |
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/* Update network interrupt status */ |
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static inline void dev_c3725_iofpga_net_update_irq(struct c3725_iofpga_data *d) |
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{ |
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if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) { |
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vm_set_irq(d->router->vm,C3725_NETIO_IRQ); |
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} else { |
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vm_clear_irq(d->router->vm,C3725_NETIO_IRQ); |
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} |
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} |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c3725_iofpga_net_set_irq(struct c3725_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
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dev_c3725_iofpga_net_update_irq(d); |
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} |
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/* Clear a Network IRQ for the specified slot/port */ |
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void dev_c3725_iofpga_net_clear_irq(struct c3725_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port)); |
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dev_c3725_iofpga_net_update_irq(d); |
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} |
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/* |
/* |
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* dev_c3725_iofpga_access() |
* dev_c3725_iofpga_access() |
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*/ |
*/ |
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static void * |
static void * |
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dev_c3725_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c3725_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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struct iofpga_data *d = dev->priv_data; |
struct c3725_iofpga_data *d = dev->priv_data; |
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
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*data = 0x0; |
*data = 0x0; |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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#endif |
#endif |
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/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
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case 0x0e: |
case 0x0e: |
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if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
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else |
else |
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*data = nmc93c46_read(&d->router->mb_eeprom_group); |
*data = nmc93cX6_read(&d->router->mb_eeprom_group); |
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break; |
break; |
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case 0x12: |
case 0x12: |
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/* NM Slot 1 EEPROM */ |
/* NM Slot 1 EEPROM */ |
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case 0x44: |
case 0x44: |
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if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->nm_eeprom_group[0],(u_int)(*data)); |
nmc93cX6_write(&d->router->nm_eeprom_group[0],(u_int)(*data)); |
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else |
else |
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*data = nmc93c46_read(&d->router->nm_eeprom_group[0]); |
*data = nmc93cX6_read(&d->router->nm_eeprom_group[0]); |
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break; |
break; |
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/* NM Slot 2 EEPROM */ |
/* NM Slot 2 EEPROM */ |
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case 0x46: |
case 0x46: |
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if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->nm_eeprom_group[1],(u_int)(*data)); |
nmc93cX6_write(&d->router->nm_eeprom_group[1],(u_int)(*data)); |
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else |
else |
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*data = nmc93c46_read(&d->router->nm_eeprom_group[1]); |
*data = nmc93cX6_read(&d->router->nm_eeprom_group[1]); |
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break; |
break; |
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/* AIM EEPROM #0 */ |
/* AIM EEPROM #0 */ |
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*/ |
*/ |
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case 0x26: |
case 0x26: |
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
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*data = 0xFFFE; |
*data = d->net_irq_status[0]; |
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break; |
break; |
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/* |
/* |
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* Other bits unknown. |
* Other bits unknown. |
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*/ |
*/ |
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case 0x28: |
case 0x28: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) |
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*data = 0xFFEE; |
*data = d->net_irq_status[1]; |
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if (++d->net_irq_clearing_count == C3725_NET_IRQ_CLEARING_DELAY) { |
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vm_clear_irq(d->router->vm,C3725_NETIO_IRQ); |
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d->net_irq_clearing_count = 0; |
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} |
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} |
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break; |
break; |
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case 0x2c: |
case 0x2c: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
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"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
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offset,*data,cpu_get_pc(cpu),op_size); |
342 |
} |
} |
343 |
#endif |
#endif |
344 |
} |
} |
365 |
} |
} |
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/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |
368 |
void dev_c3725_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
static void |
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dev_c3725_iofpga_shutdown(vm_instance_t *vm,struct c3725_iofpga_data *d) |
370 |
{ |
{ |
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if (d != NULL) { |
if (d != NULL) { |
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/* Remove the device */ |
/* Remove the device */ |
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int dev_c3725_iofpga_init(c3725_t *router,m_uint64_t paddr,m_uint32_t len) |
int dev_c3725_iofpga_init(c3725_t *router,m_uint64_t paddr,m_uint32_t len) |
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{ |
{ |
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vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
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struct iofpga_data *d; |
struct c3725_iofpga_data *d; |
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/* Allocate private data structure */ |
/* Allocate private data structure */ |
389 |
if (!(d = malloc(sizeof(*d)))) { |
if (!(d = malloc(sizeof(*d)))) { |
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memset(d,0,sizeof(*d)); |
memset(d,0,sizeof(*d)); |
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d->router = router; |
d->router = router; |
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d->net_irq_status[0] = 0xFFFF; |
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d->net_irq_status[1] = 0xFFFF; |
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399 |
vm_object_init(&d->vm_obj); |
vm_object_init(&d->vm_obj); |
400 |
d->vm_obj.name = "io_fpga"; |
d->vm_obj.name = "io_fpga"; |