1 |
/* |
/* |
2 |
* Cisco 3600 simulation platform. |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
4 |
* |
* |
5 |
* TODO: Online Insertion/Removal (OIR). |
* TODO: Online Insertion/Removal (OIR). |
15 |
#include <pthread.h> |
#include <pthread.h> |
16 |
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|
17 |
#include "ptask.h" |
#include "ptask.h" |
18 |
#include "mips64.h" |
#include "cpu.h" |
19 |
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#include "vm.h" |
20 |
#include "dynamips.h" |
#include "dynamips.h" |
21 |
#include "memory.h" |
#include "memory.h" |
22 |
#include "device.h" |
#include "device.h" |
23 |
#include "dev_vtty.h" |
#include "dev_vtty.h" |
24 |
#include "nmc93c46.h" |
#include "nmc93cX6.h" |
25 |
#include "dev_c3600.h" |
#include "dev_c3600.h" |
26 |
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|
27 |
/* Debugging flags */ |
/* Debugging flags */ |
28 |
#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
29 |
#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
30 |
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#define DEBUG_NET_IRQ 0 |
31 |
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32 |
/* Definitions for Mainboard EEPROM */ |
/* Definitions for Mainboard EEPROM */ |
33 |
#define EEPROM_MB_DOUT 3 |
#define EEPROM_MB_DOUT 3 |
41 |
#define EEPROM_NM_CLK 2 |
#define EEPROM_NM_CLK 2 |
42 |
#define EEPROM_NM_CS 4 |
#define EEPROM_NM_CS 4 |
43 |
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44 |
#define C3600_NET_IRQ_CLEARING_DELAY 16 |
/* Network IRQ distribution */ |
45 |
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struct net_irq_distrib { |
46 |
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u_int c3620_c3640_offset; |
47 |
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u_int c3660_reg; |
48 |
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u_int c3660_offset; |
49 |
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}; |
50 |
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51 |
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/* |
52 |
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* Network IRQ distribution for c3620/c3640 |
53 |
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* |
54 |
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* Slot 0 | 3620/3640: reg 0x20001 | 3660: reg 0x20010, offset 0 |
55 |
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* Slot 1 | 3620/3640: reg 0x20000 | 3660: reg 0x10010, offset 24 |
56 |
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* Slot 2 | 3640 : reg 0x20003 | 3660: reg 0x10010, offset 16 |
57 |
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* Slot 3 | 3640 : reg 0x20002 | 3660: reg 0x10010, offset 28 |
58 |
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* Slot 4 | 3620/3640: N/A | 3660: reg 0x10010, offset 20 |
59 |
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* Slot 5 | 3620/3640: N/A | 3660: reg 0x10010, offset 8 |
60 |
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* Slot 6 | 3620/3640: N/A | 3660: reg 0x10010, offset 0 |
61 |
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*/ |
62 |
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static struct net_irq_distrib net_irq_dist[C3600_MAX_NM_BAYS] = { |
63 |
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{ 16, 1, 0 }, |
64 |
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{ 24, 0, 24 }, |
65 |
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{ 0, 0, 16 }, |
66 |
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{ 8, 0, 28 }, |
67 |
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{ 32, 0, 20 }, |
68 |
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{ 32, 0, 8 }, |
69 |
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{ 32, 0, 0 }, |
70 |
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}; |
71 |
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72 |
/* IO FPGA structure */ |
/* IO FPGA structure */ |
73 |
struct iofpga_data { |
struct c3600_iofpga_data { |
74 |
vm_obj_t vm_obj; |
vm_obj_t vm_obj; |
75 |
struct vdevice dev; |
struct vdevice dev; |
76 |
c3600_t *router; |
c3600_t *router; |
77 |
|
|
78 |
/* |
/* Network IRQ status */ |
79 |
* Used to introduce a "delay" before clearing the network interrupt |
m_uint32_t net_irq_status[2]; |
80 |
* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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81 |
/* Slot select for EEPROM access */ |
/* Slot select for EEPROM access */ |
82 |
u_int eeprom_slot; |
u_int eeprom_slot; |
83 |
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|
88 |
}; |
}; |
89 |
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|
90 |
/* Mainboard EEPROM definition */ |
/* Mainboard EEPROM definition */ |
91 |
static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
92 |
EEPROM_MB_CLK, EEPROM_MB_CS, |
EEPROM_MB_CLK, EEPROM_MB_CS, |
93 |
EEPROM_MB_DIN, EEPROM_MB_DOUT, |
EEPROM_MB_DIN, EEPROM_MB_DOUT, |
94 |
}; |
}; |
95 |
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|
96 |
/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
97 |
static const struct nmc93c46_group eeprom_mb_group = { |
static const struct nmc93cX6_group eeprom_mb_group = { |
98 |
1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
99 |
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EEPROM_DORD_NORMAL, |
100 |
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EEPROM_DOUT_HIGH, |
101 |
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EEPROM_DEBUG_DISABLED, |
102 |
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"Mainboard EEPROM", |
103 |
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{ &eeprom_mb_def }, |
104 |
}; |
}; |
105 |
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|
106 |
/* NM EEPROM definition */ |
/* NM EEPROM definition */ |
107 |
static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
108 |
EEPROM_NM_CLK, EEPROM_NM_CS, |
EEPROM_NM_CLK, EEPROM_NM_CS, |
109 |
EEPROM_NM_DIN, EEPROM_NM_DOUT, |
EEPROM_NM_DIN, EEPROM_NM_DOUT, |
110 |
}; |
}; |
111 |
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|
112 |
/* NM EEPROM */ |
/* NM EEPROM */ |
113 |
static const struct nmc93c46_group eeprom_nm_group = { |
static const struct nmc93cX6_group eeprom_nm_group = { |
114 |
1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
115 |
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EEPROM_DORD_NORMAL, |
116 |
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EEPROM_DOUT_HIGH, |
117 |
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EEPROM_DEBUG_DISABLED, |
118 |
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"NM EEPROM", |
119 |
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{ &eeprom_nm_def }, |
120 |
}; |
}; |
121 |
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|
122 |
/* C3660 NM presence masks */ |
/* C3660 NM presence masks */ |
130 |
}; |
}; |
131 |
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|
132 |
/* Select the current NM EEPROM */ |
/* Select the current NM EEPROM */ |
133 |
static void nm_eeprom_select(struct iofpga_data *d,u_int slot) |
static void nm_eeprom_select(struct c3600_iofpga_data *d,u_int slot) |
134 |
{ |
{ |
135 |
d->router->nm_eeprom_group.eeprom[0] = &d->router->nm_bay[slot].eeprom; |
struct cisco_eeprom *eeprom = NULL; |
136 |
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struct cisco_card *card; |
137 |
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138 |
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card = vm_slot_get_card_ptr(d->router->vm,slot); |
139 |
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140 |
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if (card != NULL) |
141 |
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eeprom = &card->eeprom; |
142 |
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143 |
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d->router->nm_eeprom_group.eeprom[0] = eeprom; |
144 |
} |
} |
145 |
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146 |
/* Return the NM status register given the detected EEPROM (3620/3640) */ |
/* Return the NM status register given the detected EEPROM (3620/3640) */ |
147 |
static u_int nm_get_status_1(struct iofpga_data *d) |
static u_int nm_get_status_1(struct c3600_iofpga_data *d) |
148 |
{ |
{ |
149 |
u_int res = 0xFFFF; |
u_int res = 0xFFFF; |
150 |
int i; |
int i; |
151 |
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|
152 |
for(i=0;i<4;i++) { |
for(i=0;i<4;i++) { |
153 |
if (c3600_nm_check_eeprom(d->router,i)) |
if (vm_slot_get_card_ptr(d->router->vm,i)) |
154 |
res &= ~(0x1111 << i); |
res &= ~(0x1111 << i); |
155 |
} |
} |
156 |
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|
158 |
} |
} |
159 |
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|
160 |
/* Return the NM status register given the detected EEPROM (3660) */ |
/* Return the NM status register given the detected EEPROM (3660) */ |
161 |
static u_int nm_get_status_2(struct iofpga_data *d,u_int pos) |
static u_int nm_get_status_2(struct c3600_iofpga_data *d,u_int pos) |
162 |
{ |
{ |
163 |
u_int res = 0xFFFF; |
u_int res = 0xFFFF; |
164 |
u_int start,end; |
u_int start,end; |
178 |
} |
} |
179 |
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|
180 |
for(i=start;i<=end;i++) { |
for(i=start;i<=end;i++) { |
181 |
if (c3600_nm_check_eeprom(d->router,i)) |
if (vm_slot_get_card_ptr(d->router->vm,i)) |
182 |
res &= c3660_nm_masks[i-1]; |
res &= c3660_nm_masks[i-1]; |
183 |
} |
} |
184 |
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|
185 |
return(res); |
return(res); |
186 |
} |
} |
187 |
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188 |
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/* Update network interrupt status */ |
189 |
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static inline void |
190 |
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dev_c3620_c3640_iofpga_net_update_irq(struct c3600_iofpga_data *d) |
191 |
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{ |
192 |
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if (d->net_irq_status[0]) { |
193 |
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vm_set_irq(d->router->vm,C3600_NETIO_IRQ); |
194 |
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} else { |
195 |
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vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
196 |
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} |
197 |
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} |
198 |
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199 |
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static inline void |
200 |
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dev_c3660_iofpga_net_update_irq(struct c3600_iofpga_data *d) |
201 |
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{ |
202 |
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if (d->net_irq_status[0] || d->net_irq_status[1]) { |
203 |
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vm_set_irq(d->router->vm,C3600_NETIO_IRQ); |
204 |
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} else { |
205 |
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vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
206 |
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} |
207 |
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} |
208 |
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209 |
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/* Trigger a Network IRQ for the specified slot/port */ |
210 |
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void dev_c3600_iofpga_net_set_irq(struct c3600_iofpga_data *d, |
211 |
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u_int slot,u_int port) |
212 |
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{ |
213 |
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struct net_irq_distrib *irq_dist; |
214 |
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215 |
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#if DEBUG_NET_IRQ |
216 |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
217 |
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slot,port); |
218 |
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#endif |
219 |
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220 |
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irq_dist = &net_irq_dist[slot]; |
221 |
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222 |
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switch(c3600_chassis_get_id(d->router)) { |
223 |
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case 3620: |
224 |
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case 3640: |
225 |
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d->net_irq_status[0] |= (1 << (irq_dist->c3620_c3640_offset + port)); |
226 |
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dev_c3620_c3640_iofpga_net_update_irq(d); |
227 |
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break; |
228 |
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case 3660: |
229 |
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d->net_irq_status[irq_dist->c3660_reg] |= |
230 |
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(1 << (irq_dist->c3660_offset + port)); |
231 |
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dev_c3660_iofpga_net_update_irq(d); |
232 |
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break; |
233 |
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} |
234 |
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} |
235 |
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236 |
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/* Clear a Network IRQ for the specified slot/port */ |
237 |
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void dev_c3600_iofpga_net_clear_irq(struct c3600_iofpga_data *d, |
238 |
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u_int slot,u_int port) |
239 |
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{ |
240 |
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struct net_irq_distrib *irq_dist; |
241 |
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242 |
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#if DEBUG_NET_IRQ |
243 |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
244 |
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slot,port); |
245 |
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#endif |
246 |
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|
247 |
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irq_dist = &net_irq_dist[slot]; |
248 |
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|
249 |
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switch(c3600_chassis_get_id(d->router)) { |
250 |
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case 3620: |
251 |
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case 3640: |
252 |
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d->net_irq_status[0] &= ~(1 << (irq_dist->c3620_c3640_offset + port)); |
253 |
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dev_c3620_c3640_iofpga_net_update_irq(d); |
254 |
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break; |
255 |
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case 3660: |
256 |
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d->net_irq_status[irq_dist->c3660_reg] &= |
257 |
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~(1 << (irq_dist->c3660_offset + port)); |
258 |
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dev_c3660_iofpga_net_update_irq(d); |
259 |
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break; |
260 |
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} |
261 |
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} |
262 |
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|
263 |
/* |
/* |
264 |
* dev_c3620_c3640_iofpga_access() |
* dev_c3620_c3640_iofpga_access() |
265 |
*/ |
*/ |
266 |
static void * |
static void * |
267 |
dev_c3620_c3640_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
268 |
m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
269 |
m_uint64_t *data) |
m_uint64_t *data) |
270 |
{ |
{ |
271 |
struct iofpga_data *d = dev->priv_data; |
struct c3600_iofpga_data *d = dev->priv_data; |
|
u_int slot; |
|
272 |
|
|
273 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
274 |
*data = 0x0; |
*data = 0x0; |
277 |
if (offset != 0x0c) { |
if (offset != 0x0c) { |
278 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
279 |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
280 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
281 |
} else { |
} else { |
282 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
283 |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
284 |
offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
285 |
} |
} |
286 |
} |
} |
287 |
#endif |
#endif |
309 |
/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
310 |
case 0x0000e: |
case 0x0000e: |
311 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
312 |
nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
313 |
else |
else |
314 |
*data = nmc93c46_read(&d->router->mb_eeprom_group); |
*data = nmc93cX6_read(&d->router->mb_eeprom_group); |
315 |
break; |
break; |
316 |
|
|
317 |
case 0x10004: /* ??? OIR control ??? */ |
case 0x10004: /* ??? OIR control ??? */ |
343 |
if (op_type == MTS_WRITE) { |
if (op_type == MTS_WRITE) { |
344 |
d->eeprom_slot = *data & 0x03; |
d->eeprom_slot = *data & 0x03; |
345 |
nm_eeprom_select(d,d->eeprom_slot); |
nm_eeprom_select(d,d->eeprom_slot); |
346 |
nmc93c46_write(&d->router->nm_eeprom_group,*data); |
nmc93cX6_write(&d->router->nm_eeprom_group,*data); |
347 |
} else { |
} else { |
348 |
*data = nmc93c46_read(&d->router->nm_eeprom_group); |
*data = nmc93cX6_read(&d->router->nm_eeprom_group); |
349 |
} |
} |
350 |
break; |
break; |
351 |
|
|
352 |
/* Network interrupt status */ |
/* Network interrupt status */ |
353 |
case 0x20000: |
case 0x20000: /* slot 1 */ |
|
case 0x20001: |
|
|
case 0x20002: |
|
|
case 0x20003: |
|
|
/* XXX This doesn't seem to be correct (at least on 3620) */ |
|
|
slot = offset - 0x20000; |
|
|
|
|
354 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
355 |
*data = 0xFF; |
*data = d->net_irq_status[0] >> 24; |
356 |
|
break; |
357 |
if (++d->net_irq_clearing_count == C3600_NET_IRQ_CLEARING_DELAY) { |
case 0x20001: /* slot 0 */ |
358 |
vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
if (op_type == MTS_READ) |
359 |
d->net_irq_clearing_count = 0; |
*data = d->net_irq_status[0] >> 16; |
360 |
} |
break; |
361 |
|
case 0x20002: /* slot 3 */ |
362 |
|
if (op_type == MTS_READ) |
363 |
|
*data = d->net_irq_status[0] >> 8; |
364 |
|
break; |
365 |
|
case 0x20003: /* slot 2 */ |
366 |
|
if (op_type == MTS_READ) |
367 |
|
*data = d->net_irq_status[0]; |
368 |
break; |
break; |
369 |
|
|
370 |
/* |
/* |
453 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
454 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
455 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
456 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
457 |
} else { |
} else { |
458 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
459 |
"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
460 |
"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
461 |
|
offset,*data,cpu_get_pc(cpu),op_size); |
462 |
} |
} |
463 |
#endif |
#endif |
464 |
} |
} |
470 |
* dev_c3660_iofpga_access() |
* dev_c3660_iofpga_access() |
471 |
*/ |
*/ |
472 |
static void * |
static void * |
473 |
dev_c3660_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
474 |
m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
475 |
m_uint64_t *data) |
m_uint64_t *data) |
476 |
{ |
{ |
477 |
struct iofpga_data *d = dev->priv_data; |
struct c3600_iofpga_data *d = dev->priv_data; |
478 |
u_int slot; |
u_int slot; |
479 |
|
|
480 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
484 |
if (offset != 0x0c) { |
if (offset != 0x0c) { |
485 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
486 |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
487 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
488 |
} else { |
} else { |
489 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
490 |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
491 |
offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
492 |
} |
} |
493 |
} |
} |
494 |
#endif |
#endif |
575 |
*/ |
*/ |
576 |
case 0x10000: |
case 0x10000: |
577 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
578 |
nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
579 |
else |
else |
580 |
*data = nmc93c46_read(&d->router->mb_eeprom_group) | 0x80; |
*data = nmc93cX6_read(&d->router->mb_eeprom_group) | 0x80; |
581 |
break; |
break; |
582 |
|
|
583 |
/* NM EEPROMs - slots 1 to 6 */ |
/* NM EEPROMs - slots 1 to 6 */ |
590 |
slot = (offset - 0x1000a) + 1; |
slot = (offset - 0x1000a) + 1; |
591 |
|
|
592 |
if (op_type == MTS_WRITE) { |
if (op_type == MTS_WRITE) { |
593 |
nmc93c46_write(&d->router->c3660_nm_eeprom_group[slot], |
nmc93cX6_write(&d->router->c3660_nm_eeprom_group[slot], |
594 |
(u_int)(*data)); |
(u_int)(*data)); |
595 |
} else { |
} else { |
596 |
*data = nmc93c46_read(&d->router->c3660_nm_eeprom_group[slot]); |
*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[slot]); |
597 |
} |
} |
598 |
break; |
break; |
599 |
|
|
600 |
/* NM EEPROM - slot 0 */ |
/* NM EEPROM - slot 0 */ |
601 |
case 0x20006: |
case 0x20006: |
602 |
if (op_type == MTS_WRITE) { |
if (op_type == MTS_WRITE) { |
603 |
nmc93c46_write(&d->router->c3660_nm_eeprom_group[0], |
nmc93cX6_write(&d->router->c3660_nm_eeprom_group[0], |
604 |
(u_int)(*data)); |
(u_int)(*data)); |
605 |
} else { |
} else { |
606 |
*data = nmc93c46_read(&d->router->c3660_nm_eeprom_group[0]); |
*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[0]); |
607 |
} |
} |
608 |
break; |
break; |
609 |
|
|
650 |
*/ |
*/ |
651 |
case 0x10010: |
case 0x10010: |
652 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
653 |
*data = 0xFFFFFFFF; |
*data = d->net_irq_status[0]; |
|
vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
|
654 |
break; |
break; |
655 |
|
|
656 |
/* |
/* |
662 |
*/ |
*/ |
663 |
case 0x20010: |
case 0x20010: |
664 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
665 |
*data = 0x0F; |
*data = d->net_irq_status[1]; |
666 |
break; |
break; |
667 |
|
|
668 |
/* |
/* |
697 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
698 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
699 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
700 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
701 |
} else { |
} else { |
702 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
703 |
"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
704 |
"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
705 |
|
offset,*data,cpu_get_pc(cpu),op_size); |
706 |
} |
} |
707 |
#endif |
#endif |
708 |
} |
} |
728 |
/* Initialize NM EEPROM for 3660 */ |
/* Initialize NM EEPROM for 3660 */ |
729 |
for(i=0;i<C3600_MAX_NM_BAYS;i++) { |
for(i=0;i<C3600_MAX_NM_BAYS;i++) { |
730 |
router->c3660_nm_eeprom_group[i] = eeprom_nm_group; |
router->c3660_nm_eeprom_group[i] = eeprom_nm_group; |
731 |
router->c3660_nm_eeprom_group[i].eeprom[0] = &router->nm_bay[i].eeprom; |
router->c3660_nm_eeprom_group[i].eeprom[0] = NULL; |
732 |
} |
} |
733 |
} |
} |
734 |
|
|
735 |
/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |
736 |
void dev_c3600_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
static void |
737 |
|
dev_c3600_iofpga_shutdown(vm_instance_t *vm,struct c3600_iofpga_data *d) |
738 |
{ |
{ |
739 |
if (d != NULL) { |
if (d != NULL) { |
740 |
/* Remove the device */ |
/* Remove the device */ |
751 |
int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len) |
int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len) |
752 |
{ |
{ |
753 |
vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
754 |
struct iofpga_data *d; |
struct c3600_iofpga_data *d; |
755 |
|
|
756 |
/* Allocate private data structure */ |
/* Allocate private data structure */ |
757 |
if (!(d = malloc(sizeof(*d)))) { |
if (!(d = malloc(sizeof(*d)))) { |