1 |
/* |
/* |
2 |
* Cisco 2691 simulation platform. |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
4 |
*/ |
*/ |
5 |
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13 |
#include <pthread.h> |
#include <pthread.h> |
14 |
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15 |
#include "ptask.h" |
#include "ptask.h" |
16 |
#include "mips64.h" |
#include "cpu.h" |
17 |
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#include "vm.h" |
18 |
#include "dynamips.h" |
#include "dynamips.h" |
19 |
#include "memory.h" |
#include "memory.h" |
20 |
#include "device.h" |
#include "device.h" |
21 |
#include "dev_vtty.h" |
#include "dev_vtty.h" |
22 |
#include "nmc93c46.h" |
#include "nmc93cX6.h" |
23 |
#include "dev_c2691.h" |
#include "dev_c2691.h" |
24 |
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25 |
/* Debugging flags */ |
/* Debugging flags */ |
26 |
#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
27 |
#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
28 |
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#define DEBUG_NET_IRQ 0 |
29 |
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30 |
/* Definitions for Mainboard EEPROM */ |
/* Definitions for Mainboard EEPROM */ |
31 |
#define EEPROM_MB_DOUT 3 |
#define EEPROM_MB_DOUT 3 |
39 |
#define EEPROM_NM_CLK 2 |
#define EEPROM_NM_CLK 2 |
40 |
#define EEPROM_NM_CS 4 |
#define EEPROM_NM_CS 4 |
41 |
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42 |
#define C2691_NET_IRQ_CLEARING_DELAY 16 |
/* Network IRQ distribution */ |
43 |
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struct net_irq_distrib { |
44 |
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u_int reg; |
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u_int offset; |
46 |
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}; |
47 |
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48 |
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static struct net_irq_distrib net_irq_dist[C2691_MAX_NM_BAYS] = { |
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{ 0, 0 }, /* Slot 0: reg 0x26, 0x000000XX */ |
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{ 1, 0 }, /* Slot 1: reg 0x28, 0x000000XX */ |
51 |
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}; |
52 |
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53 |
/* IO FPGA structure */ |
/* IO FPGA structure */ |
54 |
struct iofpga_data { |
struct c2691_iofpga_data { |
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vm_obj_t vm_obj; |
vm_obj_t vm_obj; |
56 |
struct vdevice dev; |
struct vdevice dev; |
57 |
c2691_t *router; |
c2691_t *router; |
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/* |
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* Used to introduce a "delay" before clearing the network interrupt |
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* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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58 |
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59 |
/* Interrupt mask*/ |
/* Network IRQ status */ |
60 |
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m_uint16_t net_irq_status[2]; |
61 |
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62 |
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/* Interrupt mask */ |
63 |
m_uint16_t intr_mask; |
m_uint16_t intr_mask; |
64 |
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65 |
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/* WIC select */ |
66 |
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u_int wic_select; |
67 |
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u_int wic_cmd_pos; |
68 |
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u_int wic_cmd_valid; |
69 |
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m_uint16_t wic_cmd[2]; |
70 |
}; |
}; |
71 |
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72 |
/* Mainboard EEPROM definition */ |
/* Mainboard EEPROM definition */ |
73 |
static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
EEPROM_MB_DIN, EEPROM_MB_DOUT, |
76 |
}; |
}; |
77 |
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78 |
/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
79 |
static const struct nmc93c46_group eeprom_mb_group = { |
static const struct nmc93cX6_group eeprom_mb_group = { |
80 |
1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
81 |
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EEPROM_DORD_NORMAL, |
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EEPROM_DOUT_HIGH, |
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EEPROM_DEBUG_DISABLED, |
84 |
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"Mainboard EEPROM", |
85 |
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{ &eeprom_mb_def }, |
86 |
}; |
}; |
87 |
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/* NM EEPROM definition */ |
/* NM EEPROM definition */ |
89 |
static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
EEPROM_NM_DIN, EEPROM_NM_DOUT, |
92 |
}; |
}; |
93 |
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/* NM EEPROM */ |
/* NM EEPROM */ |
95 |
static const struct nmc93c46_group eeprom_nm_group = { |
static const struct nmc93cX6_group eeprom_nm_group = { |
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1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
97 |
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EEPROM_DORD_NORMAL, |
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EEPROM_DOUT_HIGH, |
99 |
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EEPROM_DEBUG_DISABLED, |
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"NM EEPROM", |
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{ &eeprom_nm_def }, |
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}; |
}; |
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/* Update network interrupt status */ |
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static inline void dev_c2691_iofpga_net_update_irq(struct c2691_iofpga_data *d) |
106 |
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{ |
107 |
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if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) { |
108 |
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vm_set_irq(d->router->vm,C2691_NETIO_IRQ); |
109 |
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} else { |
110 |
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vm_clear_irq(d->router->vm,C2691_NETIO_IRQ); |
111 |
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} |
112 |
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} |
113 |
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114 |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c2691_iofpga_net_set_irq(struct c2691_iofpga_data *d, |
116 |
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u_int slot,u_int port) |
117 |
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{ |
118 |
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struct net_irq_distrib *irq_dist; |
119 |
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120 |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
125 |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
126 |
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dev_c2691_iofpga_net_update_irq(d); |
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} |
128 |
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129 |
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/* Clear a Network IRQ for the specified slot/port */ |
130 |
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void dev_c2691_iofpga_net_clear_irq(struct c2691_iofpga_data *d, |
131 |
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u_int slot,u_int port) |
132 |
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{ |
133 |
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struct net_irq_distrib *irq_dist; |
134 |
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135 |
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#if DEBUG_NET_IRQ |
136 |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
137 |
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slot,port); |
138 |
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#endif |
139 |
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irq_dist = &net_irq_dist[slot]; |
140 |
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d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port)); |
141 |
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dev_c2691_iofpga_net_update_irq(d); |
142 |
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} |
143 |
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144 |
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/* Read a WIC EEPROM */ |
145 |
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static m_uint16_t dev_c2691_read_wic_eeprom(struct c2691_iofpga_data *d) |
146 |
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{ |
147 |
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struct cisco_eeprom *eeprom; |
148 |
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u_int wic_port; |
149 |
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u_int eeprom_offset; |
150 |
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m_uint8_t val[2]; |
151 |
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152 |
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switch(d->wic_select) { |
153 |
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case 0x1700: |
154 |
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wic_port = 0x10; |
155 |
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break; |
156 |
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case 0x1D00: |
157 |
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wic_port = 0x20; |
158 |
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break; |
159 |
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case 0x3500: |
160 |
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wic_port = 0x30; |
161 |
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break; |
162 |
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default: |
163 |
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wic_port = 0; |
164 |
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} |
165 |
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166 |
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/* No WIC in slot or no EEPROM: fake an empty EEPROM */ |
167 |
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if (!wic_port || !(eeprom = vm_slot_get_eeprom(d->router->vm,0,wic_port))) |
168 |
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return(0xFFFF); |
169 |
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170 |
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/* EEPROM offset is in the lowest 6 bits */ |
171 |
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eeprom_offset = d->wic_cmd[0] & 0x3F; |
172 |
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173 |
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cisco_eeprom_get_byte(eeprom,eeprom_offset,&val[0]); |
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cisco_eeprom_get_byte(eeprom,eeprom_offset+1,&val[1]); |
175 |
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return(((m_uint16_t)val[0] << 8) | val[1]); |
177 |
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} |
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/* |
/* |
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* dev_c2691_iofpga_access() |
* dev_c2691_iofpga_access() |
181 |
*/ |
*/ |
182 |
static void * |
static void * |
183 |
dev_c2691_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
dev_c2691_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
184 |
m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
185 |
m_uint64_t *data) |
m_uint64_t *data) |
186 |
{ |
{ |
187 |
struct iofpga_data *d = dev->priv_data; |
struct c2691_iofpga_data *d = dev->priv_data; |
188 |
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189 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
190 |
*data = 0x0; |
*data = 0x0; |
192 |
#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
193 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
194 |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
195 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
196 |
} else { |
} else { |
197 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
198 |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
199 |
offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
200 |
} |
} |
201 |
#endif |
#endif |
202 |
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213 |
/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
214 |
case 0x0e: |
case 0x0e: |
215 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
216 |
nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
217 |
else |
else |
218 |
*data = nmc93c46_read(&d->router->mb_eeprom_group); |
*data = nmc93cX6_read(&d->router->mb_eeprom_group); |
219 |
break; |
break; |
220 |
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case 0x12: |
case 0x12: |
222 |
/* |
/* |
223 |
* Bit 0: 1=No WIC in slot 0 ? |
* Bit 0: 1=No WIC in slot 0. |
224 |
* Bit 1: 1=No WIC in slot 1 ? |
* Bit 1: 1=No WIC in slot 1. |
225 |
* Bit 2: 1=No WIC in slot 2 ? |
* Bit 2: 1=No WIC in slot 2. |
226 |
*/ |
*/ |
227 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) { |
228 |
*data = 0x0007; |
*data = 0xFFFF; |
229 |
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230 |
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/* check WIC 0 */ |
231 |
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if (vm_slot_check_eeprom(d->router->vm,0,0x10)) |
232 |
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*data &= ~0x01; |
233 |
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234 |
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/* check WIC 1 */ |
235 |
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if (vm_slot_check_eeprom(d->router->vm,0,0x20)) |
236 |
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*data &= ~0x02; |
237 |
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238 |
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/* check WIC 2 */ |
239 |
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if (vm_slot_check_eeprom(d->router->vm,0,0x30)) |
240 |
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*data &= ~0x04; |
241 |
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} else { |
242 |
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d->wic_select = *data; |
243 |
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} |
244 |
break; |
break; |
245 |
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246 |
case 0x14: |
case 0x14: |
261 |
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262 |
/* WIC related: 16-bit data */ |
/* WIC related: 16-bit data */ |
263 |
case 0x42: |
case 0x42: |
264 |
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if (op_type == MTS_READ) { |
265 |
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if (d->wic_cmd_valid) { |
266 |
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*data = dev_c2691_read_wic_eeprom(d); |
267 |
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d->wic_cmd_valid = FALSE; |
268 |
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} else { |
269 |
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*data = 0xFFFF; |
270 |
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} |
271 |
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} else { |
272 |
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/* |
273 |
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* Store the EEPROM command (in 2 words). |
274 |
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* |
275 |
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* For a read, we have: |
276 |
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* Word 0: 0x180 (nmc93c46 READ) + offset (6-bits). |
277 |
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* Word 1: 0 (no data). |
278 |
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*/ |
279 |
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d->wic_cmd[d->wic_cmd_pos++] = *data; |
280 |
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281 |
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if (d->wic_cmd_pos == 2) { |
282 |
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d->wic_cmd_pos = 0; |
283 |
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d->wic_cmd_valid = TRUE; |
284 |
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} |
285 |
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} |
286 |
break; |
break; |
287 |
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288 |
/* NM Slot 1 EEPROM */ |
/* NM Slot 1 EEPROM */ |
289 |
case 0x44: |
case 0x44: |
290 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
291 |
nmc93c46_write(&d->router->nm_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->nm_eeprom_group,(u_int)(*data)); |
292 |
else |
else |
293 |
*data = nmc93c46_read(&d->router->nm_eeprom_group); |
*data = nmc93cX6_read(&d->router->nm_eeprom_group); |
294 |
break; |
break; |
295 |
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|
296 |
/* AIM EEPROM #0 */ |
/* AIM EEPROM #0 */ |
315 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
316 |
*data = 0xFFFF; |
*data = 0xFFFF; |
317 |
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|
318 |
if (c2691_nm_check_eeprom(d->router,1)) |
if (vm_slot_get_card_ptr(d->router->vm,1)) |
319 |
*data &= ~0x08; |
*data &= ~0x08; |
320 |
} |
} |
321 |
break; |
break; |
339 |
* Other bits unknown. |
* Other bits unknown. |
340 |
*/ |
*/ |
341 |
case 0x26: |
case 0x26: |
342 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) |
343 |
*data = 0xFFFE; |
*data = d->net_irq_status[0]; |
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vm_clear_irq(d->router->vm,C2691_NETIO_IRQ); |
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} |
|
344 |
break; |
break; |
345 |
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|
346 |
/* |
/* |
350 |
* Other bits unknown. |
* Other bits unknown. |
351 |
*/ |
*/ |
352 |
case 0x28: |
case 0x28: |
353 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) |
354 |
*data = 0xFFFE; |
*data = d->net_irq_status[1]; |
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vm_clear_irq(d->router->vm,C2691_NETIO_IRQ); |
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} |
|
355 |
break; |
break; |
356 |
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|
357 |
case 0x2c: |
case 0x2c: |
405 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
406 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
407 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
408 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
409 |
} else { |
} else { |
410 |
cpu_log(cpu,"IO_FPGA", |
cpu_log(cpu,"IO_FPGA", |
411 |
"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
412 |
"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
413 |
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offset,*data,cpu_get_pc(cpu),op_size); |
414 |
} |
} |
415 |
#endif |
#endif |
416 |
} |
} |
429 |
|
|
430 |
/* EEPROM for NM slot 1 */ |
/* EEPROM for NM slot 1 */ |
431 |
router->nm_eeprom_group = eeprom_nm_group; |
router->nm_eeprom_group = eeprom_nm_group; |
432 |
router->nm_eeprom_group.eeprom[0] = &router->nm_bay[1].eeprom; |
router->nm_eeprom_group.eeprom[0] = NULL; |
433 |
} |
} |
434 |
|
|
435 |
/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |
436 |
void dev_c2691_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
static void |
437 |
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dev_c2691_iofpga_shutdown(vm_instance_t *vm,struct c2691_iofpga_data *d) |
438 |
{ |
{ |
439 |
if (d != NULL) { |
if (d != NULL) { |
440 |
/* Remove the device */ |
/* Remove the device */ |
451 |
int dev_c2691_iofpga_init(c2691_t *router,m_uint64_t paddr,m_uint32_t len) |
int dev_c2691_iofpga_init(c2691_t *router,m_uint64_t paddr,m_uint32_t len) |
452 |
{ |
{ |
453 |
vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
454 |
struct iofpga_data *d; |
struct c2691_iofpga_data *d; |
455 |
|
|
456 |
/* Allocate private data structure */ |
/* Allocate private data structure */ |
457 |
if (!(d = malloc(sizeof(*d)))) { |
if (!(d = malloc(sizeof(*d)))) { |
461 |
|
|
462 |
memset(d,0,sizeof(*d)); |
memset(d,0,sizeof(*d)); |
463 |
d->router = router; |
d->router = router; |
464 |
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d->net_irq_status[0] = 0xFFFF; |
465 |
|
d->net_irq_status[1] = 0xFFFF; |
466 |
|
|
467 |
vm_object_init(&d->vm_obj); |
vm_object_init(&d->vm_obj); |
468 |
d->vm_obj.name = "io_fpga"; |
d->vm_obj.name = "io_fpga"; |