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/* |
/* |
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* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
*/ |
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#ifndef __MEMORY_H__ |
#ifndef __MEMORY_H__ |
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#define __MEMORY_H__ |
#define __MEMORY_H__ |
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#ifndef DYNAMIPS_ASM |
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#include <sys/types.h> |
#include <sys/types.h> |
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#include "utils.h" |
#include "utils.h" |
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#endif |
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/* MTS operation */ |
/* MTS operation */ |
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#define MTS_READ 0 |
#define MTS_READ 0 |
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#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
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#define MTS_ACC_U 0x00000006 /* Unexistent */ |
#define MTS_ACC_U 0x00000006 /* Unexistent */ |
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/* 32-bit Virtual Address seen by MTS */ |
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#define MTS32_LEVEL1_BITS 10 |
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#define MTS32_LEVEL2_BITS 10 |
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#define MTS32_OFFSET_BITS 12 |
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/* Each level-1 entry covers 4 Mb */ |
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#define MTS32_LEVEL1_SIZE (1 << (MTS32_LEVEL2_BITS + MTS32_OFFSET_BITS)) |
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#define MTS32_LEVEL1_MASK (MTS32_LEVEL1_SIZE - 1) |
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/* Each level-2 entry covers 4 Kb */ |
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#define MTS32_LEVEL2_SIZE (1 << MTS32_OFFSET_BITS) |
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#define MTS32_LEVEL2_MASK (MTS32_LEVEL2_SIZE - 1) |
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/* Hash table size for MTS64 (default: [shift:16,bits:12]) */ |
/* Hash table size for MTS64 (default: [shift:16,bits:12]) */ |
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#define MTS64_HASH_SHIFT 15 |
#define MTS64_HASH_SHIFT 12 |
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#define MTS64_HASH_BITS 15 |
#define MTS64_HASH_BITS 14 |
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#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS) |
#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS) |
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#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1) |
#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1) |
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/* MTS64 hash on virtual addresses */ |
/* MTS64 hash on virtual addresses */ |
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#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK) |
#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK) |
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/* Number of entries per chunk */ |
/* Hash table size for MTS32 (default: [shift:15,bits:15]) */ |
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#define MTS64_CHUNK_SIZE 256 |
#define MTS32_HASH_SHIFT 12 |
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#define MTS32_HASH_BITS 14 |
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#define MTS32_HASH_SIZE (1 << MTS32_HASH_BITS) |
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#define MTS32_HASH_MASK (MTS32_HASH_SIZE - 1) |
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#ifndef DYNAMIPS_ASM |
/* MTS32 hash on virtual addresses */ |
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/* MTS32: Level 1 & 2 arrays */ |
#define MTS32_HASH(vaddr) (((vaddr) >> MTS32_HASH_SHIFT) & MTS32_HASH_MASK) |
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typedef struct mts32_l1_array mts32_l1_array_t; |
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struct mts32_l1_array { |
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m_iptr_t entry[1 << MTS32_LEVEL1_BITS]; |
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}; |
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typedef struct mts32_l2_array mts32_l2_array_t; |
/* Number of entries per chunk */ |
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struct mts32_l2_array { |
#define MTS64_CHUNK_SIZE 256 |
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m_iptr_t entry[1 << MTS32_LEVEL2_BITS]; |
#define MTS32_CHUNK_SIZE 256 |
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mts32_l2_array_t *next; |
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}; |
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/* MTS64: chunk definition */ |
/* MTS64: chunk definition */ |
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struct mts64_chunk { |
struct mts64_chunk { |
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u_int count; |
u_int count; |
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}; |
}; |
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/* Show the last memory accesses */ |
/* MTS32: chunk definition */ |
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void memlog_dump(cpu_mips_t *cpu); |
struct mts32_chunk { |
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mts32_entry_t entry[MTS32_CHUNK_SIZE]; |
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/* Allocate an L1 array */ |
struct mts32_chunk *next; |
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mts32_l1_array_t *mts32_alloc_l1_array(m_iptr_t val); |
u_int count; |
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}; |
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/* Allocate an L2 array */ |
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mts32_l2_array_t *mts32_alloc_l2_array(cpu_mips_t *cpu,m_iptr_t val); |
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/* Initialize an empty MTS32 subsystem */ |
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int mts32_init_empty(cpu_mips_t *cpu); |
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/* Free memory used by MTS32 */ |
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void mts32_shutdown(cpu_mips_t *cpu); |
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/* Map a physical address to the specified virtual address */ |
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void mts32_map(cpu_mips_t *cpu,m_uint64_t vaddr, |
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m_uint64_t paddr,m_uint32_t len, |
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int cache_access); |
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/* Unmap a memory zone */ |
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void mts32_unmap(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len, |
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m_uint32_t val); |
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/* Map all devices for kernel mode */ |
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void mts32_km_map_all_dev(cpu_mips_t *cpu); |
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/* Initialize the MTS64 subsystem for the specified CPU */ |
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int mts64_init(cpu_mips_t *cpu); |
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/* Free memory used by MTS64 */ |
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void mts64_shutdown(cpu_mips_t *cpu); |
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/* Show MTS64 detailed information (debugging only!) */ |
/* Record a memory access */ |
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void mts64_show_stats(cpu_mips_t *cpu); |
void memlog_rec_access(cpu_gen_t *cpu,m_uint64_t vaddr,m_uint64_t data, |
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m_uint32_t op_size,m_uint32_t op_type); |
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/* Initialize memory access vectors */ |
/* Show the last memory accesses */ |
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void mts_init_memop_vectors(cpu_mips_t *cpu); |
void memlog_dump(cpu_gen_t *cpu); |
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/* Shutdown MTS subsystem */ |
/* Update the data obtained by a read access */ |
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void mts_shutdown(cpu_mips_t *cpu); |
void memlog_update_read(cpu_gen_t *cpu,m_iptr_t raddr); |
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/* Copy a memory block from VM physical RAM to real host */ |
/* Copy a memory block from VM physical RAM to real host */ |
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void physmem_copy_from_vm(vm_instance_t *vm,void *real_buffer, |
void physmem_copy_from_vm(vm_instance_t *vm,void *real_buffer, |
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/* Copy a 16-bit word to the VM physical RAM from real host */ |
/* Copy a 16-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u16_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint16_t val); |
void physmem_copy_u16_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint16_t val); |
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/* Copy a byte from the VM physical RAM to real host */ |
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m_uint8_t physmem_copy_u8_from_vm(vm_instance_t *vm,m_uint64_t paddr); |
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/* Copy a 16-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u8_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint8_t val); |
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/* DMA transfer operation */ |
/* DMA transfer operation */ |
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void physmem_dma_transfer(vm_instance_t *vm,m_uint64_t src,m_uint64_t dst, |
void physmem_dma_transfer(vm_instance_t *vm,m_uint64_t src,m_uint64_t dst, |
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size_t len); |
size_t len); |
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/* Physical memory dump (32-bit words) */ |
/* Physical memory dump (32-bit words) */ |
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void physmem_dump_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint32_t u32_count); |
void physmem_dump_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint32_t u32_count); |
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#endif /* DYNAMIPS_ASM */ |
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#endif |
#endif |