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dpavlin |
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/* |
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dpavlin |
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* Cisco router simulation platform. |
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dpavlin |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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#include "nmc93cX6.h" |
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#include "dev_c2691.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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#define DEBUG_NET_IRQ 0 |
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|
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/* Definitions for Mainboard EEPROM */ |
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#define EEPROM_MB_DOUT 3 |
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#define EEPROM_MB_DIN 2 |
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#define EEPROM_MB_CLK 1 |
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#define EEPROM_MB_CS 0 |
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/* Definitions for Network Modules EEPROM */ |
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#define EEPROM_NM_DOUT 7 |
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#define EEPROM_NM_DIN 6 |
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#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
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dpavlin |
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/* Network IRQ distribution */ |
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struct net_irq_distrib { |
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u_int reg; |
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u_int offset; |
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}; |
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static struct net_irq_distrib net_irq_dist[C2691_MAX_NM_BAYS] = { |
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{ 0, 0 }, /* Slot 0: reg 0x26, 0x000000XX */ |
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{ 1, 0 }, /* Slot 1: reg 0x28, 0x000000XX */ |
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}; |
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/* IO FPGA structure */ |
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struct c2691_iofpga_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c2691_t *router; |
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dpavlin |
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/* Network IRQ status */ |
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m_uint16_t net_irq_status[2]; |
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/* Interrupt mask */ |
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m_uint16_t intr_mask; |
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}; |
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/* Mainboard EEPROM definition */ |
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static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
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/* Mainboard EEPROM */ |
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static const struct nmc93cX6_group eeprom_mb_group = { |
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EEPROM_TYPE_NMC93C46, 1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
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}; |
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/* NM EEPROM definition */ |
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static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
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/* NM EEPROM */ |
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static const struct nmc93cX6_group eeprom_nm_group = { |
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EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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}; |
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/* Update network interrupt status */ |
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static inline void dev_c2691_iofpga_net_update_irq(struct c2691_iofpga_data *d) |
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{ |
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if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) { |
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vm_set_irq(d->router->vm,C2691_NETIO_IRQ); |
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} else { |
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vm_clear_irq(d->router->vm,C2691_NETIO_IRQ); |
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} |
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} |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c2691_iofpga_net_set_irq(struct c2691_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
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dev_c2691_iofpga_net_update_irq(d); |
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} |
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/* Clear a Network IRQ for the specified slot/port */ |
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void dev_c2691_iofpga_net_clear_irq(struct c2691_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port)); |
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dev_c2691_iofpga_net_update_irq(d); |
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} |
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dpavlin |
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/* |
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* dev_c2691_iofpga_access() |
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*/ |
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static void * |
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dev_c2691_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct c2691_iofpga_data *d = dev->priv_data; |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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} |
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#endif |
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switch(offset) { |
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/* |
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dpavlin |
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* Platform type ? |
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* 0x04 and 0x05 seem to work. |
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*/ |
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case 0x36: |
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if (op_type == MTS_READ) |
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*data = 0x04 << 5; |
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break; |
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/* Mainboard EEPROM */ |
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case 0x0e: |
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if (op_type == MTS_WRITE) |
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nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
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else |
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*data = nmc93cX6_read(&d->router->mb_eeprom_group); |
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break; |
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case 0x12: |
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/* |
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* Bit 0: 1=No WIC in slot 0 ? |
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* Bit 1: 1=No WIC in slot 1 ? |
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* Bit 2: 1=No WIC in slot 2 ? |
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*/ |
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if (op_type == MTS_READ) |
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*data = 0x0007; |
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break; |
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case 0x14: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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case 0x18: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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/* wic/vwic related */ |
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case 0x40: |
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if (op_type == MTS_READ) |
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*data = 0x0004; |
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break; |
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/* WIC related: 16-bit data */ |
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case 0x42: |
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break; |
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200 |
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/* NM Slot 1 EEPROM */ |
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case 0x44: |
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if (op_type == MTS_WRITE) |
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dpavlin |
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nmc93cX6_write(&d->router->nm_eeprom_group,(u_int)(*data)); |
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else |
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dpavlin |
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*data = nmc93cX6_read(&d->router->nm_eeprom_group); |
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break; |
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/* AIM EEPROM #0 */ |
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case 0x48: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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/* AIM EEPROM #1 */ |
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case 0x4a: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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220 |
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/* |
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* NM Presence. |
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* |
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* Bit 7: 0=NM present in slot 1. |
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* Other bits unknown. |
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*/ |
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case 0x20: |
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if (op_type == MTS_READ) { |
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*data = 0xFFFF; |
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if (c2691_nm_check_eeprom(d->router,1)) |
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*data &= ~0x08; |
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} |
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break; |
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/* ??? */ |
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case 0x24: |
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break; |
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239 |
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/* Intr Mask (sh platform) */ |
240 |
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case 0x30: |
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if (op_type == MTS_READ) |
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*data = d->intr_mask; |
243 |
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else |
244 |
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d->intr_mask = *data; |
245 |
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break; |
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247 |
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/* |
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* Network interrupt status. |
249 |
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* |
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* Bit 0: 0 = GT96100 Ethernet ports. |
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* Other bits unknown. |
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*/ |
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case 0x26: |
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dpavlin |
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if (op_type == MTS_READ) |
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*data = d->net_irq_status[0]; |
256 |
dpavlin |
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break; |
257 |
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258 |
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/* |
259 |
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* Network interrupt status. |
260 |
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* |
261 |
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* Bit 0: 0 = NM in Slot 1. |
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* Other bits unknown. |
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*/ |
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case 0x28: |
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dpavlin |
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if (op_type == MTS_READ) |
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*data = d->net_irq_status[1]; |
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dpavlin |
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break; |
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269 |
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case 0x2c: |
270 |
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if (op_type == MTS_READ) |
271 |
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*data = 0xFFFF; |
272 |
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break; |
273 |
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274 |
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/* OIR interrupt but not supported (IRQ 6) */ |
275 |
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case 0x2e: |
276 |
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if (op_type == MTS_READ) |
277 |
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*data = 0xFFFF; |
278 |
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break; |
279 |
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280 |
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/* |
281 |
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* Environmental monitor, determined with "sh env all". |
282 |
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* |
283 |
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* Bit 0: 1 = Fan Error |
284 |
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* Bit 1: 1 = Fan Error |
285 |
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* Bit 2: 1 = Over-temperature |
286 |
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* Bit 3: ??? |
287 |
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* Bit 4: 0 = RPS present. |
288 |
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* Bit 5: 0 = Input Voltage status failure. |
289 |
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* Bit 6: 1 = Thermal status failure. |
290 |
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* Bit 7: 1 = DC Output Voltage status failure. |
291 |
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*/ |
292 |
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case 0x3a: |
293 |
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if (op_type == MTS_READ) |
294 |
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*data = 0x0020; |
295 |
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break; |
296 |
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297 |
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/* |
298 |
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* Bit 0: Slot0 Compact Flash presence. |
299 |
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* Bit 1: System Compact Flash presence. |
300 |
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*/ |
301 |
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case 0x3c: |
302 |
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if (op_type == MTS_READ) { |
303 |
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*data = 0xFFFF; |
304 |
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305 |
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/* System Flash ? */ |
306 |
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if (cpu->vm->pcmcia_disk_size[0]) |
307 |
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*data &= ~0x02; |
308 |
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309 |
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/* Slot0 Flash ? */ |
310 |
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if (cpu->vm->pcmcia_disk_size[1]) |
311 |
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*data &= ~0x01; |
312 |
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} |
313 |
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break; |
314 |
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315 |
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#if DEBUG_UNKNOWN |
316 |
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default: |
317 |
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if (op_type == MTS_READ) { |
318 |
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cpu_log(cpu,"IO_FPGA", |
319 |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
320 |
dpavlin |
7 |
offset,cpu_get_pc(cpu),op_size); |
321 |
dpavlin |
4 |
} else { |
322 |
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cpu_log(cpu,"IO_FPGA", |
323 |
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"write to unknown addr 0x%x, value=0x%llx, " |
324 |
dpavlin |
7 |
"pc=0x%llx (size=%u)\n", |
325 |
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offset,*data,cpu_get_pc(cpu),op_size); |
326 |
dpavlin |
4 |
} |
327 |
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#endif |
328 |
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} |
329 |
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330 |
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return NULL; |
331 |
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} |
332 |
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333 |
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/* Initialize EEPROM groups */ |
334 |
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void c2691_init_eeprom_groups(c2691_t *router) |
335 |
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{ |
336 |
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/* Initialize Mainboard EEPROM */ |
337 |
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router->mb_eeprom_group = eeprom_mb_group; |
338 |
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router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom; |
339 |
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router->mb_eeprom.data = NULL; |
340 |
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router->mb_eeprom.len = 0; |
341 |
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342 |
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/* EEPROM for NM slot 1 */ |
343 |
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router->nm_eeprom_group = eeprom_nm_group; |
344 |
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router->nm_eeprom_group.eeprom[0] = &router->nm_bay[1].eeprom; |
345 |
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} |
346 |
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347 |
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/* Shutdown the IO FPGA device */ |
348 |
dpavlin |
8 |
static void |
349 |
|
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dev_c2691_iofpga_shutdown(vm_instance_t *vm,struct c2691_iofpga_data *d) |
350 |
dpavlin |
4 |
{ |
351 |
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if (d != NULL) { |
352 |
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/* Remove the device */ |
353 |
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dev_remove(vm,&d->dev); |
354 |
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355 |
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/* Free the structure itself */ |
356 |
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free(d); |
357 |
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} |
358 |
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} |
359 |
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360 |
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/* |
361 |
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* dev_c2691_iofpga_init() |
362 |
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*/ |
363 |
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int dev_c2691_iofpga_init(c2691_t *router,m_uint64_t paddr,m_uint32_t len) |
364 |
|
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{ |
365 |
|
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vm_instance_t *vm = router->vm; |
366 |
dpavlin |
8 |
struct c2691_iofpga_data *d; |
367 |
dpavlin |
4 |
|
368 |
|
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/* Allocate private data structure */ |
369 |
|
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if (!(d = malloc(sizeof(*d)))) { |
370 |
|
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fprintf(stderr,"IO_FPGA: out of memory\n"); |
371 |
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return(-1); |
372 |
|
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} |
373 |
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374 |
|
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memset(d,0,sizeof(*d)); |
375 |
|
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d->router = router; |
376 |
dpavlin |
8 |
d->net_irq_status[0] = 0xFFFF; |
377 |
|
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d->net_irq_status[1] = 0xFFFF; |
378 |
dpavlin |
4 |
|
379 |
|
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vm_object_init(&d->vm_obj); |
380 |
|
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d->vm_obj.name = "io_fpga"; |
381 |
|
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d->vm_obj.data = d; |
382 |
|
|
d->vm_obj.shutdown = (vm_shutdown_t)dev_c2691_iofpga_shutdown; |
383 |
|
|
|
384 |
|
|
/* Set device properties */ |
385 |
|
|
dev_init(&d->dev); |
386 |
|
|
d->dev.name = "io_fpga"; |
387 |
|
|
d->dev.phys_addr = paddr; |
388 |
|
|
d->dev.phys_len = len; |
389 |
|
|
d->dev.priv_data = d; |
390 |
|
|
d->dev.handler = dev_c2691_iofpga_access; |
391 |
|
|
|
392 |
|
|
/* Map this device to the VM */ |
393 |
|
|
vm_bind_device(router->vm,&d->dev); |
394 |
|
|
vm_object_add(vm,&d->vm_obj); |
395 |
|
|
return(0); |
396 |
|
|
} |