68 |
#define PPC32_EXC_TRACE 0x00000D00 /* Trace */ |
#define PPC32_EXC_TRACE 0x00000D00 /* Trace */ |
69 |
#define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */ |
#define PPC32_EXC_FPU_HLP 0x00000E00 /* Floating-Point Assist */ |
70 |
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71 |
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/* Condition Register (CR) is accessed through 8 fields of 4 bits */ |
72 |
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#define ppc32_get_cr_field(n) ((n) >> 2) |
73 |
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#define ppc32_get_cr_bit(n) (~(n) & 0x03) |
74 |
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75 |
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/* Positions of LT, GT, EQ and SO bits in CR fields */ |
76 |
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#define PPC32_CR_LT_BIT 3 |
77 |
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#define PPC32_CR_GT_BIT 2 |
78 |
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#define PPC32_CR_EQ_BIT 1 |
79 |
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#define PPC32_CR_SO_BIT 0 |
80 |
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81 |
/* CR0 (Condition Register Field 0) bits */ |
/* CR0 (Condition Register Field 0) bits */ |
82 |
#define PPC32_CR0_LT_BIT 31 |
#define PPC32_CR0_LT_BIT 31 |
83 |
#define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */ |
#define PPC32_CR0_LT (1 << PPC32_CR0_LT_BIT) /* Negative */ |
291 |
volatile m_uint32_t irq_pending,irq_check; |
volatile m_uint32_t irq_pending,irq_check; |
292 |
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293 |
/* XER, Condition Register, Link Register, Count Register */ |
/* XER, Condition Register, Link Register, Count Register */ |
294 |
m_uint32_t xer,cr,lr,ctr,reserve; |
m_uint32_t xer,lr,ctr,reserve; |
295 |
m_uint32_t xer_ca; |
m_uint32_t xer_ca; |
296 |
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297 |
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/* Condition Register (CR) fields */ |
298 |
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u_int cr_fields[8]; |
299 |
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300 |
/* MTS caches (Instruction+Data) */ |
/* MTS caches (Instruction+Data) */ |
301 |
mts32_entry_t *mts_cache[2]; |
mts32_entry_t *mts_cache[2]; |
302 |
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303 |
/* Code page translation cache */ |
/* Code page translation cache and physical page mapping */ |
304 |
ppc32_jit_tcb_t **exec_phys_map; |
ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map; |
305 |
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306 |
/* Virtual address to physical page translation */ |
/* Virtual address to physical page translation */ |
307 |
fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid, |
fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid, |
404 |
/* Fast memory operations use */ |
/* Fast memory operations use */ |
405 |
u_int fast_memop; |
u_int fast_memop; |
406 |
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407 |
/* IRQ idling preemption */ |
/* Direct block jump */ |
408 |
u_int irq_idle_preempt[32]; |
u_int exec_blk_direct_jump; |
409 |
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410 |
/* Current exec page (non-JIT) info */ |
/* Current exec page (non-JIT) info */ |
411 |
m_uint64_t njm_exec_page; |
m_uint64_t njm_exec_page; |
422 |
u_int breakpoints_enabled; |
u_int breakpoints_enabled; |
423 |
}; |
}; |
424 |
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425 |
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#define PPC32_CR_FIELD_OFFSET(f) \ |
426 |
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(OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int))) |
427 |
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428 |
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/* Get the full CR register */ |
429 |
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static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu) |
430 |
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{ |
431 |
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m_uint32_t cr = 0; |
432 |
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int i; |
433 |
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434 |
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for(i=0;i<8;i++) |
435 |
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cr |= cpu->cr_fields[i] << (28 - (i << 2)); |
436 |
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437 |
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return(cr); |
438 |
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} |
439 |
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440 |
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/* Set the CR fields given a CR value */ |
441 |
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static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr) |
442 |
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{ |
443 |
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int i; |
444 |
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445 |
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for(i=0;i<8;i++) |
446 |
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cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F; |
447 |
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} |
448 |
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449 |
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/* Get a CR bit */ |
450 |
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static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit) |
451 |
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{ |
452 |
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m_uint32_t res; |
453 |
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454 |
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res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit); |
455 |
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return(res & 0x01); |
456 |
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} |
457 |
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458 |
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/* Set a CR bit */ |
459 |
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static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit) |
460 |
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{ |
461 |
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cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit); |
462 |
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} |
463 |
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464 |
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/* Clear a CR bit */ |
465 |
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static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit) |
466 |
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{ |
467 |
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cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit)); |
468 |
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} |
469 |
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470 |
/* Reset a PowerPC CPU */ |
/* Reset a PowerPC CPU */ |
471 |
int ppc32_reset(cpu_ppc_t *cpu); |
int ppc32_reset(cpu_ppc_t *cpu); |
472 |
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