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/* |
/* |
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* Cisco C7200 (Predator) Simulation Platform. |
* Cisco router simulation platform. |
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* Copyright (C) 2005,2006 Christophe Fillot. All rights reserved. |
* Copyright (C) 2005,2006 Christophe Fillot. All rights reserved. |
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* |
* |
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* Serial Interfaces (Mueslix). |
* Serial Interfaces (Mueslix). |
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#include <errno.h> |
#include <errno.h> |
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#include <assert.h> |
#include <assert.h> |
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|
|
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#include "mips64.h" |
#include "cpu.h" |
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|
#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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/* |
/* |
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* Access to channel registers. |
* Access to channel registers. |
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*/ |
*/ |
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void dev_mueslix_chan_access(cpu_mips_t *cpu,struct mueslix_channel *channel, |
void dev_mueslix_chan_access(cpu_gen_t *cpu,struct mueslix_channel *channel, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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/* |
/* |
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* dev_mueslix_access() |
* dev_mueslix_access() |
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*/ |
*/ |
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void *dev_mueslix_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset, |
void *dev_mueslix_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset, |
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u_int op_size,u_int op_type,m_uint64_t *data) |
u_int op_size,u_int op_type,m_uint64_t *data) |
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{ |
{ |
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struct mueslix_data *d = dev->priv_data; |
struct mueslix_data *d = dev->priv_data; |
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#if DEBUG_ACCESS >= 2 |
#if DEBUG_ACCESS >= 2 |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name,"read access to offset=0x%x, pc=0x%llx, size=%u\n", |
cpu_log(cpu,d->name,"read access to offset=0x%x, pc=0x%llx, size=%u\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,d->name,"write access to offset=0x%x, pc=0x%llx, " |
cpu_log(cpu,d->name,"write access to offset=0x%x, pc=0x%llx, " |
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"val=0x%llx, size=%u\n",offset,cpu->pc,*data,op_size); |
"val=0x%llx, size=%u\n",offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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#endif |
#endif |
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|
|
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"channel_enable_mask = 0x%5.5llx at pc=0x%llx\n", |
"channel_enable_mask = 0x%5.5llx at pc=0x%llx\n", |
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*data,cpu->pc); |
*data,cpu_get_pc(cpu)); |
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#endif |
#endif |
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d->channel_enable_mask = *data; |
d->channel_enable_mask = *data; |
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} |
} |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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if (op_type == MTS_WRITE) { |
if (op_type == MTS_WRITE) { |
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cpu_log(cpu,d->name,"cmd_reg = 0x%5.5llx at pc=0x%llx\n", |
cpu_log(cpu,d->name,"cmd_reg = 0x%5.5llx at pc=0x%llx\n", |
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*data,cpu->pc); |
*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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switch(d->chip_mode) { |
switch(d->chip_mode) { |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,d->name, |
cpu_log(cpu,d->name, |
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"write to unknown addr 0x%x, value=0x%llx, " |
"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
"pc=0x%llx (size=%u)\n", |
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|
offset,*data,cpu_get_pc(cpu),op_size); |
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} |
} |
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#endif |
#endif |
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} |
} |
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} |
} |
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|
|
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/* pci_mueslix_read() */ |
/* pci_mueslix_read() */ |
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static m_uint32_t pci_mueslix_read(cpu_mips_t *cpu,struct pci_device *dev, |
static m_uint32_t pci_mueslix_read(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg) |
int reg) |
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{ |
{ |
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struct mueslix_data *d = dev->priv_data; |
struct mueslix_data *d = dev->priv_data; |
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} |
} |
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|
|
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/* pci_mueslix_write() */ |
/* pci_mueslix_write() */ |
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static void pci_mueslix_write(cpu_mips_t *cpu,struct pci_device *dev, |
static void pci_mueslix_write(cpu_gen_t *cpu,struct pci_device *dev, |
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int reg,m_uint32_t value) |
int reg,m_uint32_t value) |
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{ |
{ |
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struct mueslix_data *d = dev->priv_data; |
struct mueslix_data *d = dev->priv_data; |