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#include "net.h" |
#include "net.h" |
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#include "device.h" |
#include "device.h" |
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#include "pci_dev.h" |
#include "pci_dev.h" |
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#include "nmc93c46.h" |
#include "nmc93cX6.h" |
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#include "dev_mv64460.h" |
#include "dev_mv64460.h" |
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#include "net_io.h" |
#include "net_io.h" |
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#include "vm.h" |
#include "vm.h" |
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/* C7200 Error/OIR Interrupt */ |
/* C7200 Error/OIR Interrupt */ |
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#define C7200_OIR_IRQ 6 |
#define C7200_OIR_IRQ 6 |
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/* Network IRQ */ |
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#define C7200_NETIO_IRQ_BASE 32 |
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#define C7200_NETIO_IRQ_PORT_BITS 3 |
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#define C7200_NETIO_IRQ_PORT_MASK ((1 << C7200_NETIO_IRQ_PORT_BITS) - 1) |
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#define C7200_NETIO_IRQ_PER_SLOT (1 << C7200_NETIO_IRQ_PORT_BITS) |
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#define C7200_NETIO_IRQ_END \ |
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(C7200_NETIO_IRQ_BASE + (C7200_MAX_PA_BAYS * C7200_NETIO_IRQ_PER_SLOT) - 1) |
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/* C7200 base ram limit (256 Mb) */ |
/* C7200 base ram limit (256 Mb) */ |
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#define C7200_BASE_RAM_LIMIT 256 |
#define C7200_BASE_RAM_LIMIT 256 |
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/* MV64460 device for NPE-G2 */ |
/* MV64460 device for NPE-G2 */ |
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struct mv64460_data *mv64460_sysctr; |
struct mv64460_data *mv64460_sysctr; |
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/* Midplane FPGA */ |
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struct c7200_mpfpga_data *mpfpga_data; |
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/* NPE and PA information */ |
/* NPE and PA information */ |
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struct c7200_npe_driver *npe_driver; |
struct c7200_npe_driver *npe_driver; |
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struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS]; |
struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS]; |
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/* Midplane EEPROM can be modified to change the chassis MAC address... */ |
/* Midplane EEPROM can be modified to change the chassis MAC address... */ |
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struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom; |
struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom; |
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struct nmc93c46_group sys_eeprom_g1; /* EEPROMs for CPU and Midplane */ |
struct nmc93cX6_group sys_eeprom_g1; /* EEPROMs for CPU and Midplane */ |
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struct nmc93c46_group sys_eeprom_g2; /* EEPROM for PEM */ |
struct nmc93cX6_group sys_eeprom_g2; /* EEPROM for PEM */ |
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struct nmc93c46_group pa_eeprom_g1; /* EEPROMs for bays 0, 1, 3, 4 */ |
struct nmc93cX6_group pa_eeprom_g1; /* EEPROMs for bays 0, 1, 3, 4 */ |
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struct nmc93c46_group pa_eeprom_g2; /* EEPROMs for bays 2, 5, 6 */ |
struct nmc93cX6_group pa_eeprom_g2; /* EEPROMs for bays 2, 5, 6 */ |
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}; |
}; |
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/* Initialize EEPROM groups */ |
/* Initialize EEPROM groups */ |
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/* Save configurations of all C7200 instances */ |
/* Save configurations of all C7200 instances */ |
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void c7200_save_config_all(FILE *fd); |
void c7200_save_config_all(FILE *fd); |
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/* Get network IRQ for specified slot/port */ |
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u_int c7200_net_irq_for_slot_port(u_int slot,u_int port); |
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/* Set PA EEPROM definition */ |
/* Set PA EEPROM definition */ |
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int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay, |
int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay, |
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const struct cisco_eeprom *eeprom); |
const struct cisco_eeprom *eeprom); |
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/* dev_c7200_iofpga_init() */ |
/* dev_c7200_iofpga_init() */ |
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int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* dev_mpfpga_init() */ |
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int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* PA drivers */ |
/* PA drivers */ |
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extern struct c7200_pa_driver dev_c7200_iocard_fe_driver; |
extern struct c7200_pa_driver dev_c7200_iocard_fe_driver; |
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extern struct c7200_pa_driver dev_c7200_iocard_2fe_driver; |
extern struct c7200_pa_driver dev_c7200_iocard_2fe_driver; |