/[dynamips]/upstream/dynamips-0.2.7-RC2/dev_c3745_iofpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.7-RC1/dev_c3745_iofpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC upstream/dynamips-0.2.7-RC2/dev_c3745_iofpga.c revision 8 by dpavlin, Sat Oct 6 16:24:54 2007 UTC
# Line 21  Line 21 
21  #include "memory.h"  #include "memory.h"
22  #include "device.h"  #include "device.h"
23  #include "dev_vtty.h"  #include "dev_vtty.h"
24  #include "nmc93c46.h"  #include "nmc93cX6.h"
25  #include "dev_c3745.h"  #include "dev_c3745.h"
26    
27  /* Debugging flags */  /* Debugging flags */
28  #define DEBUG_UNKNOWN   1  #define DEBUG_UNKNOWN   1
29  #define DEBUG_ACCESS    0  #define DEBUG_ACCESS    0
30    #define DEBUG_NET_IRQ   0
31    
32  /* Definitions for Motherboard EEPROM (0x00) */  /* Definitions for Motherboard EEPROM (0x00) */
33  #define EEPROM_MB_DOUT  3  #define EEPROM_MB_DOUT  3
# Line 52  Line 53 
53  #define EEPROM_NM_CLK   2  #define EEPROM_NM_CLK   2
54  #define EEPROM_NM_CS    4  #define EEPROM_NM_CS    4
55    
56  #define C3745_NET_IRQ_CLEARING_DELAY  16  /* Network IRQ distribution */
57    struct net_irq_distrib  {
58       u_int reg;
59       u_int offset;
60    };
61    
62    static struct net_irq_distrib net_irq_dist[C3745_MAX_NM_BAYS] = {
63       { 0,  0  },  /* Slot 0: reg 0x20, 0x00XX */
64       { 1,  0  },  /* Slot 1: reg 0x22, 0x000X */
65       { 1,  4  },  /* Slot 2: reg 0x22, 0x00X0 */
66       { 1,  8  },  /* Slot 3: reg 0x22, 0x0X00 */
67       { 1,  12 },  /* Slot 4: reg 0x22, 0xX000 */
68    };
69    
70  /* IO FPGA structure */  /* IO FPGA structure */
71  struct iofpga_data {  struct c3745_iofpga_data {
72     vm_obj_t vm_obj;     vm_obj_t vm_obj;
73     struct vdevice dev;     struct vdevice dev;
74     c3745_t *router;     c3745_t *router;
75        
76     /*     /* Network IRQ status */
77      * Used to introduce a "delay" before clearing the network interrupt     m_uint16_t net_irq_status[2];
     * on 3620/3640 platforms. Added due to a packet loss when using an  
     * Ethernet NM on these platforms.  
     *  
     * Anyway, we should rely on the device information with appropriate IRQ  
     * routing.  
     */  
    int net_irq_clearing_count;  
78    
79     /* Interrupt mask */     /* Interrupt mask */
80     m_uint16_t intr_mask,io_mask2;     m_uint16_t intr_mask,io_mask2;
# Line 78  struct iofpga_data { Line 84  struct iofpga_data {
84  };  };
85    
86  /* Motherboard EEPROM definition */  /* Motherboard EEPROM definition */
87  static const struct nmc93c46_eeprom_def eeprom_mb_def = {  static const struct nmc93cX6_eeprom_def eeprom_mb_def = {
88     EEPROM_MB_CLK, EEPROM_MB_CS,     EEPROM_MB_CLK, EEPROM_MB_CS,
89     EEPROM_MB_DIN, EEPROM_MB_DOUT,     EEPROM_MB_DIN, EEPROM_MB_DOUT,
90  };  };
91    
92  /* I/O board EEPROM definition */  /* I/O board EEPROM definition */
93  static const struct nmc93c46_eeprom_def eeprom_io_def = {  static const struct nmc93cX6_eeprom_def eeprom_io_def = {
94     EEPROM_IO_CLK, EEPROM_IO_CS,     EEPROM_IO_CLK, EEPROM_IO_CS,
95     EEPROM_IO_DIN, EEPROM_IO_DOUT,     EEPROM_IO_DIN, EEPROM_IO_DOUT,
96  };  };
97    
98  /* Midplane EEPROM definition */  /* Midplane EEPROM definition */
99  static const struct nmc93c46_eeprom_def eeprom_mp_def = {  static const struct nmc93cX6_eeprom_def eeprom_mp_def = {
100     EEPROM_MP_CLK, EEPROM_MP_CS,     EEPROM_MP_CLK, EEPROM_MP_CS,
101     EEPROM_MP_DIN, EEPROM_MP_DOUT,     EEPROM_MP_DIN, EEPROM_MP_DOUT,
102  };  };
103    
104  /* System EEPROM group */  /* System EEPROM group */
105  static const struct nmc93c46_group eeprom_sys_group = {  static const struct nmc93cX6_group eeprom_sys_group = {
106     3, 0, "System EEPROM", 0,     EEPROM_TYPE_NMC93C46, 3, 0, "System EEPROM", 0,
107     { &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def },     { &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def },
108  };  };
109    
110  /* NM EEPROM definition */  /* NM EEPROM definition */
111  static const struct nmc93c46_eeprom_def eeprom_nm_def = {  static const struct nmc93cX6_eeprom_def eeprom_nm_def = {
112     EEPROM_NM_CLK, EEPROM_NM_CS,     EEPROM_NM_CLK, EEPROM_NM_CS,
113     EEPROM_NM_DIN, EEPROM_NM_DOUT,     EEPROM_NM_DIN, EEPROM_NM_DOUT,
114  };  };
115    
116  /* NM EEPROM */  /* NM EEPROM */
117  static const struct nmc93c46_group eeprom_nm_group = {  static const struct nmc93cX6_group eeprom_nm_group = {
118     1, 0, "NM EEPROM", 0, { &eeprom_nm_def },     EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def },
119  };  };
120    
121    /* Update network interrupt status */
122    static inline void dev_c3745_iofpga_net_update_irq(struct c3745_iofpga_data *d)
123    {
124       if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) {
125          vm_set_irq(d->router->vm,C3745_NETIO_IRQ);
126       } else {
127          vm_clear_irq(d->router->vm,C3745_NETIO_IRQ);
128       }
129    }
130    
131    /* Trigger a Network IRQ for the specified slot/port */
132    void dev_c3745_iofpga_net_set_irq(struct c3745_iofpga_data *d,
133                                      u_int slot,u_int port)
134    {
135       struct net_irq_distrib *irq_dist;
136    
137    #if DEBUG_NET_IRQ
138       vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n",
139              slot,port);
140    #endif
141       irq_dist = &net_irq_dist[slot];
142       d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port));
143       dev_c3745_iofpga_net_update_irq(d);
144    }
145    
146    /* Clear a Network IRQ for the specified slot/port */
147    void dev_c3745_iofpga_net_clear_irq(struct c3745_iofpga_data *d,
148                                        u_int slot,u_int port)
149    {
150       struct net_irq_distrib *irq_dist;
151    
152    #if DEBUG_NET_IRQ
153       vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n",
154              slot,port);
155    #endif
156       irq_dist = &net_irq_dist[slot];
157       d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port));
158       dev_c3745_iofpga_net_update_irq(d);
159    }
160    
161  /*  /*
162   * dev_c3745_iofpga_access()   * dev_c3745_iofpga_access()
163   */   */
# Line 120  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 166  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
166                          m_uint32_t offset,u_int op_size,u_int op_type,                          m_uint32_t offset,u_int op_size,u_int op_type,
167                          m_uint64_t *data)                          m_uint64_t *data)
168  {  {
169     struct iofpga_data *d = dev->priv_data;     struct c3745_iofpga_data *d = dev->priv_data;
170     u_int slot;     u_int slot;
171    
172     if (op_type == MTS_READ)     if (op_type == MTS_READ)
# Line 191  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 237  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
237        /* System EEPROMs */        /* System EEPROMs */
238        case 0x00000e:        case 0x00000e:
239           if (op_type == MTS_WRITE)           if (op_type == MTS_WRITE)
240              nmc93c46_write(&d->router->sys_eeprom_group,(u_int)(*data));              nmc93cX6_write(&d->router->sys_eeprom_group,(u_int)(*data));
241           else           else
242              *data = nmc93c46_read(&d->router->sys_eeprom_group);              *data = nmc93cX6_read(&d->router->sys_eeprom_group);
243           break;           break;
244    
245        /*        /*
# Line 205  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 251  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
251         */         */
252        case 0x000020:        case 0x000020:
253           if (op_type == MTS_READ)           if (op_type == MTS_READ)
254              *data = 0xFFFE;              *data = d->net_irq_status[0];
255           break;           break;
256    
257        /*        /*
# Line 218  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 264  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
264         */         */
265        case 0x000022:        case 0x000022:
266           if (op_type == MTS_READ)           if (op_type == MTS_READ)
267              *data = 0x0000;              *data = d->net_irq_status[1];
          vm_clear_irq(d->router->vm,C3745_NETIO_IRQ);  
268           break;           break;
269    
270        /*        /*
# Line 249  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 294  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
294           slot = (offset - 0x000040) >> 1;           slot = (offset - 0x000040) >> 1;
295    
296           if (op_type == MTS_WRITE)           if (op_type == MTS_WRITE)
297              nmc93c46_write(&d->router->nm_eeprom_group[slot],(u_int)(*data));              nmc93cX6_write(&d->router->nm_eeprom_group[slot],(u_int)(*data));
298           else           else
299              *data = nmc93c46_read(&d->router->nm_eeprom_group[slot]);              *data = nmc93cX6_read(&d->router->nm_eeprom_group[slot]);
300           break;           break;
301    
302        /* AIM slot 0 EEPROM */        /* AIM slot 0 EEPROM */
# Line 340  void c3745_init_eeprom_groups(c3745_t *r Line 385  void c3745_init_eeprom_groups(c3745_t *r
385  }  }
386    
387  /* Shutdown the IO FPGA device */  /* Shutdown the IO FPGA device */
388  void dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)  static void
389    dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct c3745_iofpga_data *d)
390  {  {
391     if (d != NULL) {     if (d != NULL) {
392        /* Remove the device */        /* Remove the device */
# Line 357  void dev_c3745_iofpga_shutdown(vm_instan Line 403  void dev_c3745_iofpga_shutdown(vm_instan
403  int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len)  int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len)
404  {  {
405     vm_instance_t *vm = router->vm;     vm_instance_t *vm = router->vm;
406     struct iofpga_data *d;     struct c3745_iofpga_data *d;
407    
408     /* Allocate private data structure */     /* Allocate private data structure */
409     if (!(d = malloc(sizeof(*d)))) {     if (!(d = malloc(sizeof(*d)))) {
# Line 367  int dev_c3745_iofpga_init(c3745_t *route Line 413  int dev_c3745_iofpga_init(c3745_t *route
413    
414     memset(d,0,sizeof(*d));     memset(d,0,sizeof(*d));
415     d->router = router;     d->router = router;
416       d->net_irq_status[0] = 0xFFFF;
417       d->net_irq_status[1] = 0xFFFF;
418    
419     vm_object_init(&d->vm_obj);     vm_object_init(&d->vm_obj);
420     d->vm_obj.name = "io_fpga";     d->vm_obj.name = "io_fpga";

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