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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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#include "cpu.h" |
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#include "vm.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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dpavlin |
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#include "nmc93cX6.h" |
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dpavlin |
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#include "dev_c2600.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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dpavlin |
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#define DEBUG_NET_IRQ 0 |
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dpavlin |
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/* Definitions for Mainboard EEPROM */ |
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#define EEPROM_MB_DOUT 3 |
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#define EEPROM_MB_DIN 2 |
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#define EEPROM_MB_CLK 1 |
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#define EEPROM_MB_CS 0 |
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/* Definitions for Network Modules EEPROM */ |
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#define EEPROM_NM_DOUT 7 |
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#define EEPROM_NM_DIN 6 |
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#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
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#define C2691_NET_IRQ_CLEARING_DELAY 16 |
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dpavlin |
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/* Network IRQ distribution */ |
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static u_int net_irq_dist[C2600_MAX_NM_BAYS] = { |
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4, /* reg 0x08, bits 4-5 */ |
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0, /* reg 0x08, bits 0-3 */ |
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}; |
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dpavlin |
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/* IO FPGA structure */ |
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dpavlin |
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struct c2600_iofpga_data { |
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dpavlin |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c2600_t *router; |
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dpavlin |
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/* Network Interrupt status */ |
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m_uint8_t net_irq_status; |
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dpavlin |
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dpavlin |
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/* Interrupt mask */ |
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dpavlin |
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m_uint16_t intr_mask; |
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}; |
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/* Mainboard EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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dpavlin |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
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/* Mainboard EEPROM */ |
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dpavlin |
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static const struct nmc93cX6_group eeprom_mb_group = { |
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EEPROM_TYPE_NMC93C46, 1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
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dpavlin |
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}; |
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/* NM EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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dpavlin |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
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/* NM EEPROM */ |
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dpavlin |
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static const struct nmc93cX6_group eeprom_nm_group = { |
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EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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dpavlin |
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}; |
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dpavlin |
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/* Update network interrupt status */ |
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static inline void dev_c2600_iofpga_net_update_irq(struct c2600_iofpga_data *d) |
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{ |
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if (d->net_irq_status) { |
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vm_set_irq(d->router->vm,C2600_NETIO_IRQ); |
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} else { |
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vm_clear_irq(d->router->vm,C2600_NETIO_IRQ); |
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} |
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} |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c2600_iofpga_net_set_irq(struct c2600_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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d->net_irq_status |= 1 << (net_irq_dist[slot] + port); |
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dev_c2600_iofpga_net_update_irq(d); |
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} |
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/* Clear a Network IRQ for the specified slot/port */ |
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void dev_c2600_iofpga_net_clear_irq(struct c2600_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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d->net_irq_status &= ~(1 << (net_irq_dist[slot] + port)); |
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dev_c2600_iofpga_net_update_irq(d); |
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} |
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dpavlin |
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/* |
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* dev_c2600_iofpga_access() |
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*/ |
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static void * |
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dev_c2600_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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dpavlin |
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struct c2600_iofpga_data *d = dev->priv_data; |
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dpavlin |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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} |
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#endif |
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switch(offset) { |
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case 0x04: |
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if (op_type == MTS_READ) |
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*data = 0x00; |
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break; |
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/* |
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* Network Interrupt. |
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* |
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dpavlin |
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* Bit 0-3: slot 1. |
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dpavlin |
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* Bit 4: slot 0 (MB), port 0 |
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* Bit 5: slot 0 (MB), port 1 |
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* Other: AIM ? (error messages displayed) |
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*/ |
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case 0x08: |
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if (op_type == MTS_READ) |
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dpavlin |
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*data = d->net_irq_status; |
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dpavlin |
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break; |
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case 0x10: |
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case 0x14: |
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if (op_type == MTS_READ) |
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*data = 0xFFFFFFFF; |
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break; |
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dpavlin |
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/* |
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* Flash Related: 0x1y |
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* |
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* Bit 1: card present in slot 0 / WIC 0. |
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* Bit 2: card present in slot 0 / WIC 1. |
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* |
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* Other bits unknown. |
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*/ |
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dpavlin |
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#if 1 |
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case 0x0c: |
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if (op_type == MTS_READ) |
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dpavlin |
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*data = 0x10; //0x10; |
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dpavlin |
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break; |
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#endif |
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/* NM EEPROM */ |
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case 0x1c: |
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if (op_type == MTS_WRITE) |
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dpavlin |
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nmc93cX6_write(&d->router->nm_eeprom_group,(u_int)(*data)); |
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dpavlin |
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else |
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dpavlin |
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*data = nmc93cX6_read(&d->router->nm_eeprom_group); |
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dpavlin |
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break; |
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#if DEBUG_UNKNOWN |
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default: |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA", |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"write to unknown addr 0x%x, value=0x%llx, " |
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"pc=0x%llx (size=%u)\n", |
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offset,*data,cpu_get_pc(cpu),op_size); |
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} |
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#endif |
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} |
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return NULL; |
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} |
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/* Initialize EEPROM groups */ |
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void c2600_init_eeprom_groups(c2600_t *router) |
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{ |
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/* Initialize Mainboard EEPROM */ |
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router->mb_eeprom_group = eeprom_mb_group; |
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router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom; |
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router->mb_eeprom.data = NULL; |
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router->mb_eeprom.len = 0; |
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/* EEPROM for NM slot 1 */ |
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router->nm_eeprom_group = eeprom_nm_group; |
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router->nm_eeprom_group.eeprom[0] = &router->nm_bay[1].eeprom; |
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} |
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/* Shutdown the IO FPGA device */ |
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dpavlin |
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static void |
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dev_c2600_iofpga_shutdown(vm_instance_t *vm,struct c2600_iofpga_data *d) |
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dpavlin |
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{ |
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if (d != NULL) { |
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/* Remove the device */ |
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dev_remove(vm,&d->dev); |
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/* Free the structure itself */ |
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free(d); |
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} |
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} |
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/* |
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* dev_c2600_iofpga_init() |
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*/ |
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int dev_c2600_iofpga_init(c2600_t *router,m_uint64_t paddr,m_uint32_t len) |
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{ |
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vm_instance_t *vm = router->vm; |
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dpavlin |
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struct c2600_iofpga_data *d; |
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dpavlin |
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/* Allocate private data structure */ |
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if (!(d = malloc(sizeof(*d)))) { |
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fprintf(stderr,"IO_FPGA: out of memory\n"); |
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return(-1); |
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} |
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memset(d,0,sizeof(*d)); |
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d->router = router; |
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vm_object_init(&d->vm_obj); |
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d->vm_obj.name = "io_fpga"; |
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d->vm_obj.data = d; |
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d->vm_obj.shutdown = (vm_shutdown_t)dev_c2600_iofpga_shutdown; |
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/* Set device properties */ |
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dev_init(&d->dev); |
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d->dev.name = "io_fpga"; |
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d->dev.phys_addr = paddr; |
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d->dev.phys_len = len; |
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d->dev.priv_data = d; |
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d->dev.handler = dev_c2600_iofpga_access; |
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/* Map this device to the VM */ |
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vm_bind_device(router->vm,&d->dev); |
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vm_object_add(vm,&d->vm_obj); |
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return(0); |
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} |