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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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* |
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* Just an empty JIT template file for architectures not supported by the JIT |
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* code. |
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*/ |
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|
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#ifndef __MIPS64_NOJIT_TRANS_H__ |
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#define __MIPS64_NOJIT_TRANS_H__ |
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|
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#include "utils.h" |
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#include "cpu.h" |
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#include "dynamips.h" |
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|
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#define JIT_SUPPORT 0 |
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|
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#define mips64_jit_tcb_set_patch(a,b) |
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#define mips64_jit_tcb_set_jump(a,b) |
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|
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/* MIPS instruction array */ |
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extern struct mips64_insn_tag mips64_insn_tags[]; |
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|
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/* Push epilog for an x86 instruction block */ |
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void mips64_jit_tcb_push_epilog(mips64_jit_tcb_t *block); |
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|
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/* Execute JIT code */ |
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void mips64_jit_tcb_exec(cpu_mips_t *cpu,mips64_jit_tcb_t *block); |
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|
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/* Set the Pointer Counter (PC) register */ |
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void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc); |
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|
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/* Set the Return Address (RA) register */ |
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void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc); |
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|
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/* Virtual Breakpoint */ |
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void mips64_emit_breakpoint(mips64_jit_tcb_t *b); |
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|
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/* Emit unhandled instruction code */ |
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void mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b); |
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|
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/* |
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* Increment count register and trigger the timer IRQ if value in compare |
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* register is the same. |
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*/ |
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void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b); |
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|
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/* Increment the number of executed instructions (performance debugging) */ |
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void mips64_inc_perf_counter(mips64_jit_tcb_t *b); |
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|
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#endif |