1 |
/* |
/* |
2 |
* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
4 |
* |
* |
5 |
* MIPS64 Step-by-step execution. |
* MIPS64 Step-by-step execution. |
16 |
#include <sys/mman.h> |
#include <sys/mman.h> |
17 |
#include <fcntl.h> |
#include <fcntl.h> |
18 |
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#include "rbtree.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "vm.h" |
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#include "memory.h" |
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19 |
#include "cpu.h" |
#include "cpu.h" |
20 |
#include "cp0.h" |
#include "vm.h" |
21 |
#include "mips64_exec.h" |
#include "mips64_exec.h" |
22 |
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#include "memory.h" |
23 |
#include "insn_lookup.h" |
#include "insn_lookup.h" |
24 |
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#include "dynamips.h" |
25 |
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26 |
/* Forward declaration of instruction array */ |
/* Forward declaration of instruction array */ |
27 |
static struct insn_exec_tag mips64_exec_tags[]; |
static struct mips64_insn_exec_tag mips64_exec_tags[]; |
28 |
static insn_lookup_t *ilt = NULL; |
static insn_lookup_t *ilt = NULL; |
29 |
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|
30 |
/* ILT */ |
/* ILT */ |
33 |
return(&mips64_exec_tags[index]); |
return(&mips64_exec_tags[index]); |
34 |
} |
} |
35 |
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36 |
static int mips64_exec_chk_lo(struct insn_exec_tag *tag,int value) |
static int mips64_exec_chk_lo(struct mips64_insn_exec_tag *tag,int value) |
37 |
{ |
{ |
38 |
return((value & tag->mask) == (tag->value & 0xFFFF)); |
return((value & tag->mask) == (tag->value & 0xFFFF)); |
39 |
} |
} |
40 |
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|
41 |
static int mips64_exec_chk_hi(struct insn_exec_tag *tag,int value) |
static int mips64_exec_chk_hi(struct mips64_insn_exec_tag *tag,int value) |
42 |
{ |
{ |
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return((value & (tag->mask >> 16)) == (tag->value >> 16)); |
return((value & (tag->mask >> 16)) == (tag->value >> 16)); |
44 |
} |
} |
51 |
for(i=0,count=0;mips64_exec_tags[i].exec;i++) |
for(i=0,count=0;mips64_exec_tags[i].exec;i++) |
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count++; |
count++; |
53 |
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|
54 |
ilt = ilt_create(count, |
ilt = ilt_create(count+1, |
55 |
(ilt_get_insn_cbk_t)mips64_exec_get_insn, |
(ilt_get_insn_cbk_t)mips64_exec_get_insn, |
56 |
(ilt_check_cbk_t)mips64_exec_chk_lo, |
(ilt_check_cbk_t)mips64_exec_chk_lo, |
57 |
(ilt_check_cbk_t)mips64_exec_chk_hi); |
(ilt_check_cbk_t)mips64_exec_chk_hi); |
81 |
{ |
{ |
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char insn_name[64],insn_format[32],*name; |
char insn_name[64],insn_format[32],*name; |
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int base,rs,rd,rt,sa,offset,imm; |
int base,rs,rd,rt,sa,offset,imm; |
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struct insn_exec_tag *tag; |
struct mips64_insn_exec_tag *tag; |
85 |
m_uint64_t new_pc; |
m_uint64_t new_pc; |
86 |
int index; |
int index; |
87 |
|
|
327 |
mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction) |
mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction) |
328 |
{ |
{ |
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register fastcall int (*exec)(cpu_mips_t *,mips_insn_t) = NULL; |
register fastcall int (*exec)(cpu_mips_t *,mips_insn_t) = NULL; |
330 |
struct insn_exec_tag *tag; |
struct mips64_insn_exec_tag *tag; |
331 |
int index; |
int index; |
332 |
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333 |
#if DEBUG_PERF_COUNTER |
#if DEBUG_INSN_PERF_CNT |
334 |
cpu->perf_counter++; |
cpu->perf_counter++; |
335 |
#endif |
#endif |
336 |
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361 |
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362 |
printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n", |
printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n", |
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instruction,cpu->pc); |
instruction,cpu->pc); |
364 |
mips64_dump_regs(cpu); |
mips64_dump_regs(cpu->gen); |
365 |
return(0); |
return(0); |
366 |
} |
} |
367 |
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|
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/* Single-step execution */ |
/* Single-step execution */ |
369 |
void mips64_exec_single_step(cpu_mips_t *cpu,mips_insn_t instruction) |
fastcall void mips64_exec_single_step(cpu_mips_t *cpu,mips_insn_t instruction) |
370 |
{ |
{ |
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int res; |
int res; |
372 |
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377 |
} |
} |
378 |
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/* Run MIPS code in step-by-step mode */ |
/* Run MIPS code in step-by-step mode */ |
380 |
void *mips64_exec_run_cpu(cpu_mips_t *cpu) |
void *mips64_exec_run_cpu(cpu_gen_t *gen) |
381 |
{ |
{ |
382 |
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cpu_mips_t *cpu = CPU_MIPS64(gen); |
383 |
pthread_t timer_irq_thread; |
pthread_t timer_irq_thread; |
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mips_insn_t insn; |
|
384 |
int timer_irq_check = 0; |
int timer_irq_check = 0; |
385 |
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mips_insn_t insn; |
386 |
int res; |
int res; |
387 |
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388 |
if (pthread_create(&timer_irq_thread,NULL, |
if (pthread_create(&timer_irq_thread,NULL, |
389 |
(void *)mips64_timer_irq_run,cpu)) |
(void *)mips64_timer_irq_run,cpu)) |
390 |
{ |
{ |
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fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n", |
fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n", |
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cpu->vm->name,cpu->id); |
cpu->vm->name,gen->id); |
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cpu_stop(cpu); |
cpu_stop(gen); |
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return NULL; |
return NULL; |
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} |
} |
396 |
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cpu->cpu_thread_running = TRUE; |
gen->cpu_thread_running = TRUE; |
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start_cpu: |
start_cpu: |
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cpu->idle_count = 0; |
gen->idle_count = 0; |
401 |
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for(;;) { |
for(;;) { |
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if (unlikely(cpu->state != MIPS_CPU_RUNNING)) |
if (unlikely(gen->state != CPU_STATE_RUNNING)) |
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break; |
break; |
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|
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/* Handle virtual idle loop */ |
/* Handle virtual idle loop */ |
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if (unlikely(cpu->pc == cpu->idle_pc)) { |
if (unlikely(cpu->pc == cpu->idle_pc)) { |
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if (++cpu->idle_count == cpu->idle_max) { |
if (++gen->idle_count == gen->idle_max) { |
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mips64_idle_loop(cpu); |
cpu_idle_loop(gen); |
410 |
cpu->idle_count = 0; |
gen->idle_count = 0; |
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} |
} |
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} |
} |
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res = mips64_exec_single_instruction(cpu,insn); |
res = mips64_exec_single_instruction(cpu,insn); |
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/* Normal flow ? */ |
/* Normal flow ? */ |
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if (likely(!res)) cpu->pc += 4; |
if (likely(!res)) cpu->pc += sizeof(mips_insn_t); |
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} |
} |
441 |
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|
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if (!cpu->pc) { |
if (!cpu->pc) { |
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cpu_stop(cpu); |
cpu_stop(gen); |
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cpu_log(cpu,"SLOW_EXEC","PC=0, halting CPU.\n"); |
cpu_log(gen,"SLOW_EXEC","PC=0, halting CPU.\n"); |
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} |
} |
446 |
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/* Check regularly if the CPU has been restarted */ |
/* Check regularly if the CPU has been restarted */ |
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while(cpu->cpu_thread_running) { |
while(gen->cpu_thread_running) { |
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cpu->seq_state++; |
gen->seq_state++; |
450 |
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|
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switch(cpu->state) { |
switch(gen->state) { |
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case MIPS_CPU_RUNNING: |
case CPU_STATE_RUNNING: |
453 |
cpu->state = MIPS_CPU_RUNNING; |
gen->state = CPU_STATE_RUNNING; |
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goto start_cpu; |
goto start_cpu; |
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case MIPS_CPU_HALTED: |
case CPU_STATE_HALTED: |
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cpu->cpu_thread_running = FALSE; |
gen->cpu_thread_running = FALSE; |
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pthread_join(timer_irq_thread,NULL); |
pthread_join(timer_irq_thread,NULL); |
459 |
break; |
break; |
460 |
} |
} |
1084 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1085 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1086 |
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1087 |
cp0_exec_cfc0(cpu,rt,rd); |
mips64_cp0_exec_cfc0(cpu,rt,rd); |
1088 |
return(0); |
return(0); |
1089 |
} |
} |
1090 |
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|
1094 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1095 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1096 |
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1097 |
cp0_exec_ctc0(cpu,rt,rd); |
mips64_cp0_exec_ctc0(cpu,rt,rd); |
1098 |
return(0); |
return(0); |
1099 |
} |
} |
1100 |
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1158 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1159 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1160 |
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1161 |
cp0_exec_dmfc0(cpu,rt,rd); |
mips64_cp0_exec_dmfc0(cpu,rt,rd); |
1162 |
return(0); |
return(0); |
1163 |
} |
} |
1164 |
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1178 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1179 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1180 |
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1181 |
cp0_exec_dmtc0(cpu,rt,rd); |
mips64_cp0_exec_dmtc0(cpu,rt,rd); |
1182 |
return(0); |
return(0); |
1183 |
} |
} |
1184 |
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1542 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1543 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1544 |
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1545 |
cp0_exec_mfc0(cpu,rt,rd); |
mips64_cp0_exec_mfc0(cpu,rt,rd); |
1546 |
return(0); |
return(0); |
1547 |
} |
} |
1548 |
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1590 |
int rt = bits(insn,16,20); |
int rt = bits(insn,16,20); |
1591 |
int rd = bits(insn,11,15); |
int rd = bits(insn,11,15); |
1592 |
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1593 |
cp0_exec_mtc0(cpu,rt,rd); |
mips64_cp0_exec_mtc0(cpu,rt,rd); |
1594 |
return(0); |
return(0); |
1595 |
} |
} |
1596 |
|
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2028 |
/* TLBP */ |
/* TLBP */ |
2029 |
static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn) |
static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn) |
2030 |
{ |
{ |
2031 |
cp0_exec_tlbp(cpu); |
mips64_cp0_exec_tlbp(cpu); |
2032 |
return(0); |
return(0); |
2033 |
} |
} |
2034 |
|
|
2035 |
/* TLBR */ |
/* TLBR */ |
2036 |
static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn) |
static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn) |
2037 |
{ |
{ |
2038 |
cp0_exec_tlbr(cpu); |
mips64_cp0_exec_tlbr(cpu); |
2039 |
return(0); |
return(0); |
2040 |
} |
} |
2041 |
|
|
2042 |
/* TLBWI */ |
/* TLBWI */ |
2043 |
static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn) |
static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn) |
2044 |
{ |
{ |
2045 |
cp0_exec_tlbwi(cpu); |
mips64_cp0_exec_tlbwi(cpu); |
2046 |
return(0); |
return(0); |
2047 |
} |
} |
2048 |
|
|
2049 |
/* TLBWR */ |
/* TLBWR */ |
2050 |
static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn) |
static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn) |
2051 |
{ |
{ |
2052 |
cp0_exec_tlbwr(cpu); |
mips64_cp0_exec_tlbwr(cpu); |
2053 |
return(0); |
return(0); |
2054 |
} |
} |
2055 |
|
|
2076 |
} |
} |
2077 |
|
|
2078 |
/* MIPS instruction array */ |
/* MIPS instruction array */ |
2079 |
static struct insn_exec_tag mips64_exec_tags[] = { |
static struct mips64_insn_exec_tag mips64_exec_tags[] = { |
2080 |
{ "li" , mips64_exec_LI , 0xffe00000 , 0x24000000, 1, 16 }, |
{ "li" , mips64_exec_LI , 0xffe00000 , 0x24000000, 1, 16 }, |
2081 |
{ "move" , mips64_exec_MOVE , 0xfc1f07ff , 0x00000021, 1, 15 }, |
{ "move" , mips64_exec_MOVE , 0xfc1f07ff , 0x00000021, 1, 15 }, |
2082 |
{ "b" , mips64_exec_B , 0xffff0000 , 0x10000000, 0, 10 }, |
{ "b" , mips64_exec_B , 0xffff0000 , 0x10000000, 0, 10 }, |