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dpavlin |
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/* |
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dpavlin |
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* Cisco router simulation platform. |
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dpavlin |
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* Copyright (c) 2005 Christophe Fillot (cf@utc.fr) |
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* |
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* SB-1 I/O devices. |
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* |
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* XXX: just for tests! |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "utils.h" |
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#include "ptask.h" |
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dpavlin |
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#include "cpu.h" |
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#include "vm.h" |
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dpavlin |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_c7200.h" |
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#define DEBUG_UNKNOWN 1 |
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/* DUART Status Register */ |
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#define DUART_SR_RX_RDY 0x01 /* Receiver ready */ |
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#define DUART_SR_RX_FFUL 0x02 /* Receive FIFO full */ |
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#define DUART_SR_TX_RDY 0x04 /* Transmitter ready */ |
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#define DUART_SR_TX_EMT 0x08 /* Transmitter empty */ |
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/* DUART Interrupt Status Register */ |
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#define DUART_ISR_TXA 0x01 /* Channel A Transmitter Ready */ |
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#define DUART_ISR_RXA 0x02 /* Channel A Receiver Ready */ |
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#define DUART_ISR_TXB 0x10 /* Channel B Transmitter Ready */ |
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#define DUART_ISR_RXB 0x20 /* Channel B Receiver Ready */ |
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/* DUART Interrupt Mask Register */ |
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#define DUART_IMR_TXA 0x01 /* Channel A Transmitter Ready */ |
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#define DUART_IMR_RXA 0x02 /* Channel A Receiver Ready */ |
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#define DUART_IMR_TXB 0x10 /* Channel B Transmitter Ready */ |
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#define DUART_IMR_RXB 0x20 /* Channel B Receiver Ready */ |
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/* SB-1 DUART channel */ |
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struct sb1_duart_channel { |
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m_uint8_t mode; |
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m_uint8_t cmd; |
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}; |
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/* SB-1 I/O private data */ |
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struct sb1_io_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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/* Virtual machine */ |
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vm_instance_t *vm; |
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/* DUART info */ |
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u_int duart_irq,duart_irq_seq; |
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m_uint8_t duart_isr,duart_imr; |
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struct sb1_duart_channel duart_chan[2]; |
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/* Periodic task to trigger dummy DUART IRQ */ |
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ptask_id_t duart_irq_tid; |
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}; |
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/* Console port input */ |
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static void tty_con_input(vtty_t *vtty) |
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{ |
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struct sb1_io_data *d = vtty->priv_data; |
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if (d->duart_imr & DUART_IMR_RXA) { |
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d->duart_isr |= DUART_ISR_RXA; |
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vm_set_irq(d->vm,d->duart_irq); |
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} |
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} |
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/* AUX port input */ |
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static void tty_aux_input(vtty_t *vtty) |
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{ |
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struct sb1_io_data *d = vtty->priv_data; |
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if (d->duart_imr & DUART_IMR_RXB) { |
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d->duart_isr |= DUART_ISR_RXB; |
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vm_set_irq(d->vm,d->duart_irq); |
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} |
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} |
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/* IRQ trickery for Console and AUX ports */ |
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static int tty_trigger_dummy_irq(struct sb1_io_data *d,void *arg) |
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{ |
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u_int mask; |
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d->duart_irq_seq++; |
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if (d->duart_irq_seq == 2) { |
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mask = DUART_IMR_TXA|DUART_IMR_TXB; |
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if (d->duart_imr & mask) { |
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d->duart_isr |= DUART_ISR_TXA|DUART_ISR_TXB; |
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vm_set_irq(d->vm,d->duart_irq); |
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} |
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d->duart_irq_seq = 0; |
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} |
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return(0); |
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} |
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/* |
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* dev_sb1_io_access() |
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*/ |
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dpavlin |
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void *dev_sb1_io_access(cpu_gen_t *cpu,struct vdevice *dev, |
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dpavlin |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct sb1_io_data *d = dev->priv_data; |
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u_char odata; |
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if (op_type == MTS_READ) |
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*data = 0; |
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switch(offset) { |
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case 0x390: /* DUART Interrupt Status Register */ |
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if (op_type == MTS_READ) |
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*data = d->duart_isr; |
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break; |
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case 0x320: /* DUART Channel A Only Interrupt Status Register */ |
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if (op_type == MTS_READ) |
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*data = d->duart_isr & 0x0F; |
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break; |
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case 0x340: /* DUART Channel B Only Interrupt Status Register */ |
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if (op_type == MTS_READ) |
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*data = (d->duart_isr >> 4) & 0x0F; |
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break; |
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case 0x3a0: /* DUART Interrupt Mask Register */ |
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if (op_type == MTS_READ) |
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*data = d->duart_imr; |
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else |
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d->duart_imr = *data; |
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break; |
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case 0x330: /* DUART Channel A Only Interrupt Mask Register */ |
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if (op_type == MTS_READ) { |
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*data = d->duart_imr & 0x0F; |
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} else { |
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d->duart_imr &= ~0x0F; |
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d->duart_imr |= *data & 0x0F; |
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} |
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break; |
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case 0x350: /* DUART Channel B Only Interrupt Mask Register */ |
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if (op_type == MTS_READ) { |
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*data = (d->duart_imr >> 4) & 0x0F; |
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} else { |
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d->duart_imr &= ~0xF0; |
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d->duart_imr |= (*data & 0x0F) << 4; |
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} |
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break; |
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case 0x100: /* DUART Mode (Channel A) */ |
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if (op_type == MTS_READ) |
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d->duart_chan[0].mode = *data; |
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else |
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*data = d->duart_chan[0].mode; |
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break; |
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case 0x200: /* DUART Mode (Channel B) */ |
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if (op_type == MTS_READ) |
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d->duart_chan[1].mode = *data; |
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else |
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*data = d->duart_chan[1].mode; |
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break; |
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case 0x150: /* DUART Command Register (Channel A) */ |
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if (op_type == MTS_READ) |
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d->duart_chan[0].cmd = *data; |
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else |
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*data = d->duart_chan[0].cmd; |
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break; |
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case 0x250: /* DUART Command Register (Channel B) */ |
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if (op_type == MTS_READ) |
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d->duart_chan[1].cmd = *data; |
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else |
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*data = d->duart_chan[1].cmd; |
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break; |
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case 0x120: /* DUART Status Register (Channel A) */ |
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if (op_type == MTS_READ) { |
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odata = 0; |
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if (vtty_is_char_avail(d->vm->vtty_con)) |
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odata |= DUART_SR_RX_RDY; |
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odata |= DUART_SR_TX_RDY; |
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vm_clear_irq(d->vm,d->duart_irq); |
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*data = odata; |
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} |
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break; |
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case 0x220: /* DUART Status Register (Channel B) */ |
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if (op_type == MTS_READ) { |
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odata = 0; |
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if (vtty_is_char_avail(d->vm->vtty_aux)) |
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odata |= DUART_SR_RX_RDY; |
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odata |= DUART_SR_TX_RDY; |
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//vm_clear_irq(d->vm,d->duart_irq); |
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*data = odata; |
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} |
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break; |
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case 0x160: /* DUART Received Data Register (Channel A) */ |
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if (op_type == MTS_READ) { |
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*data = vtty_get_char(d->vm->vtty_con); |
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d->duart_isr &= ~DUART_ISR_RXA; |
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} |
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break; |
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case 0x260: /* DUART Received Data Register (Channel B) */ |
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if (op_type == MTS_READ) { |
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*data = vtty_get_char(d->vm->vtty_aux); |
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d->duart_isr &= ~DUART_ISR_RXB; |
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} |
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break; |
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case 0x170: /* DUART Transmit Data Register (Channel A) */ |
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if (op_type == MTS_WRITE) { |
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vtty_put_char(d->vm->vtty_con,(char)*data); |
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d->duart_isr &= ~DUART_ISR_TXA; |
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} |
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break; |
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case 0x270: /* DUART Transmit Data Register (Channel B) */ |
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if (op_type == MTS_WRITE) { |
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vtty_put_char(d->vm->vtty_aux,(char)*data); |
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d->duart_isr &= ~DUART_ISR_TXB; |
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} |
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break; |
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case 0x1a76: /* pcmcia status */ |
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if (op_type == MTS_READ) |
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*data = 0xFF; |
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break; |
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#if DEBUG_UNKNOWN |
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default: |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"SB1_IO","read from addr 0x%x, pc=0x%llx\n", |
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dpavlin |
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offset,cpu_get_pc(cpu)); |
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dpavlin |
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} else { |
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cpu_log(cpu,"SB1_IO","write to addr 0x%x, value=0x%llx, " |
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dpavlin |
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"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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dpavlin |
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} |
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#endif |
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} |
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return NULL; |
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} |
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/* Shutdown the SB-1 I/O devices */ |
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void dev_sb1_io_shutdown(vm_instance_t *vm,struct sb1_io_data *d) |
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{ |
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if (d != NULL) { |
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/* Remove the device */ |
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dev_remove(vm,&d->dev); |
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/* Free the structure itself */ |
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free(d); |
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} |
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} |
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/* Create SB-1 I/O devices */ |
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int dev_sb1_io_init(vm_instance_t *vm,u_int duart_irq) |
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{ |
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struct sb1_io_data *d; |
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/* allocate private data structure */ |
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if (!(d = malloc(sizeof(*d)))) { |
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fprintf(stderr,"SB1_IO: out of memory\n"); |
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return(-1); |
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} |
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memset(d,0,sizeof(*d)); |
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d->vm = vm; |
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d->duart_irq = duart_irq; |
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vm_object_init(&d->vm_obj); |
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d->vm_obj.name = "sb1_io"; |
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d->vm_obj.data = d; |
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d->vm_obj.shutdown = (vm_shutdown_t)dev_sb1_io_shutdown; |
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/* Set device properties */ |
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dev_init(&d->dev); |
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d->dev.name = "sb1_io"; |
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d->dev.priv_data = d; |
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d->dev.phys_addr = 0x10060000ULL; |
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d->dev.phys_len = 0x10000; |
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d->dev.handler = dev_sb1_io_access; |
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/* Set console and AUX port notifying functions */ |
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vm->vtty_con->priv_data = d; |
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vm->vtty_aux->priv_data = d; |
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vm->vtty_con->read_notifier = tty_con_input; |
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vm->vtty_aux->read_notifier = tty_aux_input; |
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/* Trigger periodically a dummy IRQ to flush buffers */ |
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d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,d,NULL); |
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/* Map this device to the VM */ |
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vm_bind_device(vm,&d->dev); |
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vm_object_add(vm,&d->vm_obj); |
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return(0); |
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} |