/[dynamips]/upstream/dynamips-0.2.7-RC1/dev_plx.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_plx.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_plx.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PLX PCI9060/PCI9054 - PCI bus master interface chip.   * PLX PCI9060/PCI9054 - PCI bus master interface chip.
# Line 12  Line 12 
12  #include <stdlib.h>  #include <stdlib.h>
13  #include <string.h>  #include <string.h>
14    
15  #include "mips64.h"  #include "cpu.h"
16    #include "vm.h"
17  #include "dynamips.h"  #include "dynamips.h"
18  #include "memory.h"  #include "memory.h"
19  #include "device.h"  #include "device.h"
# Line 86  static void plx_map_space(struct plx_dat Line 87  static void plx_map_space(struct plx_dat
87  }  }
88    
89  /* PLX device common access routine */  /* PLX device common access routine */
90  void *dev_plx_access(cpu_mips_t *cpu,struct vdevice *dev,  void *dev_plx_access(cpu_gen_t *cpu,struct vdevice *dev,
91                       m_uint32_t offset,u_int op_size,u_int op_type,                       m_uint32_t offset,u_int op_size,u_int op_type,
92                       m_uint64_t *data)                       m_uint64_t *data)
93  {  {
# Line 130  void *dev_plx_access(cpu_mips_t *cpu,str Line 131  void *dev_plx_access(cpu_mips_t *cpu,str
131           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
132              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
133                      "read from unhandled addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unhandled addr 0x%x, pc=0x%llx (size=%u)\n",
134                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
135           } else {           } else {
136              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
137                      "write to handled addr 0x%x, value=0x%llx, "                      "write to handled addr 0x%x, value=0x%llx, "
138                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
139                        offset,*data,cpu_get_pc(cpu),op_size);
140           }           }
141     }     }
142    
# Line 142  void *dev_plx_access(cpu_mips_t *cpu,str Line 144  void *dev_plx_access(cpu_mips_t *cpu,str
144  }  }
145    
146  /* PLX9054 access routine */  /* PLX9054 access routine */
147  void *dev_plx9054_access(cpu_mips_t *cpu,struct vdevice *dev,  void *dev_plx9054_access(cpu_gen_t *cpu,struct vdevice *dev,
148                           m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
149                           m_uint64_t *data)                           m_uint64_t *data)
150  {  {
# Line 172  void *dev_plx9054_access(cpu_mips_t *cpu Line 174  void *dev_plx9054_access(cpu_mips_t *cpu
174  /*  /*
175   * pci_plx_read() - Common PCI read.   * pci_plx_read() - Common PCI read.
176   */   */
177  static m_uint32_t pci_plx_read(cpu_mips_t *cpu,struct pci_device *dev,int reg)  static m_uint32_t pci_plx_read(cpu_gen_t *cpu,struct pci_device *dev,int reg)
178  {    {  
179     struct plx_data *d = dev->priv_data;     struct plx_data *d = dev->priv_data;
180    
# Line 196  static m_uint32_t pci_plx_read(cpu_mips_ Line 198  static m_uint32_t pci_plx_read(cpu_mips_
198  /*  /*
199   * pci_plx_write() - Common PCI write.   * pci_plx_write() - Common PCI write.
200   */   */
201  static void pci_plx_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_plx_write(cpu_gen_t *cpu,struct pci_device *dev,
202                            int reg,m_uint32_t value)                            int reg,m_uint32_t value)
203  {  {
204     struct plx_data *d = dev->priv_data;     struct plx_data *d = dev->priv_data;
# Line 223  static void pci_plx_write(cpu_mips_t *cp Line 225  static void pci_plx_write(cpu_mips_t *cp
225  /*  /*
226   * pci_plx9054_read()   * pci_plx9054_read()
227   */   */
228  static m_uint32_t pci_plx9054_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_plx9054_read(cpu_gen_t *cpu,struct pci_device *dev,
229                                     int reg)                                     int reg)
230  {    {  
231     struct plx_data *d = dev->priv_data;     struct plx_data *d = dev->priv_data;
# Line 244  static m_uint32_t pci_plx9054_read(cpu_m Line 246  static m_uint32_t pci_plx9054_read(cpu_m
246  /*  /*
247   * pci_plx9054_write()   * pci_plx9054_write()
248   */   */
249  static void pci_plx9054_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_plx9054_write(cpu_gen_t *cpu,struct pci_device *dev,
250                                int reg,m_uint32_t value)                                int reg,m_uint32_t value)
251  {  {
252     struct plx_data *d = dev->priv_data;     struct plx_data *d = dev->priv_data;

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