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dpavlin |
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/* |
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dpavlin |
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* Cisco router simulation platform. |
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dpavlin |
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* Copyright (C) 2005-2006 Christophe Fillot. All rights reserved. |
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* |
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* PA-MC-8TE1 card. Doesn't work at this time. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <errno.h> |
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#include <pthread.h> |
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#include <assert.h> |
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dpavlin |
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#include "cpu.h" |
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#include "vm.h" |
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dpavlin |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "net.h" |
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#include "net_io.h" |
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#include "ptask.h" |
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#include "dev_c7200.h" |
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#include "dev_plx.h" |
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/* Debugging flags */ |
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#define DEBUG_ACCESS 1 |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_TRANSMIT 1 |
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#define DEBUG_RECEIVE 1 |
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/* SSRAM */ |
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#define SSRAM_START 0x10000 |
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#define SSRAM_END 0x30000 |
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/* PA-MC-8TE1 Data */ |
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struct pa_mc_data { |
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char *name; |
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/* Virtual machine */ |
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vm_instance_t *vm; |
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/* PCI device information */ |
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struct vdevice dev; |
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struct pci_device *pci_dev; |
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/* SSRAM device */ |
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struct vdevice ssram_dev; |
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char *ssram_name; |
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m_uint8_t ssram_data[0x20000]; |
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/* PLX9054 */ |
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vm_obj_t *plx_obj; |
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/* NetIO descriptor */ |
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netio_desc_t *nio; |
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/* TX ring scanner task id */ |
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ptask_id_t tx_tid; |
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}; |
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/* Log a PA-MC-8TE1 message */ |
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#define PA_MC_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg) |
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/* |
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* dev_ssram_access |
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*/ |
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dpavlin |
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static void *dev_ssram_access(cpu_gen_t *cpu,struct vdevice *dev, |
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dpavlin |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct pa_mc_data *d = dev->priv_data; |
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if (op_type == MTS_READ) |
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*data = 0; |
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if ((offset >= SSRAM_START) && (offset < SSRAM_END)) |
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return(&d->ssram_data[offset-SSRAM_START]); |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name, |
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"read access to offset = 0x%x, pc = 0x%llx (size=%u)\n", |
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dpavlin |
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offset,cpu_get_pc(cpu),op_size); |
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} else { |
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cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
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dpavlin |
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"val = 0x%llx (size=%u)\n", |
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offset,cpu_get_pc(cpu),*data,op_size); |
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dpavlin |
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} |
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#endif |
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switch(offset) { |
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case 0xfff0c: |
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if (op_type == MTS_READ) |
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*data = 0xdeadbeef; |
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break; |
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case 0xfff10: |
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if (op_type == MTS_READ) |
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*data = 0xbeeffeed; |
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break; |
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case 0x08: /* max_dsx1 */ |
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case 0x10: /* no_buf */ |
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case 0x18: /* ev */ |
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if (op_type == MTS_READ) |
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*data = 0x0ULL; |
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break; |
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case 0x00: /* tx packets */ |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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break; |
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case 0x04: /* rx packets */ |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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break; |
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case 0x0c: /* rx drops */ |
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if (op_type == MTS_READ) |
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*data = 0; |
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break; |
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} |
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return NULL; |
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} |
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/* Callback when PLX9054 PCI-to-Local register is written */ |
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static void plx9054_doorbell_callback(struct plx_data *plx_data, |
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struct pa_mc_data *pa_data, |
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m_uint32_t val) |
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{ |
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printf("DOORBELL: 0x%x\n",val); |
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/* Trigger interrupt */ |
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vm_set_irq(pa_data->vm,2); |
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vm_set_irq(pa_data->vm,3); |
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} |
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/* |
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* pa_mc8te1_access() |
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*/ |
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dpavlin |
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static void *pa_mc8te1_access(cpu_gen_t *cpu,struct vdevice *dev, |
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dpavlin |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct pa_mc_data *d = dev->priv_data; |
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if (op_type == MTS_READ) |
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*data = 0; |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", |
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dpavlin |
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offset,cpu_get_pc(cpu)); |
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} else { |
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cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
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dpavlin |
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"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
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dpavlin |
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} |
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#endif |
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switch(offset) { |
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#if DEBUG_UNKNOWN |
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default: |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,d->name, |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
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dpavlin |
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offset,cpu_get_pc(cpu),op_size); |
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dpavlin |
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} else { |
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cpu_log(cpu,d->name, |
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"write to unknown addr 0x%x, value=0x%llx, " |
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dpavlin |
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"pc=0x%llx (size=%u)\n", |
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offset,*data,cpu_get_pc(cpu),op_size); |
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dpavlin |
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} |
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#endif |
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} |
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return NULL; |
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} |
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/* |
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* pci_pos_read() |
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*/ |
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dpavlin |
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static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg) |
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dpavlin |
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{ |
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struct pa_mc_data *d = dev->priv_data; |
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#if DEBUG_ACCESS |
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PA_MC_LOG(d,"read PCI register 0x%x\n",reg); |
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#endif |
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switch(reg) { |
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case PCI_REG_BAR0: |
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return(d->dev.phys_addr); |
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default: |
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return(0); |
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} |
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} |
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/* |
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* pci_pos_write() |
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*/ |
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dpavlin |
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static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev, |
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dpavlin |
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int reg,m_uint32_t value) |
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{ |
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struct pa_mc_data *d = dev->priv_data; |
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#if DEBUG_ACCESS |
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PA_MC_LOG(d,"write 0x%x to PCI register 0x%x\n",value,reg); |
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#endif |
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switch(reg) { |
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case PCI_REG_BAR0: |
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//vm_map_device(cpu->vm,&d->dev,(m_uint64_t)value); |
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PA_MC_LOG(d,"registers are mapped at 0x%x\n",value); |
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break; |
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} |
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} |
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/* |
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* dev_c7200_pa_mc8te1_init() |
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* |
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* Add a PA-MC-8TE1 port adapter into specified slot. |
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*/ |
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int dev_c7200_pa_mc8te1_init(c7200_t *router,char *name,u_int pa_bay) |
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{ |
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struct pa_mc_data *d; |
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/* Allocate the private data structure for PA-MC-8TE1 chip */ |
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if (!(d = malloc(sizeof(*d)))) { |
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fprintf(stderr,"%s (PA-MC-8TE1): out of memory\n",name); |
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return(-1); |
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} |
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memset(d,0,sizeof(*d)); |
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d->name = name; |
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d->vm = router->vm; |
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/* Set the EEPROM */ |
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c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-MC-8TE1")); |
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/* Create the PM7380 */ |
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d->pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name, |
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0x11f8, 0x7380, |
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0,0,C7200_NETIO_IRQ,d, |
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NULL,pci_pos_read,pci_pos_write); |
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/* Initialize SSRAM device */ |
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d->ssram_name = dyn_sprintf("%s_ssram",name); |
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dev_init(&d->ssram_dev); |
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d->ssram_dev.name = d->ssram_name; |
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d->ssram_dev.priv_data = d; |
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d->ssram_dev.handler = dev_ssram_access; |
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/* Create the PLX9054 */ |
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d->plx_obj = dev_plx9054_init(d->vm,d->name, |
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router->pa_bay[pa_bay].pci_map,1, |
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&d->ssram_dev,NULL); |
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/* Set callback function for PLX9054 PCI-To-Local doorbell */ |
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dev_plx_set_pci2loc_doorbell_cbk(d->plx_obj->data, |
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(dev_plx_doorbell_cbk) |
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plx9054_doorbell_callback, |
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d); |
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/* Store device info into the router structure */ |
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return(c7200_pa_set_drvinfo(router,pa_bay,d)); |
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} |
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/* Remove a PA-POS-OC3 from the specified slot */ |
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int dev_c7200_pa_mc8te1_shutdown(c7200_t *router,u_int pa_bay) |
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{ |
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struct c7200_pa_bay *bay; |
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struct pa_mc_data *d; |
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if (!(bay = c7200_pa_get_info(router,pa_bay))) |
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return(-1); |
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d = bay->drv_info; |
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/* Remove the PA EEPROM */ |
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c7200_pa_unset_eeprom(router,pa_bay); |
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/* Remove the PCI device */ |
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pci_dev_remove(d->pci_dev); |
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/* Remove the PLX9054 chip */ |
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vm_object_remove(d->vm,d->plx_obj); |
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/* Remove the device from the CPU address space */ |
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//vm_unbind_device(router->vm,&d->dev); |
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vm_unbind_device(router->vm,&d->ssram_dev); |
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cpu_group_rebuild_mts(router->vm->cpu_group); |
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/* Free the device structure itself */ |
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free(d); |
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return(0); |
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} |
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/* Bind a Network IO descriptor to a specific port */ |
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int dev_c7200_pa_mc8te1_set_nio(c7200_t *router,u_int pa_bay,u_int port_id, |
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netio_desc_t *nio) |
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{ |
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struct pa_mc_data *d; |
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if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay))) |
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return(-1); |
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if (d->nio != NULL) |
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return(-1); |
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d->nio = nio; |
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//d->tx_tid = ptask_add((ptask_callback)dev_pos_oc3_handle_txring,d,NULL); |
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//netio_rxl_add(nio,(netio_rx_handler_t)dev_pos_oc3_handle_rxring,d,NULL); |
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return(0); |
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} |
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/* Bind a Network IO descriptor to a specific port */ |
323 |
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int dev_c7200_pa_mc8te1_unset_nio(c7200_t *router,u_int pa_bay,u_int port_id) |
324 |
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{ |
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struct pa_mc_data *d; |
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if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay))) |
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return(-1); |
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330 |
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if (d->nio) { |
331 |
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ptask_remove(d->tx_tid); |
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netio_rxl_remove(d->nio); |
333 |
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d->nio = NULL; |
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} |
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return(0); |
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} |
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/* PA-MC-8TE1 driver */ |
339 |
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struct c7200_pa_driver dev_c7200_pa_mc8te1_driver = { |
340 |
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"PA-MC-8TE1", 0, |
341 |
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dev_c7200_pa_mc8te1_init, |
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dev_c7200_pa_mc8te1_shutdown, |
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dev_c7200_pa_mc8te1_set_nio, |
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dev_c7200_pa_mc8te1_unset_nio, |
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NULL, |
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}; |