1 |
/* |
2 |
* Cisco router Simulation Platform. |
3 |
* Copyright (c) 2005-2007 Christophe Fillot. All rights reserved. |
4 |
* |
5 |
* EEPROM types: |
6 |
* - 0x95: PA-POS-OC3SMI |
7 |
* - 0x96: PA-POS-OC3MM |
8 |
* |
9 |
* Just an experimentation (I don't have any PA-POS-OC3). It basically works, |
10 |
* on NPE-400. There is something strange with the buffer addresses in TX ring, |
11 |
* preventing this driver working with platforms using SRAM. |
12 |
*/ |
13 |
|
14 |
#include <stdio.h> |
15 |
#include <stdlib.h> |
16 |
#include <string.h> |
17 |
#include <unistd.h> |
18 |
#include <errno.h> |
19 |
#include <pthread.h> |
20 |
#include <assert.h> |
21 |
|
22 |
#include "cpu.h" |
23 |
#include "vm.h" |
24 |
#include "dynamips.h" |
25 |
#include "memory.h" |
26 |
#include "device.h" |
27 |
#include "net.h" |
28 |
#include "net_io.h" |
29 |
#include "ptask.h" |
30 |
#include "dev_c7200.h" |
31 |
#include "dev_plx.h" |
32 |
|
33 |
/* Debugging flags */ |
34 |
#define DEBUG_ACCESS 0 |
35 |
#define DEBUG_UNKNOWN 1 |
36 |
#define DEBUG_TRANSMIT 0 |
37 |
#define DEBUG_RECEIVE 0 |
38 |
|
39 |
/* PCI vendor/product codes */ |
40 |
#define POS_OC3_PCI_VENDOR_ID 0x10b5 |
41 |
#define POS_OC3_PCI_PRODUCT_ID 0x9060 |
42 |
|
43 |
/* Maximum packet size */ |
44 |
#define POS_OC3_MAX_PKT_SIZE 8192 |
45 |
|
46 |
/* RX descriptors */ |
47 |
#define POS_OC3_RXDESC_OWN 0x80000000 /* Ownership */ |
48 |
#define POS_OC3_RXDESC_WRAP 0x40000000 /* Wrap ring */ |
49 |
#define POS_OC3_RXDESC_CONT 0x08000000 /* Packet continues */ |
50 |
#define POS_OC3_RXDESC_LEN_MASK 0x1fff |
51 |
|
52 |
/* TX descriptors */ |
53 |
#define POS_OC3_TXDESC_OWN 0x80000000 /* Ownership */ |
54 |
#define POS_OC3_TXDESC_WRAP 0x40000000 /* Wrap ring */ |
55 |
#define POS_OC3_TXDESC_CONT 0x08000000 /* Packet continues */ |
56 |
#define POS_OC3_TXDESC_LEN_MASK 0x1fff |
57 |
|
58 |
/* RX Descriptor */ |
59 |
struct rx_desc { |
60 |
m_uint32_t rdes[2]; |
61 |
}; |
62 |
|
63 |
/* TX Descriptor */ |
64 |
struct tx_desc { |
65 |
m_uint32_t tdes[2]; |
66 |
}; |
67 |
|
68 |
/* PA-POS-OC3 Data */ |
69 |
struct pos_oc3_data { |
70 |
char *name; |
71 |
|
72 |
/* physical addresses for start and end of RX/TX rings */ |
73 |
m_uint32_t rx_start,rx_end,tx_start,tx_end; |
74 |
|
75 |
/* physical addresses of current RX and TX descriptors */ |
76 |
m_uint32_t rx_current,tx_current; |
77 |
|
78 |
/* Virtual machine */ |
79 |
vm_instance_t *vm; |
80 |
|
81 |
/* Virtual devices */ |
82 |
char *rx_name,*tx_name,*cs_name; |
83 |
vm_obj_t *rx_obj,*tx_obj,*cs_obj; |
84 |
struct vdevice rx_dev,tx_dev,cs_dev; |
85 |
|
86 |
/* PCI device information */ |
87 |
struct vdevice dev; |
88 |
struct pci_device *pci_dev; |
89 |
|
90 |
/* NetIO descriptor */ |
91 |
netio_desc_t *nio; |
92 |
|
93 |
/* TX ring scanner task id */ |
94 |
ptask_id_t tx_tid; |
95 |
}; |
96 |
|
97 |
/* Log a PA-POS-OC3 message */ |
98 |
#define POS_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg) |
99 |
|
100 |
/* |
101 |
* pos_access() |
102 |
*/ |
103 |
static void *dev_pos_access(cpu_gen_t *cpu,struct vdevice *dev, |
104 |
m_uint32_t offset,u_int op_size,u_int op_type, |
105 |
m_uint64_t *data) |
106 |
{ |
107 |
struct pos_oc3_data *d = dev->priv_data; |
108 |
|
109 |
if (op_type == MTS_READ) |
110 |
*data = 0; |
111 |
|
112 |
#if DEBUG_ACCESS |
113 |
if (op_type == MTS_READ) { |
114 |
cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", |
115 |
offset,cpu_get_pc(cpu)); |
116 |
} else { |
117 |
if (offset != 0x404) |
118 |
cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
119 |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
120 |
} |
121 |
#endif |
122 |
|
123 |
switch(offset) { |
124 |
case 0x404: |
125 |
if (op_type == MTS_READ) |
126 |
*data = 0xFFFFFFFF; |
127 |
break; |
128 |
case 0x406: |
129 |
if (op_type == MTS_READ) |
130 |
*data = 0xFFFFFFFF; |
131 |
break; |
132 |
case 0x407: |
133 |
if (op_type == MTS_READ) |
134 |
*data = 0xFFFFFFFF; |
135 |
break; |
136 |
|
137 |
#if DEBUG_UNKNOWN |
138 |
default: |
139 |
if (op_type == MTS_READ) { |
140 |
cpu_log(cpu,d->name, |
141 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
142 |
offset,cpu_get_pc(cpu),op_size); |
143 |
} else { |
144 |
cpu_log(cpu,d->name, |
145 |
"write to unknown addr 0x%x, value=0x%llx, " |
146 |
"pc=0x%llx (size=%u)\n", |
147 |
offset,*data,cpu_get_pc(cpu),op_size); |
148 |
} |
149 |
#endif |
150 |
} |
151 |
|
152 |
return NULL; |
153 |
} |
154 |
|
155 |
/* |
156 |
* pos_rx_access() |
157 |
*/ |
158 |
static void *dev_pos_rx_access(cpu_gen_t *cpu,struct vdevice *dev, |
159 |
m_uint32_t offset,u_int op_size,u_int op_type, |
160 |
m_uint64_t *data) |
161 |
{ |
162 |
struct pos_oc3_data *d = dev->priv_data; |
163 |
|
164 |
if (op_type == MTS_READ) |
165 |
*data = 0; |
166 |
|
167 |
#if DEBUG_ACCESS |
168 |
if (op_type == MTS_READ) { |
169 |
cpu_log(cpu,d->name,"read access to offset = 0x%x, pc = 0x%llx\n", |
170 |
offset,cpu_get_pc(cpu)); |
171 |
} else { |
172 |
cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
173 |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
174 |
} |
175 |
#endif |
176 |
|
177 |
switch(offset) { |
178 |
case 0x04: |
179 |
if (op_type == MTS_READ) |
180 |
*data = d->rx_start; |
181 |
else |
182 |
d->rx_start = *data; |
183 |
break; |
184 |
|
185 |
case 0x08: |
186 |
if (op_type == MTS_READ) |
187 |
*data = d->rx_current; |
188 |
else |
189 |
d->rx_current = *data; |
190 |
break; |
191 |
|
192 |
#if DEBUG_UNKNOWN |
193 |
default: |
194 |
if (op_type == MTS_READ) { |
195 |
cpu_log(cpu,d->rx_name, |
196 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
197 |
offset,cpu_get_pc(cpu),op_size); |
198 |
} else { |
199 |
cpu_log(cpu,d->rx_name, |
200 |
"write to unknown addr 0x%x, value=0x%llx, " |
201 |
"pc=0x%llx (size=%u)\n", |
202 |
offset,*data,cpu_get_pc(cpu),op_size); |
203 |
} |
204 |
#endif |
205 |
} |
206 |
|
207 |
return NULL; |
208 |
} |
209 |
|
210 |
/* |
211 |
* pos_tx_access() |
212 |
*/ |
213 |
static void *dev_pos_tx_access(cpu_gen_t *cpu,struct vdevice *dev, |
214 |
m_uint32_t offset,u_int op_size,u_int op_type, |
215 |
m_uint64_t *data) |
216 |
{ |
217 |
struct pos_oc3_data *d = dev->priv_data; |
218 |
|
219 |
if (op_type == MTS_READ) |
220 |
*data = 0; |
221 |
|
222 |
#if DEBUG_ACCESS |
223 |
if (op_type == MTS_READ) { |
224 |
cpu_log(cpu,d->tx_name,"read access to offset = 0x%x, pc = 0x%llx\n", |
225 |
offset,cpu_get_pc(cpu)); |
226 |
} else { |
227 |
cpu_log(cpu,d->tx_name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
228 |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
229 |
} |
230 |
#endif |
231 |
|
232 |
switch(offset) { |
233 |
case 0x04: |
234 |
if (op_type == MTS_READ) |
235 |
*data = d->tx_start; |
236 |
else |
237 |
d->tx_start = *data; |
238 |
break; |
239 |
|
240 |
case 0x08: |
241 |
if (op_type == MTS_READ) |
242 |
*data = d->tx_current; |
243 |
else |
244 |
d->tx_current = *data; |
245 |
break; |
246 |
|
247 |
#if DEBUG_UNKNOWN |
248 |
default: |
249 |
if (op_type == MTS_READ) { |
250 |
cpu_log(cpu,d->tx_name, |
251 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
252 |
offset,cpu_get_pc(cpu),op_size); |
253 |
} else { |
254 |
cpu_log(cpu,d->tx_name, |
255 |
"write to unknown addr 0x%x, value=0x%llx, " |
256 |
"pc=0x%llx (size=%u)\n", |
257 |
offset,*data,cpu_get_pc(cpu),op_size); |
258 |
} |
259 |
#endif |
260 |
} |
261 |
|
262 |
return NULL; |
263 |
} |
264 |
|
265 |
/* |
266 |
* pos_cs_access() |
267 |
*/ |
268 |
static void *dev_pos_cs_access(cpu_gen_t *cpu,struct vdevice *dev, |
269 |
m_uint32_t offset,u_int op_size,u_int op_type, |
270 |
m_uint64_t *data) |
271 |
{ |
272 |
struct pos_oc3_data *d = dev->priv_data; |
273 |
|
274 |
if (op_type == MTS_READ) |
275 |
*data = 0; |
276 |
|
277 |
#if DEBUG_ACCESS |
278 |
if (op_type == MTS_READ) { |
279 |
cpu_log(cpu,d->cs_name,"read access to offset = 0x%x, pc = 0x%llx\n", |
280 |
offset,cpu_get_pc(cpu)); |
281 |
} else { |
282 |
cpu_log(cpu,d->cs_name,"write access to vaddr = 0x%x, pc = 0x%llx, " |
283 |
"val = 0x%llx\n",offset,cpu_get_pc(cpu),*data); |
284 |
} |
285 |
#endif |
286 |
|
287 |
switch(offset) { |
288 |
case 0x300000: |
289 |
case 0x300004: |
290 |
case 0x30001c: |
291 |
if (op_type == MTS_READ) |
292 |
*data = 0x00000FFF; |
293 |
break; |
294 |
|
295 |
case 0x300008: |
296 |
if (op_type == MTS_READ) |
297 |
*data = 0x000007F; |
298 |
break; |
299 |
|
300 |
#if DEBUG_UNKNOWN |
301 |
default: |
302 |
if (op_type == MTS_READ) { |
303 |
cpu_log(cpu,d->cs_name, |
304 |
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
305 |
offset,cpu_get_pc(cpu),op_size); |
306 |
} else { |
307 |
cpu_log(cpu,d->cs_name, |
308 |
"write to unknown addr 0x%x, value=0x%llx, " |
309 |
"pc=0x%llx (size=%u)\n", |
310 |
offset,*data,cpu_get_pc(cpu),op_size); |
311 |
} |
312 |
#endif |
313 |
} |
314 |
|
315 |
return NULL; |
316 |
} |
317 |
|
318 |
/* |
319 |
* Get the address of the next RX descriptor. |
320 |
*/ |
321 |
static m_uint32_t rxdesc_get_next(struct pos_oc3_data *d,m_uint32_t rxd_addr, |
322 |
struct rx_desc *rxd) |
323 |
{ |
324 |
m_uint32_t nrxd_addr; |
325 |
|
326 |
if (rxd->rdes[0] & POS_OC3_RXDESC_WRAP) |
327 |
nrxd_addr = d->rx_start; |
328 |
else |
329 |
nrxd_addr = rxd_addr + sizeof(struct rx_desc); |
330 |
|
331 |
return(nrxd_addr); |
332 |
} |
333 |
|
334 |
/* Read an RX descriptor */ |
335 |
static void rxdesc_read(struct pos_oc3_data *d,m_uint32_t rxd_addr, |
336 |
struct rx_desc *rxd) |
337 |
{ |
338 |
#if DEBUG_RECEIVE |
339 |
POS_LOG(d,"reading RX descriptor at address 0x%x\n",rxd_addr); |
340 |
#endif |
341 |
|
342 |
/* get the next descriptor from VM physical RAM */ |
343 |
physmem_copy_from_vm(d->vm,rxd,rxd_addr,sizeof(struct rx_desc)); |
344 |
|
345 |
/* byte-swapping */ |
346 |
rxd->rdes[0] = vmtoh32(rxd->rdes[0]); |
347 |
rxd->rdes[1] = vmtoh32(rxd->rdes[1]); |
348 |
} |
349 |
|
350 |
/* |
351 |
* Try to acquire the specified RX descriptor. Returns TRUE if we have it. |
352 |
* It assumes that the byte-swapping is done. |
353 |
*/ |
354 |
static inline int rxdesc_acquire(m_uint32_t rdes0) |
355 |
{ |
356 |
return(rdes0 & POS_OC3_RXDESC_OWN); |
357 |
} |
358 |
|
359 |
/* Put a packet in buffer of a descriptor */ |
360 |
static ssize_t rxdesc_put_pkt(struct pos_oc3_data *d,struct rx_desc *rxd, |
361 |
u_char **pkt,ssize_t *pkt_len) |
362 |
{ |
363 |
ssize_t len,cp_len; |
364 |
|
365 |
len = rxd->rdes[0] & POS_OC3_RXDESC_LEN_MASK; |
366 |
|
367 |
/* compute the data length to copy */ |
368 |
cp_len = m_min(len,*pkt_len); |
369 |
|
370 |
#if DEBUG_RECEIVE |
371 |
POS_LOG(d,"copying %d bytes at 0x%x\n",cp_len,rxd->rdes[1]); |
372 |
#endif |
373 |
|
374 |
/* copy packet data to the VM physical RAM */ |
375 |
physmem_copy_to_vm(d->vm,*pkt,rxd->rdes[1],cp_len); |
376 |
|
377 |
*pkt += cp_len; |
378 |
*pkt_len -= cp_len; |
379 |
return(cp_len); |
380 |
} |
381 |
|
382 |
/* |
383 |
* Put a packet in the RX ring. |
384 |
*/ |
385 |
static void dev_pos_oc3_receive_pkt(struct pos_oc3_data *d, |
386 |
u_char *pkt,ssize_t pkt_len) |
387 |
{ |
388 |
m_uint32_t rx_start,rxdn_addr,rxdn_rdes0; |
389 |
struct rx_desc rxd0,rxdn,*rxdc; |
390 |
ssize_t cp_len,tot_len = pkt_len; |
391 |
u_char *pkt_ptr = pkt; |
392 |
int i; |
393 |
|
394 |
if (d->rx_start == 0) |
395 |
return; |
396 |
|
397 |
/* Truncate the packet if it is too big */ |
398 |
pkt_len = m_min(pkt_len,POS_OC3_MAX_PKT_SIZE); |
399 |
|
400 |
/* Copy the current rxring descriptor */ |
401 |
rxdesc_read(d,d->rx_current,&rxd0); |
402 |
|
403 |
/* We must have the first descriptor... */ |
404 |
if (!rxdesc_acquire(rxd0.rdes[0])) |
405 |
return; |
406 |
|
407 |
/* Remember the first RX descriptor address */ |
408 |
rx_start = d->rx_current; |
409 |
|
410 |
for(i=0,rxdc=&rxd0;tot_len>0;i++) |
411 |
{ |
412 |
/* Put data into the descriptor buffers */ |
413 |
cp_len = rxdesc_put_pkt(d,rxdc,&pkt_ptr,&tot_len); |
414 |
|
415 |
/* Get address of the next descriptor */ |
416 |
rxdn_addr = rxdesc_get_next(d,d->rx_current,rxdc); |
417 |
|
418 |
/* We have finished if the complete packet has been stored */ |
419 |
if (tot_len == 0) { |
420 |
rxdc->rdes[0] = cp_len + 4; |
421 |
|
422 |
if (i != 0) |
423 |
physmem_copy_u32_to_vm(d->vm,d->rx_current,rxdc->rdes[0]); |
424 |
|
425 |
d->rx_current = rxdn_addr; |
426 |
break; |
427 |
} |
428 |
|
429 |
#if DEBUG_RECEIVE |
430 |
POS_LOG(d,"trying to acquire new descriptor at 0x%x\n",rxdn_addr); |
431 |
#endif |
432 |
/* Get status of the next descriptor to see if we can acquire it */ |
433 |
rxdn_rdes0 = physmem_copy_u32_from_vm(d->vm,rxdn_addr); |
434 |
|
435 |
if (!rxdesc_acquire(rxdn_rdes0)) |
436 |
rxdc->rdes[0] = 0; /* error, no buf available (special flag?) */ |
437 |
else |
438 |
rxdc->rdes[0] = POS_OC3_RXDESC_CONT; /* packet continues */ |
439 |
|
440 |
rxdc->rdes[0] |= cp_len; |
441 |
|
442 |
/* Update the new status (only if we are not on the first desc) */ |
443 |
if (i != 0) |
444 |
physmem_copy_u32_to_vm(d->vm,d->rx_current,rxdc->rdes[0]); |
445 |
|
446 |
/* Update the RX pointer */ |
447 |
d->rx_current = rxdn_addr; |
448 |
|
449 |
if (!(rxdc->rdes[0] & POS_OC3_RXDESC_CONT)) |
450 |
break; |
451 |
|
452 |
/* Read the next descriptor from VM physical RAM */ |
453 |
rxdesc_read(d,rxdn_addr,&rxdn); |
454 |
rxdc = &rxdn; |
455 |
} |
456 |
|
457 |
/* Update the first RX descriptor */ |
458 |
physmem_copy_u32_to_vm(d->vm,rx_start,rxd0.rdes[0]); |
459 |
|
460 |
/* Generate IRQ on CPU */ |
461 |
pci_dev_trigger_irq(d->vm,d->pci_dev); |
462 |
} |
463 |
|
464 |
/* Handle the RX ring */ |
465 |
static int dev_pos_oc3_handle_rxring(netio_desc_t *nio, |
466 |
u_char *pkt,ssize_t pkt_len, |
467 |
struct pos_oc3_data *d) |
468 |
{ |
469 |
#if DEBUG_RECEIVE |
470 |
POS_LOG(d,"receiving a packet of %d bytes\n",pkt_len); |
471 |
mem_dump(log_file,pkt,pkt_len); |
472 |
#endif |
473 |
|
474 |
dev_pos_oc3_receive_pkt(d,pkt,pkt_len); |
475 |
return(TRUE); |
476 |
} |
477 |
|
478 |
/* Read a TX descriptor */ |
479 |
static void txdesc_read(struct pos_oc3_data *d,m_uint32_t txd_addr, |
480 |
struct tx_desc *txd) |
481 |
{ |
482 |
/* get the next descriptor from VM physical RAM */ |
483 |
physmem_copy_from_vm(d->vm,txd,txd_addr,sizeof(struct tx_desc)); |
484 |
|
485 |
/* byte-swapping */ |
486 |
txd->tdes[0] = vmtoh32(txd->tdes[0]); |
487 |
txd->tdes[1] = vmtoh32(txd->tdes[1]); |
488 |
} |
489 |
|
490 |
/* Set the address of the next TX descriptor */ |
491 |
static void txdesc_set_next(struct pos_oc3_data *d,struct tx_desc *txd) |
492 |
{ |
493 |
if (txd->tdes[0] & POS_OC3_TXDESC_WRAP) |
494 |
d->tx_current = d->tx_start; |
495 |
else |
496 |
d->tx_current += sizeof(struct tx_desc); |
497 |
} |
498 |
|
499 |
/* Handle the TX ring */ |
500 |
static int dev_pos_oc3_handle_txring(struct pos_oc3_data *d) |
501 |
{ |
502 |
u_char pkt[POS_OC3_MAX_PKT_SIZE],*pkt_ptr; |
503 |
m_uint32_t clen,tot_len,norm_len; |
504 |
m_uint32_t tx_start,addr; |
505 |
struct tx_desc txd0,ctxd,*ptxd; |
506 |
int i,done = FALSE; |
507 |
|
508 |
if ((d->tx_start == 0) || (d->nio == NULL)) |
509 |
return(FALSE); |
510 |
|
511 |
/* Copy the current txring descriptor */ |
512 |
tx_start = d->tx_current; |
513 |
ptxd = &txd0; |
514 |
txdesc_read(d,d->tx_current,ptxd); |
515 |
|
516 |
/* If we don't own the descriptor, we cannot transmit */ |
517 |
if (!(txd0.tdes[0] & POS_OC3_TXDESC_OWN)) |
518 |
return(FALSE); |
519 |
|
520 |
#if DEBUG_TRANSMIT |
521 |
POS_LOG(d,"pos_oc3_handle_txring: 1st desc: tdes[0]=0x%x, tdes[1]=0x%x\n", |
522 |
ptxd->tdes[0],ptxd->tdes[1]); |
523 |
#endif |
524 |
|
525 |
pkt_ptr = pkt; |
526 |
tot_len = 0; |
527 |
i = 0; |
528 |
|
529 |
do { |
530 |
#if DEBUG_TRANSMIT |
531 |
POS_LOG(d,"pos_oc3_handle_txring: loop: tdes[0]=0x%x, tdes[1]=0x%x\n", |
532 |
ptxd->tdes[0],ptxd->tdes[1]); |
533 |
#endif |
534 |
|
535 |
if (!(ptxd->tdes[0] & POS_OC3_TXDESC_OWN)) { |
536 |
POS_LOG(d,"pos_oc3_handle_txring: descriptor not owned!\n"); |
537 |
return(FALSE); |
538 |
} |
539 |
|
540 |
clen = ptxd->tdes[0] & POS_OC3_TXDESC_LEN_MASK; |
541 |
|
542 |
/* Be sure that we have length not null */ |
543 |
if (clen != 0) { |
544 |
addr = ptxd->tdes[1]; |
545 |
|
546 |
norm_len = normalize_size(clen,4,0); |
547 |
physmem_copy_from_vm(d->vm,pkt_ptr,addr,clen); |
548 |
mem_bswap32(pkt_ptr,norm_len); |
549 |
} |
550 |
|
551 |
pkt_ptr += clen; |
552 |
tot_len += clen; |
553 |
|
554 |
/* Clear the OWN bit if this is not the first descriptor */ |
555 |
if (i != 0) |
556 |
physmem_copy_u32_to_vm(d->vm,d->tx_current,0); |
557 |
|
558 |
/* Go to the next descriptor */ |
559 |
txdesc_set_next(d,ptxd); |
560 |
|
561 |
/* Copy the next txring descriptor */ |
562 |
if (ptxd->tdes[0] & POS_OC3_TXDESC_CONT) { |
563 |
txdesc_read(d,d->tx_current,&ctxd); |
564 |
ptxd = &ctxd; |
565 |
i++; |
566 |
} else |
567 |
done = TRUE; |
568 |
}while(!done); |
569 |
|
570 |
if (tot_len != 0) { |
571 |
#if DEBUG_TRANSMIT |
572 |
POS_LOG(d,"sending packet of %u bytes (flags=0x%4.4x)\n", |
573 |
tot_len,txd0.tdes[0]); |
574 |
mem_dump(log_file,pkt,tot_len); |
575 |
#endif |
576 |
/* send it on wire */ |
577 |
netio_send(d->nio,pkt,tot_len); |
578 |
} |
579 |
|
580 |
/* Clear the OWN flag of the first descriptor */ |
581 |
txd0.tdes[0] &= ~POS_OC3_TXDESC_OWN; |
582 |
physmem_copy_u32_to_vm(d->vm,tx_start,txd0.tdes[0]); |
583 |
|
584 |
/* Interrupt on completion */ |
585 |
pci_dev_trigger_irq(d->vm,d->pci_dev); |
586 |
return(TRUE); |
587 |
} |
588 |
|
589 |
/* |
590 |
* pci_pos_read() |
591 |
*/ |
592 |
static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg) |
593 |
{ |
594 |
struct pos_oc3_data *d = dev->priv_data; |
595 |
|
596 |
#if DEBUG_ACCESS |
597 |
POS_LOG(d,"read PCI register 0x%x\n",reg); |
598 |
#endif |
599 |
|
600 |
switch(reg) { |
601 |
case PCI_REG_BAR0: |
602 |
return(d->dev.phys_addr); |
603 |
default: |
604 |
return(0); |
605 |
} |
606 |
} |
607 |
|
608 |
/* |
609 |
* pci_pos_write() |
610 |
*/ |
611 |
static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev, |
612 |
int reg,m_uint32_t value) |
613 |
{ |
614 |
struct pos_oc3_data *d = dev->priv_data; |
615 |
|
616 |
#if DEBUG_ACCESS |
617 |
POS_LOG(d,"write 0x%x to PCI register 0x%x\n",value,reg); |
618 |
#endif |
619 |
|
620 |
switch(reg) { |
621 |
case PCI_REG_BAR0: |
622 |
vm_map_device(cpu->vm,&d->dev,(m_uint64_t)value); |
623 |
POS_LOG(d,"registers are mapped at 0x%x\n",value); |
624 |
break; |
625 |
} |
626 |
} |
627 |
|
628 |
/* |
629 |
* dev_c7200_pa_pos_init() |
630 |
* |
631 |
* Add a PA-POS port adapter into specified slot. |
632 |
*/ |
633 |
int dev_c7200_pa_pos_init(c7200_t *router,char *name,u_int pa_bay) |
634 |
{ |
635 |
struct pci_bus *pci_bus; |
636 |
struct pos_oc3_data *d; |
637 |
|
638 |
/* Allocate the private data structure for PA-POS-OC3 chip */ |
639 |
if (!(d = malloc(sizeof(*d)))) { |
640 |
fprintf(stderr,"%s (PA-POS-OC3): out of memory\n",name); |
641 |
return(-1); |
642 |
} |
643 |
|
644 |
memset(d,0,sizeof(*d)); |
645 |
d->name = name; |
646 |
d->vm = router->vm; |
647 |
|
648 |
/* Set the EEPROM */ |
649 |
c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-POS-OC3")); |
650 |
|
651 |
/* Get the appropriate PCI bus */ |
652 |
pci_bus = router->pa_bay[pa_bay].pci_map; |
653 |
|
654 |
/* Initialize RX device */ |
655 |
d->rx_name = dyn_sprintf("%s_RX",name); |
656 |
dev_init(&d->rx_dev); |
657 |
d->rx_dev.name = d->rx_name; |
658 |
d->rx_dev.priv_data = d; |
659 |
d->rx_dev.handler = dev_pos_rx_access; |
660 |
|
661 |
/* Initialize TX device */ |
662 |
d->tx_name = dyn_sprintf("%s_TX",name); |
663 |
dev_init(&d->tx_dev); |
664 |
d->tx_dev.name = d->tx_name; |
665 |
d->tx_dev.priv_data = d; |
666 |
d->tx_dev.handler = dev_pos_tx_access; |
667 |
|
668 |
/* Initialize CS device */ |
669 |
d->cs_name = dyn_sprintf("%s_CS",name); |
670 |
dev_init(&d->cs_dev); |
671 |
d->cs_dev.name = d->cs_name; |
672 |
d->cs_dev.priv_data = d; |
673 |
d->cs_dev.handler = dev_pos_cs_access; |
674 |
|
675 |
/* Initialize PLX9060 for RX part */ |
676 |
d->rx_obj = dev_plx9060_init(d->vm,d->rx_name,pci_bus,0,&d->rx_dev); |
677 |
|
678 |
/* Initialize PLX9060 for TX part */ |
679 |
d->tx_obj = dev_plx9060_init(d->vm,d->tx_name,pci_bus,1,&d->tx_dev); |
680 |
|
681 |
/* Initialize PLX9060 for CS part (CS=card status, chip status, ... ?) */ |
682 |
d->cs_obj = dev_plx9060_init(d->vm,d->cs_name,pci_bus,2,&d->cs_dev); |
683 |
|
684 |
/* Unknown PCI device here (will be mapped at 0x30000) */ |
685 |
dev_init(&d->dev); |
686 |
d->dev.name = name; |
687 |
d->dev.priv_data = d; |
688 |
d->dev.phys_len = 0x10000; |
689 |
d->dev.handler = dev_pos_access; |
690 |
|
691 |
d->pci_dev = pci_dev_add(pci_bus,name,0,0,3,0,C7200_NETIO_IRQ, |
692 |
d,NULL,pci_pos_read,pci_pos_write); |
693 |
|
694 |
/* Store device info into the router structure */ |
695 |
return(c7200_pa_set_drvinfo(router,pa_bay,d)); |
696 |
} |
697 |
|
698 |
/* Remove a PA-POS-OC3 from the specified slot */ |
699 |
int dev_c7200_pa_pos_shutdown(c7200_t *router,u_int pa_bay) |
700 |
{ |
701 |
struct c7200_pa_bay *bay; |
702 |
struct pos_oc3_data *d; |
703 |
|
704 |
if (!(bay = c7200_pa_get_info(router,pa_bay))) |
705 |
return(-1); |
706 |
|
707 |
d = bay->drv_info; |
708 |
|
709 |
/* Remove the PA EEPROM */ |
710 |
c7200_pa_unset_eeprom(router,pa_bay); |
711 |
|
712 |
/* Remove the PCI device */ |
713 |
pci_dev_remove(d->pci_dev); |
714 |
|
715 |
/* Remove the PLX9060 chips */ |
716 |
vm_object_remove(d->vm,d->rx_obj); |
717 |
vm_object_remove(d->vm,d->tx_obj); |
718 |
vm_object_remove(d->vm,d->cs_obj); |
719 |
|
720 |
/* Remove the devices from the CPU address space */ |
721 |
vm_unbind_device(router->vm,&d->rx_dev); |
722 |
vm_unbind_device(router->vm,&d->tx_dev); |
723 |
vm_unbind_device(router->vm,&d->cs_dev); |
724 |
|
725 |
vm_unbind_device(router->vm,&d->dev); |
726 |
cpu_group_rebuild_mts(router->vm->cpu_group); |
727 |
|
728 |
/* Free the device structure itself */ |
729 |
free(d); |
730 |
return(0); |
731 |
} |
732 |
|
733 |
/* Bind a Network IO descriptor to a specific port */ |
734 |
int dev_c7200_pa_pos_set_nio(c7200_t *router,u_int pa_bay,u_int port_id, |
735 |
netio_desc_t *nio) |
736 |
{ |
737 |
struct pos_oc3_data *d; |
738 |
|
739 |
if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay))) |
740 |
return(-1); |
741 |
|
742 |
if (d->nio != NULL) |
743 |
return(-1); |
744 |
|
745 |
d->nio = nio; |
746 |
d->tx_tid = ptask_add((ptask_callback)dev_pos_oc3_handle_txring,d,NULL); |
747 |
netio_rxl_add(nio,(netio_rx_handler_t)dev_pos_oc3_handle_rxring,d,NULL); |
748 |
return(0); |
749 |
} |
750 |
|
751 |
/* Bind a Network IO descriptor to a specific port */ |
752 |
int dev_c7200_pa_pos_unset_nio(c7200_t *router,u_int pa_bay,u_int port_id) |
753 |
{ |
754 |
struct pos_oc3_data *d; |
755 |
|
756 |
if ((port_id > 0) || !(d = c7200_pa_get_drvinfo(router,pa_bay))) |
757 |
return(-1); |
758 |
|
759 |
if (d->nio) { |
760 |
ptask_remove(d->tx_tid); |
761 |
netio_rxl_remove(d->nio); |
762 |
d->nio = NULL; |
763 |
} |
764 |
return(0); |
765 |
} |
766 |
|
767 |
/* PA-POS-OC3 driver */ |
768 |
struct c7200_pa_driver dev_c7200_pa_pos_oc3_driver = { |
769 |
"PA-POS-OC3", 1, |
770 |
dev_c7200_pa_pos_init, |
771 |
dev_c7200_pa_pos_shutdown, |
772 |
dev_c7200_pa_pos_set_nio, |
773 |
dev_c7200_pa_pos_unset_nio, |
774 |
NULL, |
775 |
}; |