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/* |
/* |
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* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
* |
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* Cisco C7200 (Predator) Midplane FPGA. |
* Cisco c7200 Midplane FPGA. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include <stdlib.h> |
#include <stdlib.h> |
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#include <string.h> |
#include <string.h> |
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|
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#include "mips64.h" |
#include "cpu.h" |
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|
#include "vm.h" |
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#include "dynamips.h" |
#include "dynamips.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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|
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#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
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#define DEBUG_OIR 0 |
#define DEBUG_OIR 1 |
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|
|
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/* |
/* |
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* Definitions for Port Adapter Status. |
* Definitions for Port Adapter Status. |
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/* PA Power. Bay 0 is always powered */ |
/* PA Power. Bay 0 is always powered */ |
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res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; |
res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; |
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|
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/* We fake power on bays defined by the final user */ |
/* We fake power on bays defined by the final user */ |
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if (c7200_pa_check_eeprom(d->router,1)) |
if (c7200_pa_check_eeprom(d->router,1)) |
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res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; |
res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; |
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/* |
/* |
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* dev_mpfpga_access() |
* dev_mpfpga_access() |
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*/ |
*/ |
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void *dev_c7200_mpfpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
m_uint64_t *data) |
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{ |
{ |
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#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
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} else { |
} else { |
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cpu_log(cpu,"MP_FPGA", |
cpu_log(cpu,"MP_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
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} |
} |
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#endif |
#endif |
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|
|
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
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*data = 0x66666600 & d->pa_status_reg; |
*data = 0x66666600 & d->pa_status_reg; |
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|
|
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mips64_clear_irq(cpu,C7200_PA_MGMT_IRQ); |
vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ); |
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break; |
break; |
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|
|
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case 0x48: /* ??? (test) */ |
case 0x48: /* ??? (test) */ |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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#if DEBUG_OIR |
#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", |
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offset,cpu->pc,d->router->oir_status); |
offset,cpu_get_pc(cpu),d->router->oir_status); |
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#endif |
#endif |
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*data = d->router->oir_status; |
*data = d->router->oir_status; |
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vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
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} else { |
} else { |
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#if DEBUG_OIR |
#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " |
cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " |
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"(data=0x%llx)\n",offset,cpu->pc,*data); |
"(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data); |
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#endif |
#endif |
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d->router->oir_status &= ~(*data); |
d->router->oir_status &= ~(*data); |
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vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
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case 0x78: |
case 0x78: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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#if DEBUG_OIR |
#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",cpu->pc); |
cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n", |
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|
cpu_get_pc(cpu)); |
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#endif |
#endif |
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*data = 0x00; |
*data = 0x00; |
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} else { |
} else { |
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#if DEBUG_OIR |
#if DEBUG_OIR |
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cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " |
cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " |
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"(data=0x%llx)\n",cpu->pc,*data); |
"(data=0x%llx)\n",cpu_get_pc(cpu),*data); |
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#endif |
#endif |
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} |
} |
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break; |
break; |
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default: |
default: |
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if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", |
cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", |
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offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
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} else { |
} else { |
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cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " |
cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " |
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"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
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} |
} |
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#endif |
#endif |
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} |
} |