--- upstream/dynamips-0.2.6-RC1/dev_c7200_mpfpga.c 2007/10/06 16:03:58 2 +++ upstream/dynamips-0.2.7-RC1/dev_c7200_mpfpga.c 2007/10/06 16:23:47 7 @@ -1,15 +1,16 @@ /* - * Cisco 7200 (Predator) simulation platform. + * Cisco router simulation platform. * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) * - * Cisco C7200 (Predator) Midplane FPGA. + * Cisco c7200 Midplane FPGA. */ #include #include #include -#include "mips64.h" +#include "cpu.h" +#include "vm.h" #include "dynamips.h" #include "memory.h" #include "device.h" @@ -18,7 +19,7 @@ #define DEBUG_UNKNOWN 1 #define DEBUG_ACCESS 0 -#define DEBUG_OIR 0 +#define DEBUG_OIR 1 /* * Definitions for Port Adapter Status. @@ -90,56 +91,53 @@ /* Bay 0 */ { BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT, BAY0_EEPROM_DIN_BIT , BAY0_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 1 */ { BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT, BAY1_EEPROM_DIN_BIT , BAY1_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 2 */ { BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT, BAY2_EEPROM_DIN_BIT , BAY2_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 3 */ { BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT, BAY3_EEPROM_DIN_BIT , BAY3_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 4 */ { BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT, BAY4_EEPROM_DIN_BIT , BAY4_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 5 */ { BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT, BAY5_EEPROM_DIN_BIT , BAY5_EEPROM_DOUT_BIT, - NULL, 0 }, + }, /* Bay 6 */ { BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT, BAY6_EEPROM_DIN_BIT , BAY6_EEPROM_DOUT_BIT, - NULL, 0 }, + }, }; /* EEPROM group #1 (Bays 0, 1, 3, 4) */ static const struct nmc93c46_group eeprom_bays_g1 = { 4, 0, "PA Bays (Group #1) EEPROM", FALSE, - { NULL, NULL, NULL, NULL }, - - { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, - { 0, 0, 0, 0, 0} }, + { &eeprom_bay_def[0], &eeprom_bay_def[1], + &eeprom_bay_def[3], &eeprom_bay_def[4], + }, }; /* EEPROM group #2 (Bays 2, 5, 6) */ static const struct nmc93c46_group eeprom_bays_g2 = { - 3, 0, "PA Bays (Group #2) EEPROM", FALSE, - - { NULL, NULL, NULL }, + 3, 0, "PA Bays (Group #2) EEPROM", FALSE, - { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0} }, + { &eeprom_bay_def[2], &eeprom_bay_def[5], &eeprom_bay_def[6] }, }; /* Midplane FPGA private data */ @@ -159,7 +157,7 @@ /* PA Power. Bay 0 is always powered */ res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; - + /* We fake power on bays defined by the final user */ if (c7200_pa_check_eeprom(d->router,1)) res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; @@ -185,7 +183,7 @@ /* * dev_mpfpga_access() */ -void *dev_c7200_mpfpga_access(cpu_mips_t *cpu,struct vdevice *dev, +void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev, m_uint32_t offset,u_int op_size,u_int op_type, m_uint64_t *data) { @@ -201,11 +199,11 @@ #if DEBUG_ACCESS if (op_type == MTS_READ) { cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", - offset,cpu->pc,op_size); + offset,cpu_get_pc(cpu),op_size); } else { cpu_log(cpu,"MP_FPGA", "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", - offset,cpu->pc,*data,op_size); + offset,cpu_get_pc(cpu),*data,op_size); } #endif @@ -242,7 +240,7 @@ if (op_type == MTS_READ) *data = 0x66666600 & d->pa_status_reg; - mips64_clear_irq(cpu,C7200_PA_MGMT_IRQ); + vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ); break; case 0x48: /* ??? (test) */ @@ -261,13 +259,14 @@ if (op_type == MTS_READ) { #if DEBUG_OIR cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", - offset,cpu->pc,d->router->oir_status); + offset,cpu_get_pc(cpu),d->router->oir_status); #endif *data = d->router->oir_status; + vm_clear_irq(d->router->vm,C7200_OIR_IRQ); } else { #if DEBUG_OIR cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " - "(data=0x%llx)\n",offset,cpu->pc,*data); + "(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data); #endif d->router->oir_status &= ~(*data); vm_clear_irq(d->router->vm,C7200_OIR_IRQ); @@ -281,13 +280,14 @@ case 0x78: if (op_type == MTS_READ) { #if DEBUG_OIR - cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",cpu->pc); + cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n", + cpu_get_pc(cpu)); #endif *data = 0x00; } else { #if DEBUG_OIR cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " - "(data=0x%llx)\n",cpu->pc,*data); + "(data=0x%llx)\n",cpu_get_pc(cpu),*data); #endif } break; @@ -330,10 +330,10 @@ default: if (op_type == MTS_READ) { cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", - offset,cpu->pc); + offset,cpu_get_pc(cpu)); } else { cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " - "pc=0x%llx\n",offset,*data,cpu->pc); + "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); } #endif } @@ -344,32 +344,18 @@ /* Initialize EEPROM groups */ static void init_eeprom_groups(c7200_t *router) { - struct nmc93c46_group *g; - int i; - - for(i=0;ipa_bay[i].eeprom,&eeprom_bay_def[i], - sizeof(struct nmc93c46_eeprom_def)); - } - /* Group 1: bays 0, 1, 3, 4 */ - g = &router->pa_eeprom_g1; - memcpy(g,&eeprom_bays_g1,sizeof(struct nmc93c46_group)); - g->def[0] = &router->pa_bay[0].eeprom; - g->def[1] = &router->pa_bay[1].eeprom; - g->def[2] = &router->pa_bay[3].eeprom; - g->def[3] = &router->pa_bay[4].eeprom; + router->pa_eeprom_g1 = eeprom_bays_g1; + router->pa_eeprom_g1.eeprom[0] = &router->pa_bay[0].eeprom; + router->pa_eeprom_g1.eeprom[1] = &router->pa_bay[1].eeprom; + router->pa_eeprom_g1.eeprom[2] = &router->pa_bay[3].eeprom; + router->pa_eeprom_g1.eeprom[3] = &router->pa_bay[4].eeprom; /* Group 2: bays 2, 5, 6 */ - g = &router->pa_eeprom_g2; - memcpy(g,&eeprom_bays_g2,sizeof(struct nmc93c46_group)); - g->def[0] = &router->pa_bay[2].eeprom; - g->def[1] = &router->pa_bay[5].eeprom; - g->def[2] = &router->pa_bay[6].eeprom; - - /* Set empty EEPROMs for all slots */ - for(i=0;ipa_eeprom_g2 = eeprom_bays_g2; + router->pa_eeprom_g2.eeprom[0] = &router->pa_bay[2].eeprom; + router->pa_eeprom_g2.eeprom[1] = &router->pa_bay[5].eeprom; + router->pa_eeprom_g2.eeprom[2] = &router->pa_bay[6].eeprom; } /* Shutdown the MP FPGA device */