128 |
#define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock) |
#define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock) |
129 |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
130 |
|
|
|
/* Empty EEPROM */ |
|
|
static const m_uint16_t eeprom_empty_data[16] = { |
|
|
0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, |
|
|
0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, |
|
|
}; |
|
|
|
|
131 |
/* CPU EEPROM definition */ |
/* CPU EEPROM definition */ |
132 |
static const struct nmc93c46_eeprom_def eeprom_cpu_def = { |
static const struct nmc93c46_eeprom_def eeprom_cpu_def = { |
133 |
SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU, |
134 |
DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU, |
|
NULL, 0, |
|
135 |
}; |
}; |
136 |
|
|
137 |
/* Midplane EEPROM definition */ |
/* Midplane EEPROM definition */ |
138 |
static const struct nmc93c46_eeprom_def eeprom_midplane_def = { |
static const struct nmc93c46_eeprom_def eeprom_midplane_def = { |
139 |
SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE, |
140 |
DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE, |
|
NULL, 0, |
|
141 |
}; |
}; |
142 |
|
|
143 |
/* PEM (NPE-B) EEPROM definition */ |
/* PEM (NPE-B) EEPROM definition */ |
144 |
static const struct nmc93c46_eeprom_def eeprom_pem_def = { |
static const struct nmc93c46_eeprom_def eeprom_pem_def = { |
145 |
SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM, |
SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM, |
|
(m_uint16_t *)eeprom_empty_data, (sizeof(eeprom_empty_data) / 2), |
|
146 |
}; |
}; |
147 |
|
|
148 |
/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
/* IOFPGA manages simultaneously CPU and Midplane EEPROM */ |
149 |
static const struct nmc93c46_group eeprom_cpu_midplane = { |
static const struct nmc93c46_group eeprom_cpu_midplane = { |
150 |
2, 0, "CPU and Midplane EEPROM", 0, |
2, 0, "CPU and Midplane EEPROM", 0, |
151 |
{ NULL, NULL, }, { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0} }, |
{ &eeprom_cpu_def, &eeprom_midplane_def }, |
152 |
}; |
}; |
153 |
|
|
154 |
/* |
/* |
157 |
* http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml |
* http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml |
158 |
*/ |
*/ |
159 |
static const struct nmc93c46_group eeprom_pem_npeb = { |
static const struct nmc93c46_group eeprom_pem_npeb = { |
160 |
1, 0, "PEM (NPE-B) EEPROM", 0, { NULL }, { { 0, 0, 0, 0, 0} }, |
1, 0, "PEM (NPE-B) EEPROM", 0, { &eeprom_pem_def }, |
161 |
}; |
}; |
162 |
|
|
163 |
/* Reset DS1620 */ |
/* Reset DS1620 */ |
603 |
/* Initialize EEPROM groups */ |
/* Initialize EEPROM groups */ |
604 |
void c7200_init_eeprom_groups(c7200_t *router) |
void c7200_init_eeprom_groups(c7200_t *router) |
605 |
{ |
{ |
606 |
struct nmc93c46_group *g; |
router->sys_eeprom_g1 = eeprom_cpu_midplane; |
607 |
|
router->sys_eeprom_g2 = eeprom_pem_npeb; |
608 |
/* Copy EEPROM definitions */ |
|
609 |
memcpy(&router->cpu_eeprom,&eeprom_cpu_def,sizeof(eeprom_cpu_def)); |
router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom; |
610 |
memcpy(&router->mp_eeprom,&eeprom_midplane_def,sizeof(eeprom_midplane_def)); |
router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom; |
611 |
memcpy(&router->pem_eeprom,&eeprom_pem_def,sizeof(eeprom_pem_def)); |
|
612 |
|
router->sys_eeprom_g2.eeprom[0] = &router->pem_eeprom; |
|
/* Initialize groups */ |
|
|
g = &router->sys_eeprom_g1; |
|
|
memcpy(g,&eeprom_cpu_midplane,sizeof(eeprom_cpu_midplane)); |
|
|
g->def[0] = &router->cpu_eeprom; |
|
|
g->def[1] = &router->mp_eeprom; |
|
|
|
|
|
g = &router->sys_eeprom_g2; |
|
|
memcpy(g,&eeprom_pem_npeb,sizeof(eeprom_pem_npeb)); |
|
|
g->def[0] = &router->pem_eeprom; |
|
613 |
} |
} |
614 |
|
|
615 |
/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |