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dpavlin |
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/* |
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* Cisco 3600 simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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* |
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* TODO: Online Insertion/Removal (OIR). |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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#include "nmc93c46.h" |
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#include "dev_c3600.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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/* Definitions for Mainboard EEPROM */ |
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#define EEPROM_MB_DOUT 3 |
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#define EEPROM_MB_DIN 2 |
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#define EEPROM_MB_CLK 1 |
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#define EEPROM_MB_CS 0 |
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/* Definitions for Network Modules EEPROM */ |
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#define EEPROM_NM_DOUT 7 |
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#define EEPROM_NM_DIN 6 |
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#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
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dpavlin |
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#define C3600_NET_IRQ_CLEARING_DELAY 16 |
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dpavlin |
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/* IO FPGA structure */ |
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struct iofpga_data { |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c3600_t *router; |
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dpavlin |
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/* |
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* Used to introduce a "delay" before clearing the network interrupt |
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* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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dpavlin |
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/* Slot select for EEPROM access */ |
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u_int eeprom_slot; |
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/* IO Mask. Don't know the meaning */ |
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m_uint8_t io_mask; |
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m_uint16_t sel; |
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}; |
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/* Mainboard EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
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/* Mainboard EEPROM */ |
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static const struct nmc93c46_group eeprom_mb_group = { |
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dpavlin |
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1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
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dpavlin |
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}; |
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/* NM EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
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/* NM EEPROM */ |
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static const struct nmc93c46_group eeprom_nm_group = { |
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dpavlin |
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1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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dpavlin |
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}; |
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/* C3660 NM presence masks */ |
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static const m_uint16_t c3660_nm_masks[6] = { |
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0xF0FF, /* slot 1 */ |
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0xFFF0, /* slot 2 */ |
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0x0FFF, /* slot 3 */ |
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0xFF0F, /* slot 4 */ |
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0xF0FF, /* slot 5 */ |
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0xFFF0, /* slot 6 */ |
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}; |
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/* Select the current NM EEPROM */ |
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static void nm_eeprom_select(struct iofpga_data *d,u_int slot) |
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{ |
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dpavlin |
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d->router->nm_eeprom_group.eeprom[0] = &d->router->nm_bay[slot].eeprom; |
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dpavlin |
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} |
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/* Return the NM status register given the detected EEPROM (3620/3640) */ |
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static u_int nm_get_status_1(struct iofpga_data *d) |
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{ |
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u_int res = 0xFFFF; |
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int i; |
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for(i=0;i<4;i++) { |
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if (c3600_nm_check_eeprom(d->router,i)) |
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res &= ~(0x1111 << i); |
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} |
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return(res); |
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} |
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/* Return the NM status register given the detected EEPROM (3660) */ |
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static u_int nm_get_status_2(struct iofpga_data *d,u_int pos) |
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{ |
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u_int res = 0xFFFF; |
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u_int start,end; |
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int i; |
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switch(pos) { |
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case 0: /* word 0: slot 1 - 4 */ |
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start = 1; |
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end = 4; |
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break; |
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case 1: /* word 1: slot 5 - 6 */ |
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start = 5; |
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end = 6; |
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break; |
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default: |
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return(res); |
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} |
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for(i=start;i<=end;i++) { |
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if (c3600_nm_check_eeprom(d->router,i)) |
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res &= c3660_nm_masks[i-1]; |
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} |
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return(res); |
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} |
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/* |
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* dev_c3620_c3640_iofpga_access() |
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*/ |
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static void * |
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dev_c3620_c3640_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct iofpga_data *d = dev->priv_data; |
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u_int slot; |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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#if DEBUG_ACCESS |
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if (offset != 0x0c) { |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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offset,cpu->pc,op_size); |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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offset,cpu->pc,*data,op_size); |
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} |
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} |
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#endif |
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switch(offset) { |
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/* Probably flash protection (if 0, no write access allowed) */ |
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case 0x00008: |
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if (op_type == MTS_READ) |
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*data = 0xFF; |
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break; |
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/* Bootflash of 8 Mb */ |
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case 0x0000a: |
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if (op_type == MTS_READ) |
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*data = 0x1000; |
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break; |
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/* |
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* 0x7d00 is written here regularly. |
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* Some kind of hardware watchdog ? |
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*/ |
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case 0x0000c: |
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break; |
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/* Mainboard EEPROM */ |
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case 0x0000e: |
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if (op_type == MTS_WRITE) |
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nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
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else |
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*data = nmc93c46_read(&d->router->mb_eeprom_group); |
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break; |
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case 0x10004: /* ??? OIR control ??? */ |
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if (op_type == MTS_READ) { |
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*data = 0x0000; |
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} |
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break; |
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/* |
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* Network modules presence. |
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* |
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* Bit 0: 0 = NM in slot 0 is valid |
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* Bit 1: 0 = NM in slot 1 is valid |
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* Bit 2: 0 = NM in slot 2 is valid |
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* Bit 3: 0 = NM in slot 3 is valid |
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* |
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* Very well explained on Cisco website: |
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* http://www.cisco.com/en/US/customer/products/hw/routers/ps274/products_tech_note09186a0080109510.shtml |
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*/ |
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case 0x10006: |
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if (op_type == MTS_READ) |
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*data = nm_get_status_1(d); |
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break; |
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/* |
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* NM EEPROMs. |
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*/ |
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case 0x10008: |
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if (op_type == MTS_WRITE) { |
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d->eeprom_slot = *data & 0x03; |
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nm_eeprom_select(d,d->eeprom_slot); |
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nmc93c46_write(&d->router->nm_eeprom_group,*data); |
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} else { |
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*data = nmc93c46_read(&d->router->nm_eeprom_group); |
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} |
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break; |
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/* Network interrupt status */ |
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case 0x20000: |
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case 0x20001: |
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case 0x20002: |
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case 0x20003: |
244 |
dpavlin |
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/* XXX This doesn't seem to be correct (at least on 3620) */ |
245 |
dpavlin |
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slot = offset - 0x20000; |
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if (op_type == MTS_READ) |
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*data = 0xFF; |
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250 |
dpavlin |
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if (++d->net_irq_clearing_count == C3600_NET_IRQ_CLEARING_DELAY) { |
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vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
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d->net_irq_clearing_count = 0; |
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} |
254 |
dpavlin |
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break; |
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256 |
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/* |
257 |
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* Read when a PA Management interrupt is triggered. |
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* |
259 |
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* If not 0, we get: |
260 |
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* "Error: Unexpected NM Interrupt received from slot: x" |
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*/ |
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case 0x20004: |
263 |
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if (op_type == MTS_READ) |
264 |
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*data = 0x00; |
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vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ); |
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break; |
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268 |
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/* |
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* Read when an external interrupt is triggered. |
270 |
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* |
271 |
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* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s) |
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* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF |
273 |
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* |
274 |
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* oir_ctrl = register 0x10004 |
275 |
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* oir_stat = register 0x10006 |
276 |
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*/ |
277 |
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case 0x20006: |
278 |
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if (op_type == MTS_READ) |
279 |
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*data = 0x00; |
280 |
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vm_clear_irq(d->router->vm,C3600_EXT_IRQ); |
281 |
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break; |
282 |
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283 |
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/* IO Mask (displayed by "show c3600") */ |
284 |
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case 0x20008: |
285 |
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if (op_type == MTS_READ) |
286 |
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*data = d->io_mask; |
287 |
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else |
288 |
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d->io_mask = *data; |
289 |
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break; |
290 |
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291 |
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/* ??? */ |
292 |
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/* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */ |
293 |
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case 0x30000: |
294 |
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if (op_type == MTS_READ) { |
295 |
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switch(c3600_chassis_get_id(d->router)) { |
296 |
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case 3620: |
297 |
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*data = 4 << 5; |
298 |
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break; |
299 |
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case 3640: |
300 |
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*data = 0 << 5; |
301 |
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break; |
302 |
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case 3660: |
303 |
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*data = 3 << 5; |
304 |
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break; |
305 |
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default: |
306 |
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*data = 0; |
307 |
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} |
308 |
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} |
309 |
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break; |
310 |
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311 |
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/* ??? */ |
312 |
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case 0x30002: |
313 |
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if (op_type == MTS_WRITE) { |
314 |
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d->sel = *data; |
315 |
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} else { |
316 |
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//*data = d->sel; |
317 |
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} |
318 |
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break; |
319 |
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320 |
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/* |
321 |
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* Environmental parameters, determined with "sh env all". |
322 |
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* |
323 |
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* Bit 0: 0 = overtemperature condition. |
324 |
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* Bit 4: 0 = RPS present. |
325 |
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* Bit 5: 0 = Input Voltage status failure. |
326 |
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* Bit 6: 1 = Thermal status failure. |
327 |
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* Bit 7: 1 = DC Output Voltage status failure. |
328 |
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*/ |
329 |
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case 0x30004: |
330 |
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if (op_type == MTS_READ) { |
331 |
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*data = 32 + 1; |
332 |
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} |
333 |
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break; |
334 |
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335 |
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#if DEBUG_UNKNOWN |
336 |
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default: |
337 |
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if (op_type == MTS_READ) { |
338 |
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cpu_log(cpu,"IO_FPGA", |
339 |
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"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
340 |
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offset,cpu->pc,op_size); |
341 |
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} else { |
342 |
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cpu_log(cpu,"IO_FPGA", |
343 |
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"write to unknown addr 0x%x, value=0x%llx, " |
344 |
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"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
345 |
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} |
346 |
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#endif |
347 |
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} |
348 |
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349 |
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return NULL; |
350 |
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} |
351 |
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|
352 |
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/* |
353 |
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* dev_c3660_iofpga_access() |
354 |
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*/ |
355 |
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static void * |
356 |
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dev_c3660_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
357 |
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m_uint32_t offset,u_int op_size,u_int op_type, |
358 |
|
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m_uint64_t *data) |
359 |
|
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{ |
360 |
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struct iofpga_data *d = dev->priv_data; |
361 |
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u_int slot; |
362 |
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|
363 |
|
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if (op_type == MTS_READ) |
364 |
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*data = 0x0; |
365 |
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|
366 |
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#if DEBUG_ACCESS |
367 |
|
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if (offset != 0x0c) { |
368 |
|
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if (op_type == MTS_READ) { |
369 |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
370 |
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offset,cpu->pc,op_size); |
371 |
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} else { |
372 |
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cpu_log(cpu,"IO_FPGA", |
373 |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
374 |
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offset,cpu->pc,*data,op_size); |
375 |
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} |
376 |
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} |
377 |
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#endif |
378 |
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|
379 |
|
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switch(offset) { |
380 |
|
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/* |
381 |
|
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* 0x7d00 is written here regularly. |
382 |
|
|
* Some kind of hardware watchdog ? |
383 |
|
|
*/ |
384 |
|
|
case 0x0000c: |
385 |
|
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break; |
386 |
|
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|
387 |
|
|
/* Probably flash protection (if 0, no write access allowed) */ |
388 |
|
|
case 0x00008: |
389 |
|
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if (op_type == MTS_READ) |
390 |
|
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*data = 0xFF; |
391 |
|
|
break; |
392 |
|
|
|
393 |
|
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/* Bootflash of 8 Mb */ |
394 |
|
|
case 0x0000a: |
395 |
|
|
if (op_type == MTS_READ) |
396 |
|
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*data = 0x1000; |
397 |
|
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break; |
398 |
|
|
|
399 |
|
|
/* NM presence - slots 1 to 4 */ |
400 |
|
|
case 0x10006: |
401 |
|
|
if (op_type == MTS_READ) |
402 |
|
|
*data = nm_get_status_2(d,0); |
403 |
|
|
break; |
404 |
|
|
|
405 |
|
|
/* NM presence - slot 5 to 6 */ |
406 |
|
|
case 0x10008: |
407 |
|
|
if (op_type == MTS_READ) |
408 |
|
|
*data = nm_get_status_2(d,1); |
409 |
|
|
break; |
410 |
|
|
|
411 |
|
|
/* Fan status, PS presence */ |
412 |
|
|
case 0x10018: |
413 |
|
|
if (op_type == MTS_READ) |
414 |
|
|
*data = 0x0000; |
415 |
|
|
break; |
416 |
|
|
|
417 |
|
|
/* unknown, read by env monitor */ |
418 |
|
|
case 0x1001a: |
419 |
|
|
if (op_type == MTS_READ) |
420 |
|
|
*data = 0x0000; |
421 |
|
|
break; |
422 |
|
|
|
423 |
|
|
/* board temperature */ |
424 |
|
|
case 0x30004: |
425 |
|
|
if (op_type == MTS_READ) { |
426 |
|
|
*data = 32 + 1; |
427 |
|
|
} |
428 |
|
|
break; |
429 |
|
|
|
430 |
|
|
/* sh c3600: Per Slot Intr Mask */ |
431 |
|
|
case 0x10016: |
432 |
|
|
if (op_type == MTS_READ) |
433 |
|
|
*data = 0x12; |
434 |
|
|
break; |
435 |
|
|
|
436 |
|
|
/* sh c3600: OIR fsm state slot's (12) */ |
437 |
|
|
case 0x10020: |
438 |
|
|
if (op_type == MTS_READ) |
439 |
|
|
*data = 0x00; |
440 |
|
|
break; |
441 |
|
|
|
442 |
|
|
/* sh c3600: OIR fsm state slot's (34) */ |
443 |
|
|
case 0x10022: |
444 |
|
|
if (op_type == MTS_READ) |
445 |
|
|
*data = 0x00; |
446 |
|
|
break; |
447 |
|
|
|
448 |
|
|
/* sh c3600: OIR fsm state slot's (56) */ |
449 |
|
|
case 0x10024: |
450 |
|
|
if (op_type == MTS_READ) |
451 |
|
|
*data = 0x00; |
452 |
|
|
break; |
453 |
|
|
|
454 |
|
|
/* |
455 |
|
|
* Backplane EEPROM. |
456 |
|
|
* |
457 |
|
|
* Bit 7: 0=Telco chassis, 1=Enterprise chassis. |
458 |
|
|
*/ |
459 |
|
|
case 0x10000: |
460 |
|
|
if (op_type == MTS_WRITE) |
461 |
|
|
nmc93c46_write(&d->router->mb_eeprom_group,(u_int)(*data)); |
462 |
|
|
else |
463 |
|
|
*data = nmc93c46_read(&d->router->mb_eeprom_group) | 0x80; |
464 |
|
|
break; |
465 |
|
|
|
466 |
|
|
/* NM EEPROMs - slots 1 to 6 */ |
467 |
|
|
case 0x1000a: |
468 |
|
|
case 0x1000b: |
469 |
|
|
case 0x1000c: |
470 |
|
|
case 0x1000d: |
471 |
|
|
case 0x1000e: |
472 |
|
|
case 0x1000f: |
473 |
|
|
slot = (offset - 0x1000a) + 1; |
474 |
|
|
|
475 |
|
|
if (op_type == MTS_WRITE) { |
476 |
|
|
nmc93c46_write(&d->router->c3660_nm_eeprom_group[slot], |
477 |
|
|
(u_int)(*data)); |
478 |
|
|
} else { |
479 |
|
|
*data = nmc93c46_read(&d->router->c3660_nm_eeprom_group[slot]); |
480 |
|
|
} |
481 |
|
|
break; |
482 |
|
|
|
483 |
|
|
/* NM EEPROM - slot 0 */ |
484 |
|
|
case 0x20006: |
485 |
|
|
if (op_type == MTS_WRITE) { |
486 |
|
|
nmc93c46_write(&d->router->c3660_nm_eeprom_group[0], |
487 |
|
|
(u_int)(*data)); |
488 |
|
|
} else { |
489 |
|
|
*data = nmc93c46_read(&d->router->c3660_nm_eeprom_group[0]); |
490 |
|
|
} |
491 |
|
|
break; |
492 |
|
|
|
493 |
|
|
/* Unknown EEPROMs ? */ |
494 |
|
|
case 0x20000: |
495 |
|
|
case 0x20002: |
496 |
|
|
case 0x20004: |
497 |
|
|
if (op_type == MTS_READ) |
498 |
|
|
*data = 0xFFFF; |
499 |
|
|
break; |
500 |
|
|
|
501 |
|
|
/* IO Mask (displayed by "show c3600") */ |
502 |
|
|
case 0x20008: |
503 |
|
|
if (op_type == MTS_READ) |
504 |
|
|
*data = d->io_mask; |
505 |
|
|
else |
506 |
|
|
d->io_mask = *data; |
507 |
|
|
break; |
508 |
|
|
|
509 |
|
|
/* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */ |
510 |
|
|
case 0x30000: |
511 |
|
|
if (op_type == MTS_READ) |
512 |
|
|
*data = 3 << 5; |
513 |
|
|
break; |
514 |
|
|
|
515 |
|
|
/* ??? */ |
516 |
|
|
case 0x30008: |
517 |
|
|
if (op_type == MTS_READ) |
518 |
|
|
*data = 0xFF; |
519 |
|
|
break; |
520 |
|
|
|
521 |
|
|
/* |
522 |
|
|
* Read at net interrupt (size 4). |
523 |
|
|
* It seems that there are 4 lines per slot. |
524 |
|
|
* |
525 |
|
|
* Bit 24-27: slot 1 |
526 |
|
|
* Bit 16-19: slot 2 |
527 |
|
|
* Bit 28-31: slot 3 |
528 |
|
|
* Bit 20-23: slot 4 |
529 |
|
|
* Bit 08-11: slot 5 |
530 |
|
|
* Bit 00-03: slot 6 |
531 |
|
|
* |
532 |
|
|
* Other bits are unknown. |
533 |
|
|
*/ |
534 |
|
|
case 0x10010: |
535 |
|
|
if (op_type == MTS_READ) |
536 |
|
|
*data = 0xFFFFFFFF; |
537 |
|
|
vm_clear_irq(d->router->vm,C3600_NETIO_IRQ); |
538 |
|
|
break; |
539 |
|
|
|
540 |
|
|
/* |
541 |
|
|
* Read at net interrupt (size 1) |
542 |
|
|
* |
543 |
|
|
* Bit 7-6: we get "Unexpected AIM interrupt on AIM slot 1". |
544 |
|
|
* Bit 5-4: we get "Unexpected AIM interrupt on AIM slot 0". |
545 |
|
|
* Bit 0-3: net interrupt for slot 0. |
546 |
|
|
*/ |
547 |
|
|
case 0x20010: |
548 |
|
|
if (op_type == MTS_READ) |
549 |
|
|
*data = 0x0F; |
550 |
|
|
break; |
551 |
|
|
|
552 |
|
|
/* |
553 |
|
|
* Read when a PA Management interrupt is triggered. |
554 |
|
|
* |
555 |
|
|
* If not 0, we get: |
556 |
|
|
* "Error: Unexpected NM Interrupt received from slot: x" |
557 |
|
|
*/ |
558 |
|
|
case 0x10014: |
559 |
|
|
if (op_type == MTS_READ) |
560 |
|
|
*data = 0x00; |
561 |
|
|
vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ); |
562 |
|
|
break; |
563 |
|
|
|
564 |
|
|
/* |
565 |
|
|
* Read when an external interrupt is triggered. |
566 |
|
|
* |
567 |
|
|
* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s) |
568 |
|
|
* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF |
569 |
|
|
* |
570 |
|
|
* oir_ctrl = register 0x10004 |
571 |
|
|
* oir_stat = register 0x10006 |
572 |
|
|
*/ |
573 |
|
|
case 0x2000a: |
574 |
|
|
if (op_type == MTS_READ) |
575 |
|
|
*data = 0x54; |
576 |
|
|
vm_clear_irq(d->router->vm,C3600_EXT_IRQ); |
577 |
|
|
break; |
578 |
|
|
|
579 |
|
|
#if DEBUG_UNKNOWN |
580 |
|
|
default: |
581 |
|
|
if (op_type == MTS_READ) { |
582 |
|
|
cpu_log(cpu,"IO_FPGA", |
583 |
|
|
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
584 |
|
|
offset,cpu->pc,op_size); |
585 |
|
|
} else { |
586 |
|
|
cpu_log(cpu,"IO_FPGA", |
587 |
|
|
"write to unknown addr 0x%x, value=0x%llx, " |
588 |
|
|
"pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size); |
589 |
|
|
} |
590 |
|
|
#endif |
591 |
|
|
} |
592 |
|
|
|
593 |
|
|
return NULL; |
594 |
|
|
} |
595 |
|
|
|
596 |
|
|
/* Initialize EEPROM groups */ |
597 |
|
|
void c3600_init_eeprom_groups(c3600_t *router) |
598 |
|
|
{ |
599 |
|
|
int i; |
600 |
|
|
|
601 |
dpavlin |
3 |
/* Initialize Mainboard EEPROM */ |
602 |
|
|
router->mb_eeprom_group = eeprom_mb_group; |
603 |
|
|
router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom; |
604 |
|
|
router->mb_eeprom.data = NULL; |
605 |
|
|
router->mb_eeprom.len = 0; |
606 |
dpavlin |
1 |
|
607 |
dpavlin |
3 |
/* Initialize NM EEPROM for 3620/3640 */ |
608 |
|
|
router->nm_eeprom_group = eeprom_nm_group; |
609 |
|
|
router->nm_eeprom_group.eeprom[0] = NULL; |
610 |
dpavlin |
1 |
|
611 |
dpavlin |
3 |
/* Initialize NM EEPROM for 3660 */ |
612 |
dpavlin |
1 |
for(i=0;i<C3600_MAX_NM_BAYS;i++) { |
613 |
dpavlin |
3 |
router->c3660_nm_eeprom_group[i] = eeprom_nm_group; |
614 |
|
|
router->c3660_nm_eeprom_group[i].eeprom[0] = &router->nm_bay[i].eeprom; |
615 |
dpavlin |
1 |
} |
616 |
|
|
} |
617 |
|
|
|
618 |
|
|
/* Shutdown the IO FPGA device */ |
619 |
|
|
void dev_c3600_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
620 |
|
|
{ |
621 |
|
|
if (d != NULL) { |
622 |
|
|
/* Remove the device */ |
623 |
|
|
dev_remove(vm,&d->dev); |
624 |
|
|
|
625 |
|
|
/* Free the structure itself */ |
626 |
|
|
free(d); |
627 |
|
|
} |
628 |
|
|
} |
629 |
|
|
|
630 |
|
|
/* |
631 |
|
|
* dev_c3600_iofpga_init() |
632 |
|
|
*/ |
633 |
|
|
int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len) |
634 |
|
|
{ |
635 |
|
|
vm_instance_t *vm = router->vm; |
636 |
|
|
struct iofpga_data *d; |
637 |
|
|
|
638 |
|
|
/* Allocate private data structure */ |
639 |
|
|
if (!(d = malloc(sizeof(*d)))) { |
640 |
|
|
fprintf(stderr,"IO_FPGA: out of memory\n"); |
641 |
|
|
return(-1); |
642 |
|
|
} |
643 |
|
|
|
644 |
|
|
memset(d,0,sizeof(*d)); |
645 |
|
|
d->router = router; |
646 |
|
|
|
647 |
|
|
vm_object_init(&d->vm_obj); |
648 |
|
|
d->vm_obj.name = "io_fpga"; |
649 |
|
|
d->vm_obj.data = d; |
650 |
|
|
d->vm_obj.shutdown = (vm_shutdown_t)dev_c3600_iofpga_shutdown; |
651 |
|
|
|
652 |
|
|
/* Set device properties */ |
653 |
|
|
dev_init(&d->dev); |
654 |
|
|
d->dev.name = "io_fpga"; |
655 |
|
|
d->dev.phys_addr = paddr; |
656 |
|
|
d->dev.phys_len = len; |
657 |
|
|
d->dev.priv_data = d; |
658 |
|
|
|
659 |
|
|
switch(router->chassis_driver->chassis_id) { |
660 |
|
|
case 3620: |
661 |
|
|
case 3640: |
662 |
|
|
d->dev.handler = dev_c3620_c3640_iofpga_access; |
663 |
|
|
break; |
664 |
|
|
case 3660: |
665 |
|
|
d->dev.handler = dev_c3660_iofpga_access; |
666 |
|
|
break; |
667 |
|
|
default: |
668 |
|
|
fprintf(stderr,"C3600 '%s': invalid chassis ID %d\n", |
669 |
|
|
router->vm->name,router->chassis_driver->chassis_id); |
670 |
|
|
free(d); |
671 |
|
|
return(-1); |
672 |
|
|
} |
673 |
|
|
|
674 |
|
|
/* Map this device to the VM */ |
675 |
|
|
vm_bind_device(router->vm,&d->dev); |
676 |
|
|
vm_object_add(vm,&d->vm_obj); |
677 |
|
|
return(0); |
678 |
|
|
} |