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dpavlin |
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/* |
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* Cisco 7200 (Predator) simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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* |
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* MIPS Coprocessor 0 (System Coprocessor) implementation. |
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* We don't use the JIT here, since there is no high performance needed. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <unistd.h> |
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#include <string.h> |
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#include <sys/types.h> |
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#include <sys/stat.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include "rbtree.h" |
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#include "mips64.h" |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "cp0.h" |
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/* MIPS cp0 registers names */ |
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char *mips64_cp0_reg_names[MIPS64_CP0_REG_NR] = { |
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"index" , |
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"random", |
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"entry_lo0", |
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"entry_lo1", |
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"context", |
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"pagemask", |
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"wired", |
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"info", |
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"badvaddr", |
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"count", |
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"entry_hi", |
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"compare", |
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"status", |
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"cause", |
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"epc", |
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"prid", |
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"config", |
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"ll_addr", |
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"watch_lo", |
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"watch_hi", |
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"xcontext", |
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"cp0_r21", |
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"cp0_r22", |
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"cp0_r23", |
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"cp0_r24", |
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"cp0_r25", |
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"ecc", |
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"cache_err", |
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"tag_lo", |
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"tag_hi", |
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"err_epc", |
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"cp0_r31", |
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}; |
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/* Get cp0 register index given its name */ |
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int cp0_get_reg_index(char *name) |
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{ |
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int i; |
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for(i=0;i<MIPS64_CP0_REG_NR;i++) |
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if (!strcmp(mips64_cp0_reg_names[i],name)) |
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return(i); |
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return(-1); |
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} |
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/* Get the CPU operating mode (User,Supervisor or Kernel) - inline version */ |
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static forced_inline u_int cp0_get_mode_inline(cpu_mips_t *cpu) |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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u_int cpu_mode; |
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cpu_mode = cp0->reg[MIPS_CP0_STATUS] >> MIPS_CP0_STATUS_KSU_SHIFT; |
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cpu_mode &= MIPS_CP0_STATUS_KSU_MASK; |
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return(cpu_mode); |
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} |
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/* Get the CPU operating mode (User,Supervisor or Kernel) */ |
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u_int cp0_get_mode(cpu_mips_t *cpu) |
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{ |
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return(cp0_get_mode_inline(cpu)); |
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} |
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/* Check that we are running in kernel mode */ |
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int cp0_check_kernel_mode(cpu_mips_t *cpu) |
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{ |
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u_int cpu_mode; |
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cpu_mode = cp0_get_mode(cpu); |
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if (cpu_mode != MIPS_CP0_STATUS_KM) { |
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/* XXX Branch delay slot */ |
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mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_ILLOP,0); |
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return(1); |
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} |
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return(0); |
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} |
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/* Get value of random register */ |
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static inline u_int cp0_get_random_reg(cpu_mips_t *cpu) |
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{ |
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u_int wired; |
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/* We use the virtual count register as a basic "random" value */ |
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wired = cpu->cp0.reg[MIPS_CP0_WIRED]; |
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return(wired + (cpu->cp0_virt_cnt_reg % (cpu->cp0.tlb_entries - wired))); |
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} |
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/* Get a cp0 register (fast version) */ |
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static inline m_uint64_t cp0_get_reg_fast(cpu_mips_t *cpu,u_int cp0_reg) |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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m_uint32_t delta,res; |
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switch(cp0_reg) { |
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case MIPS_CP0_COUNT: |
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delta = cpu->cp0_virt_cmp_reg - cpu->cp0_virt_cnt_reg; |
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res = (m_uint32_t)cp0->reg[MIPS_CP0_COMPARE]; |
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res -= cpu->vm->clock_divisor * delta; |
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return(sign_extend(res,32)); |
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#if 1 |
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case MIPS_CP0_COMPARE: |
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return(sign_extend(cp0->reg[MIPS_CP0_COMPARE],32)); |
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#else |
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/* really useful and logical ? */ |
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case MIPS_CP0_COMPARE: |
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delta = cpu->cp0_virt_cmp_reg - cpu->cp0_virt_cnt_reg; |
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res = (m_uint32_t)cp0->reg[MIPS_CP0_COUNT]; |
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res += (cpu->vm->clock_divisor * delta); |
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return(res); |
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#endif |
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case MIPS_CP0_INFO: |
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return(MIPS64_R7000_TLB64_ENABLE); |
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case MIPS_CP0_RANDOM: |
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return(cp0_get_random_reg(cpu)); |
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default: |
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return(cp0->reg[cp0_reg]); |
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} |
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} |
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/* Get a cp0 register */ |
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m_uint64_t cp0_get_reg(cpu_mips_t *cpu,u_int cp0_reg) |
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{ |
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return(cp0_get_reg_fast(cpu,cp0_reg)); |
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} |
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/* Set a cp0 register */ |
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static inline void cp0_set_reg(cpu_mips_t *cpu,u_int cp0_reg,m_uint64_t val) |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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m_uint32_t delta; |
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switch(cp0_reg) { |
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case MIPS_CP0_STATUS: |
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case MIPS_CP0_CAUSE: |
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cp0->reg[cp0_reg] = val; |
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mips64_update_irq_flag(cpu); |
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break; |
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case MIPS_CP0_PAGEMASK: |
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cp0->reg[cp0_reg] = val & MIPS_TLB_PAGE_MASK; |
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break; |
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case MIPS_CP0_COMPARE: |
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mips64_clear_irq(cpu,7); |
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mips64_update_irq_flag(cpu); |
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cp0->reg[cp0_reg] = val; |
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delta = val - cp0->reg[MIPS_CP0_COUNT]; |
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cpu->cp0_virt_cnt_reg = 0; |
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cpu->cp0_virt_cmp_reg = delta / cpu->vm->clock_divisor; |
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break; |
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case MIPS_CP0_COUNT: |
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cp0->reg[cp0_reg] = val; |
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delta = cp0->reg[MIPS_CP0_COMPARE] - val; |
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cpu->cp0_virt_cnt_reg = 0; |
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cpu->cp0_virt_cmp_reg = delta / cpu->vm->clock_divisor; |
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break; |
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case MIPS_CP0_TLB_HI: |
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cp0->reg[cp0_reg] = val & MIPS_CP0_HI_SAFE_MASK; |
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break; |
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case MIPS_CP0_TLB_LO_0: |
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case MIPS_CP0_TLB_LO_1: |
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cp0->reg[cp0_reg] = val & MIPS_CP0_LO_SAFE_MASK; |
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break; |
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case MIPS_CP0_RANDOM: |
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case MIPS_CP0_PRID: |
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case MIPS_CP0_CONFIG: |
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/* read only registers */ |
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break; |
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case MIPS_CP0_WIRED: |
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cp0->reg[cp0_reg] = val & MIPS64_TLB_IDX_MASK; |
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break; |
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default: |
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cp0->reg[cp0_reg] = val; |
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} |
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} |
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/* Get a cp0 "set 1" register (R7000) */ |
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m_uint64_t cp0_s1_get_reg(cpu_mips_t *cpu,u_int cp0_s1_reg) |
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{ |
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switch(cp0_s1_reg) { |
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case MIPS_CP0_S1_CONFIG: |
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return(0x7F << 25); |
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case MIPS_CP0_S1_IPLLO: |
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return(cpu->cp0.ipl_lo); |
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case MIPS_CP0_S1_IPLHI: |
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return(cpu->cp0.ipl_hi); |
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case MIPS_CP0_S1_INTCTL: |
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return(cpu->cp0.int_ctl); |
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case MIPS_CP0_S1_DERRADDR0: |
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return(cpu->cp0.derraddr0); |
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case MIPS_CP0_S1_DERRADDR1: |
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return(cpu->cp0.derraddr1); |
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default: |
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/* undefined register */ |
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cpu_log(cpu,"CP0_S1","trying to read unknown register %u\n", |
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cp0_s1_reg); |
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return(0); |
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} |
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} |
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/* Set a cp0 "set 1" register (R7000) */ |
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static inline void cp0_s1_set_reg(cpu_mips_t *cpu,u_int cp0_s1_reg, |
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m_uint64_t val) |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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switch(cp0_s1_reg) { |
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case MIPS_CP0_S1_IPLLO: |
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cp0->ipl_lo = val; |
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break; |
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case MIPS_CP0_S1_IPLHI: |
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cp0->ipl_hi = val; |
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break; |
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case MIPS_CP0_S1_INTCTL: |
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cp0->int_ctl = val; |
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break; |
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case MIPS_CP0_S1_DERRADDR0: |
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cp0->derraddr0 = val; |
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break; |
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case MIPS_CP0_S1_DERRADDR1: |
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cp0->derraddr1 = val; |
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break; |
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default: |
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cpu_log(cpu,"CP0_S1","trying to set unknown register %u (val=0x%x)\n", |
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cp0_s1_reg,val); |
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} |
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} |
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/* DMFC0 */ |
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fastcall void cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cpu->gpr[gp_reg] = cp0_get_reg_fast(cpu,cp0_reg); |
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} |
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/* DMTC0 */ |
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fastcall void cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cp0_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg]); |
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} |
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/* MFC0 */ |
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fastcall void cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cpu->gpr[gp_reg] = sign_extend(cp0_get_reg_fast(cpu,cp0_reg),32); |
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} |
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/* MTC0 */ |
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fastcall void cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cp0_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg] & 0xffffffff); |
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} |
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/* CFC0 */ |
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fastcall void cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cpu->gpr[gp_reg] = sign_extend(cp0_s1_get_reg(cpu,cp0_reg),32); |
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} |
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/* CTC0 */ |
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fastcall void cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg) |
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{ |
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cp0_s1_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg] & 0xffffffff); |
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} |
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/* Get the page size corresponding to a page mask */ |
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static inline m_uint32_t get_page_size(m_uint32_t page_mask) |
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{ |
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return((page_mask + 0x2000) >> 1); |
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} |
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/* Write page size in buffer */ |
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static char *get_page_size_str(char *buffer,size_t len,m_uint32_t page_mask) |
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{ |
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m_uint32_t page_size; |
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page_size = get_page_size(page_mask); |
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/* Mb ? */ |
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if (page_size >= (1024*1024)) |
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snprintf(buffer,len,"%uMB",page_size >> 20); |
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else |
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snprintf(buffer,len,"%uKB",page_size >> 10); |
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return buffer; |
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} |
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337 |
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/* TLB lookup */ |
338 |
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int cp0_tlb_lookup(cpu_mips_t *cpu,m_uint64_t vaddr,mts_map_t *res) |
339 |
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{ |
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mips_cp0_t *cp0 = &cpu->cp0; |
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m_uint64_t v0_addr,v1_addr; |
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m_uint32_t page_size,pca; |
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tlb_entry_t *entry; |
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int i; |
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for(i=0;i<cp0->tlb_entries;i++) { |
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entry = &cp0->tlb[i]; |
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page_size = get_page_size(entry->mask); |
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v0_addr = entry->hi & MIPS_TLB_VPN2_MASK; |
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v1_addr = v0_addr + page_size; |
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/* virtual address in entry 0 ? */ |
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if ((entry->lo0 & MIPS_TLB_V_MASK) && |
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(vaddr >= v0_addr) && (vaddr < v1_addr)) |
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{ |
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res->vaddr = v0_addr; |
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res->paddr = (entry->lo0 & MIPS_TLB_PFN_MASK) << 6; |
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res->paddr &= cpu->addr_bus_mask; |
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res->len = page_size; |
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pca = (entry->lo0 & MIPS_TLB_C_MASK); |
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pca >>= MIPS_TLB_C_SHIFT; |
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res->cached = mips64_cca_cached(pca); |
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res->tlb_index = i; |
367 |
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return(TRUE); |
368 |
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} |
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370 |
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/* virtual address in entry 1 ? */ |
371 |
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if ((entry->lo1 & MIPS_TLB_V_MASK) && |
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(vaddr >= v1_addr) && ((vaddr - v1_addr) < page_size)) |
373 |
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{ |
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res->vaddr = v1_addr; |
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res->paddr = (entry->lo1 & MIPS_TLB_PFN_MASK) << 6; |
376 |
|
|
res->paddr &= cpu->addr_bus_mask; |
377 |
|
|
res->len = page_size; |
378 |
|
|
|
379 |
|
|
pca = (entry->lo1 & MIPS_TLB_C_MASK); |
380 |
|
|
pca >>= MIPS_TLB_C_SHIFT; |
381 |
|
|
res->cached = mips64_cca_cached(pca); |
382 |
|
|
|
383 |
|
|
res->tlb_index = i; |
384 |
|
|
return(TRUE); |
385 |
|
|
} |
386 |
|
|
} |
387 |
|
|
|
388 |
|
|
return(FALSE); |
389 |
|
|
} |
390 |
|
|
|
391 |
|
|
/* |
392 |
|
|
* Map a TLB entry into the MTS. |
393 |
|
|
* |
394 |
|
|
* We apply the physical address bus masking here. |
395 |
|
|
* |
396 |
|
|
* TODO: - Manage ASID |
397 |
|
|
* - Manage CPU Mode (user,supervisor or kernel) |
398 |
|
|
*/ |
399 |
|
|
void cp0_map_tlb_to_mts(cpu_mips_t *cpu,int index) |
400 |
|
|
{ |
401 |
|
|
m_uint64_t v0_addr,v1_addr,p0_addr,p1_addr; |
402 |
|
|
m_uint32_t page_size,pca; |
403 |
|
|
tlb_entry_t *entry; |
404 |
|
|
int cacheable; |
405 |
|
|
|
406 |
|
|
entry = &cpu->cp0.tlb[index]; |
407 |
|
|
|
408 |
|
|
page_size = get_page_size(entry->mask); |
409 |
|
|
v0_addr = entry->hi & MIPS_TLB_VPN2_MASK; |
410 |
|
|
v1_addr = v0_addr + page_size; |
411 |
|
|
|
412 |
|
|
if (entry->lo0 & MIPS_TLB_V_MASK) { |
413 |
|
|
pca = (entry->lo0 & MIPS_TLB_C_MASK); |
414 |
|
|
pca >>= MIPS_TLB_C_SHIFT; |
415 |
|
|
cacheable = mips64_cca_cached(pca); |
416 |
|
|
|
417 |
|
|
p0_addr = (entry->lo0 & MIPS_TLB_PFN_MASK) << 6; |
418 |
|
|
cpu->mts_map(cpu,v0_addr,p0_addr & cpu->addr_bus_mask,page_size, |
419 |
|
|
cacheable,index); |
420 |
|
|
} |
421 |
|
|
|
422 |
|
|
if (entry->lo1 & MIPS_TLB_V_MASK) { |
423 |
|
|
pca = (entry->lo1 & MIPS_TLB_C_MASK); |
424 |
|
|
pca >>= MIPS_TLB_C_SHIFT; |
425 |
|
|
cacheable = mips64_cca_cached(pca); |
426 |
|
|
|
427 |
|
|
p1_addr = (entry->lo1 & MIPS_TLB_PFN_MASK) << 6; |
428 |
|
|
cpu->mts_map(cpu,v1_addr,p1_addr & cpu->addr_bus_mask,page_size, |
429 |
|
|
cacheable,index); |
430 |
|
|
} |
431 |
|
|
} |
432 |
|
|
|
433 |
|
|
/* |
434 |
|
|
* Unmap a TLB entry in the MTS. |
435 |
|
|
*/ |
436 |
|
|
void cp0_unmap_tlb_to_mts(cpu_mips_t *cpu,int index) |
437 |
|
|
{ |
438 |
|
|
m_uint64_t v0_addr,v1_addr; |
439 |
|
|
m_uint32_t page_size; |
440 |
|
|
tlb_entry_t *entry; |
441 |
|
|
|
442 |
|
|
entry = &cpu->cp0.tlb[index]; |
443 |
|
|
|
444 |
|
|
page_size = get_page_size(entry->mask); |
445 |
|
|
v0_addr = entry->hi & MIPS_TLB_VPN2_MASK; |
446 |
|
|
v1_addr = v0_addr + page_size; |
447 |
|
|
|
448 |
|
|
if (entry->lo0 & MIPS_TLB_V_MASK) |
449 |
|
|
cpu->mts_unmap(cpu,v0_addr,page_size,MTS_ACC_T,index); |
450 |
|
|
|
451 |
|
|
if (entry->lo1 & MIPS_TLB_V_MASK) |
452 |
|
|
cpu->mts_unmap(cpu,v1_addr,page_size,MTS_ACC_T,index); |
453 |
|
|
} |
454 |
|
|
|
455 |
|
|
/* Map all TLB entries into the MTS */ |
456 |
|
|
void cp0_map_all_tlb_to_mts(cpu_mips_t *cpu) |
457 |
|
|
{ |
458 |
|
|
int i; |
459 |
|
|
|
460 |
|
|
for(i=0;i<cpu->cp0.tlb_entries;i++) |
461 |
|
|
cp0_map_tlb_to_mts(cpu,i); |
462 |
|
|
} |
463 |
|
|
|
464 |
|
|
/* TLBP: Probe a TLB entry */ |
465 |
|
|
fastcall void cp0_exec_tlbp(cpu_mips_t *cpu) |
466 |
|
|
{ |
467 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
468 |
|
|
m_uint64_t hi_reg,asid,vpn2; |
469 |
|
|
tlb_entry_t *entry; |
470 |
|
|
int i; |
471 |
|
|
|
472 |
|
|
hi_reg = cp0->reg[MIPS_CP0_TLB_HI]; |
473 |
|
|
asid = hi_reg & MIPS_TLB_ASID_MASK; |
474 |
|
|
vpn2 = hi_reg & MIPS_TLB_VPN2_MASK; |
475 |
|
|
|
476 |
|
|
cp0->reg[MIPS_CP0_INDEX] = 0xffffffff80000000ULL; |
477 |
|
|
|
478 |
|
|
for(i=0;i<cp0->tlb_entries;i++) { |
479 |
|
|
entry = &cp0->tlb[i]; |
480 |
|
|
|
481 |
|
|
if (((entry->hi & MIPS_TLB_VPN2_MASK) == vpn2) && |
482 |
|
|
((entry->hi & MIPS_TLB_G_MASK) || |
483 |
|
|
((entry->hi & MIPS_TLB_ASID_MASK) == asid))) |
484 |
|
|
{ |
485 |
|
|
cp0->reg[MIPS_CP0_INDEX] = i; |
486 |
|
|
#if DEBUG_TLB_ACTIVITY |
487 |
|
|
printf("CPU: CP0_TLBP returned %u\n",i); |
488 |
|
|
tlb_dump(cpu); |
489 |
|
|
#endif |
490 |
|
|
} |
491 |
|
|
} |
492 |
|
|
} |
493 |
|
|
|
494 |
|
|
/* TLBR: Read Indexed TLB entry */ |
495 |
|
|
fastcall void cp0_exec_tlbr(cpu_mips_t *cpu) |
496 |
|
|
{ |
497 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
498 |
|
|
tlb_entry_t *entry; |
499 |
|
|
u_int index; |
500 |
|
|
|
501 |
|
|
index = cp0->reg[MIPS_CP0_INDEX]; |
502 |
|
|
|
503 |
|
|
#if DEBUG_TLB_ACTIVITY |
504 |
|
|
cpu_log(cpu,"TLB","CP0_TLBR: reading entry %u.\n",index); |
505 |
|
|
#endif |
506 |
|
|
|
507 |
|
|
if (index < cp0->tlb_entries) |
508 |
|
|
{ |
509 |
|
|
entry = &cp0->tlb[index]; |
510 |
|
|
|
511 |
|
|
cp0->reg[MIPS_CP0_PAGEMASK] = entry->mask; |
512 |
|
|
cp0->reg[MIPS_CP0_TLB_HI] = entry->hi; |
513 |
|
|
cp0->reg[MIPS_CP0_TLB_LO_0] = entry->lo0; |
514 |
|
|
cp0->reg[MIPS_CP0_TLB_LO_1] = entry->lo1; |
515 |
|
|
|
516 |
|
|
/* |
517 |
|
|
* The G bit must be reported in both Lo0 and Lo1 registers, |
518 |
|
|
* and cleared in Hi register. |
519 |
|
|
*/ |
520 |
|
|
if (entry->hi & MIPS_TLB_G_MASK) { |
521 |
|
|
cp0->reg[MIPS_CP0_TLB_LO_0] |= MIPS_CP0_LO_G_MASK; |
522 |
|
|
cp0->reg[MIPS_CP0_TLB_LO_1] |= MIPS_CP0_LO_G_MASK; |
523 |
|
|
cp0->reg[MIPS_CP0_TLB_HI] &= ~MIPS_TLB_G_MASK; |
524 |
|
|
} |
525 |
|
|
} |
526 |
|
|
} |
527 |
|
|
|
528 |
|
|
/* TLBW: Write a TLB entry */ |
529 |
|
|
static inline void cp0_exec_tlbw(cpu_mips_t *cpu,u_int index) |
530 |
|
|
{ |
531 |
|
|
mips_cp0_t *cp0 = &cpu->cp0; |
532 |
|
|
tlb_entry_t *entry; |
533 |
|
|
|
534 |
|
|
#if DEBUG_TLB_ACTIVITY |
535 |
|
|
cpu_log(cpu,"TLB","CP0_TLBWI: writing entry %u " |
536 |
|
|
"[mask=0x%8.8llx,hi=0x%8.8llx,lo0=0x%8.8llx,lo1=0x%8.8llx]\n", |
537 |
|
|
index,cp0->reg[MIPS_CP0_PAGEMASK],cp0->reg[MIPS_CP0_TLB_HI], |
538 |
|
|
cp0->reg[MIPS_CP0_TLB_LO_0],cp0->reg[MIPS_CP0_TLB_LO_1]); |
539 |
|
|
#endif |
540 |
|
|
|
541 |
|
|
if (index < cp0->tlb_entries) |
542 |
|
|
{ |
543 |
|
|
entry = &cp0->tlb[index]; |
544 |
|
|
|
545 |
|
|
/* Unmap the old entry if it was valid */ |
546 |
|
|
cp0_unmap_tlb_to_mts(cpu,index); |
547 |
|
|
|
548 |
|
|
entry->mask = cp0->reg[MIPS_CP0_PAGEMASK] & MIPS_TLB_PAGE_MASK; |
549 |
|
|
entry->hi = cp0->reg[MIPS_CP0_TLB_HI] & ~entry->mask; |
550 |
|
|
entry->hi &= MIPS_CP0_HI_SAFE_MASK; /* clear G bit */ |
551 |
|
|
entry->lo0 = cp0->reg[MIPS_CP0_TLB_LO_0]; |
552 |
|
|
entry->lo1 = cp0->reg[MIPS_CP0_TLB_LO_1]; |
553 |
|
|
|
554 |
|
|
/* if G bit is set in lo0 and lo1, set it in hi */ |
555 |
|
|
if ((entry->lo0 & entry->lo1) & MIPS_CP0_LO_G_MASK) |
556 |
|
|
entry->hi |= MIPS_TLB_G_MASK; |
557 |
|
|
|
558 |
|
|
/* Clear G bit in TLB lo0 and lo1 */ |
559 |
|
|
entry->lo0 &= ~MIPS_CP0_LO_G_MASK; |
560 |
|
|
entry->lo1 &= ~MIPS_CP0_LO_G_MASK; |
561 |
|
|
|
562 |
|
|
/* Inform the MTS subsystem */ |
563 |
|
|
cp0_map_tlb_to_mts(cpu,index); |
564 |
|
|
|
565 |
|
|
#if DEBUG_TLB_ACTIVITY |
566 |
|
|
tlb_dump_entry(cpu,index); |
567 |
|
|
#endif |
568 |
|
|
} |
569 |
|
|
} |
570 |
|
|
|
571 |
|
|
/* TLBWI: Write Indexed TLB entry */ |
572 |
|
|
fastcall void cp0_exec_tlbwi(cpu_mips_t *cpu) |
573 |
|
|
{ |
574 |
|
|
cp0_exec_tlbw(cpu,cpu->cp0.reg[MIPS_CP0_INDEX]); |
575 |
|
|
} |
576 |
|
|
|
577 |
|
|
/* TLBWR: Write Random TLB entry */ |
578 |
|
|
fastcall void cp0_exec_tlbwr(cpu_mips_t *cpu) |
579 |
|
|
{ |
580 |
|
|
cp0_exec_tlbw(cpu,cp0_get_random_reg(cpu)); |
581 |
|
|
} |
582 |
|
|
|
583 |
|
|
/* Raw dump of the TLB */ |
584 |
|
|
void tlb_raw_dump(cpu_mips_t *cpu) |
585 |
|
|
{ |
586 |
|
|
tlb_entry_t *entry; |
587 |
|
|
u_int i; |
588 |
|
|
|
589 |
|
|
printf("TLB dump:\n"); |
590 |
|
|
|
591 |
|
|
for(i=0;i<cpu->cp0.tlb_entries;i++) { |
592 |
|
|
entry = &cpu->cp0.tlb[i]; |
593 |
|
|
printf(" %2d: mask=0x%16.16llx hi=0x%16.16llx " |
594 |
|
|
"lo0=0x%16.16llx lo1=0x%16.16llx\n", |
595 |
|
|
i, entry->mask, entry->hi, entry->lo0, entry->lo1); |
596 |
|
|
} |
597 |
|
|
|
598 |
|
|
printf("\n"); |
599 |
|
|
} |
600 |
|
|
|
601 |
|
|
/* Dump the specified TLB entry */ |
602 |
|
|
void tlb_dump_entry(cpu_mips_t *cpu,u_int index) |
603 |
|
|
{ |
604 |
|
|
tlb_entry_t *entry; |
605 |
|
|
char buffer[256]; |
606 |
|
|
|
607 |
|
|
entry = &cpu->cp0.tlb[index]; |
608 |
|
|
|
609 |
|
|
/* virtual Address */ |
610 |
|
|
printf(" %2d: vaddr=0x%8.8llx ", index, entry->hi & MIPS_TLB_VPN2_MASK); |
611 |
|
|
|
612 |
|
|
/* global or ASID */ |
613 |
|
|
if (entry->hi & MIPS_TLB_G_MASK) |
614 |
|
|
printf("(global) "); |
615 |
|
|
else |
616 |
|
|
printf("(asid 0x%2.2llx) ",entry->hi & MIPS_TLB_ASID_MASK); |
617 |
|
|
|
618 |
|
|
/* 1st page: Lo0 */ |
619 |
|
|
printf("p0="); |
620 |
|
|
|
621 |
|
|
if (entry->lo0 & MIPS_TLB_V_MASK) |
622 |
|
|
printf("0x%9.9llx",(entry->lo0 & MIPS_TLB_PFN_MASK) << 6); |
623 |
|
|
else |
624 |
|
|
printf("(invalid) "); |
625 |
|
|
|
626 |
|
|
printf(" %c ",(entry->lo0 & MIPS_TLB_D_MASK) ? 'D' : ' '); |
627 |
|
|
|
628 |
|
|
/* 2nd page: Lo1 */ |
629 |
|
|
printf("p1="); |
630 |
|
|
|
631 |
|
|
if (entry->lo1 & MIPS_TLB_V_MASK) |
632 |
|
|
printf("0x%9.9llx",(entry->lo1 & MIPS_TLB_PFN_MASK) << 6); |
633 |
|
|
else |
634 |
|
|
printf("(invalid) "); |
635 |
|
|
|
636 |
|
|
printf(" %c ",(entry->lo1 & MIPS_TLB_D_MASK) ? 'D' : ' '); |
637 |
|
|
|
638 |
|
|
/* page size */ |
639 |
|
|
printf(" (%s)\n",get_page_size_str(buffer,sizeof(buffer),entry->mask)); |
640 |
|
|
} |
641 |
|
|
|
642 |
|
|
/* Human-Readable dump of the TLB */ |
643 |
|
|
void tlb_dump(cpu_mips_t *cpu) |
644 |
|
|
{ |
645 |
|
|
u_int i; |
646 |
|
|
|
647 |
|
|
printf("TLB dump:\n"); |
648 |
|
|
|
649 |
|
|
for(i=0;i<cpu->cp0.tlb_entries;i++) |
650 |
|
|
tlb_dump_entry(cpu,i); |
651 |
|
|
|
652 |
|
|
printf("\n"); |
653 |
|
|
} |