--- upstream/dynamips-0.2.7-RC2/ppc32_amd64_trans.h	2007/10/06 16:24:54	8
+++ trunk/ppc32_amd64_trans.h	2007/10/06 16:45:40	12
@@ -33,9 +33,9 @@
 extern struct ppc32_insn_tag ppc32_insn_tags[];
 
 /* Push epilog for an x86 instruction block */
-static forced_inline void ppc32_jit_tcb_push_epilog(ppc32_jit_tcb_t *block)
+static forced_inline void ppc32_jit_tcb_push_epilog(u_char **ptr)
 {
-   amd64_ret(block->jit_ptr);
+   amd64_ret(*ptr);
 }
 
 /* Execute JIT code */
@@ -48,15 +48,20 @@
    offset = (cpu->ia & PPC32_MIN_PAGE_IMASK) >> 2;
    jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];
 
-#if 0
    if (unlikely(!jit_code)) {
-      ppc32_exec_single_step(cpu,vmtoh32(block->ppc_code[offset]));
-      return;
+      ppc32_jit_tcb_set_target_bit(block,cpu->ia);
+
+      if (++block->target_undef_cnt == 16) {
+         ppc32_jit_tcb_recompile(cpu,block);
+         jit_code = (insn_tblock_fptr)block->jit_insn_ptr[offset];
+      } else {
+         ppc32_exec_page(cpu);
+         return;
+      }
    }
-#endif
 
    asm volatile ("movq %0,%%r15"::"r"(cpu):
-                 "r14","r15","rax","rbx","rcx","rdx","rdi","rsi");
+                 "r13","r14","r15","rax","rbx","rcx","rdx","rdi","rsi");
    jit_code();
 }
 
@@ -82,13 +87,4 @@
       x86_patch(code,target);
 }
 
-/* Set the Instruction Address (IA) register */
-void ppc32_set_ia(ppc32_jit_tcb_t *b,m_uint32_t new_ia);
-
-/* Set the Link Register (LR) */
-void ppc32_set_lr(ppc32_jit_tcb_t *b,m_uint32_t new_lr);
-
-/* Increment the number of executed instructions (performance debugging) */
-void ppc32_inc_perf_counter(ppc32_jit_tcb_t *b);
-
 #endif