/[dynamips]/trunk/ppc32.h
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upstream/dynamips-0.2.7/ppc32.h revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/ppc32.h revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 250  enum { Line 250  enum {
250  typedef struct cpu_ppc cpu_ppc_t;  typedef struct cpu_ppc cpu_ppc_t;
251    
252  /* Memory operation function prototype */  /* Memory operation function prototype */
253  typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,  typedef fastcall void (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
254                                         u_int reg);                                        u_int reg);
255    
256  /* BAT type indexes */  /* BAT type indexes */
257  enum {  enum {
# Line 282  typedef struct { Line 282  typedef struct {
282  /* Maximum number of breakpoints */  /* Maximum number of breakpoints */
283  #define PPC32_MAX_BREAKPOINTS  8  #define PPC32_MAX_BREAKPOINTS  8
284    
285    /* zzz */
286    struct ppc32_vtlb_entry {
287       m_uint32_t vaddr;
288       m_uint32_t haddr;
289    };
290    
291  /* PowerPC CPU definition */  /* PowerPC CPU definition */
292  struct cpu_ppc {  struct cpu_ppc {
293     /* Instruction address */     /* Instruction address */
# Line 290  struct cpu_ppc { Line 296  struct cpu_ppc {
296     /* General Purpose registers */     /* General Purpose registers */
297     m_uint32_t gpr[PPC32_GPR_NR];     m_uint32_t gpr[PPC32_GPR_NR];
298    
299       struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];
300    
301     /* Pending IRQ */     /* Pending IRQ */
302     volatile m_uint32_t irq_pending,irq_check;     volatile m_uint32_t irq_pending,irq_check;
303    
# Line 320  struct cpu_ppc { Line 328  struct cpu_ppc {
328     mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,     mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
329                                       u_int cid,u_int op_code,u_int op_size,                                       u_int cid,u_int op_code,u_int op_size,
330                                       u_int op_type,m_uint64_t *data,                                       u_int op_type,m_uint64_t *data,
331                                       u_int *exc,mts32_entry_t *alt_entry);                                       mts32_entry_t *alt_entry);
332    
333     /* IRQ counters */     /* IRQ counters */
334     m_uint64_t irq_count,timer_irq_count,irq_fp_count;     m_uint64_t irq_count,timer_irq_count,irq_fp_count;
# Line 386  struct cpu_ppc { Line 394  struct cpu_ppc {
394     struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];     struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
395     m_uint32_t ppc405_pid;     m_uint32_t ppc405_pid;
396    
397       /* MPC860 IMMR register */
398       m_uint32_t mpc860_immr;
399    
400     /* FPU */     /* FPU */
401     ppc_fpu_t fpu;     ppc_fpu_t fpu;
402    
# Line 415  struct cpu_ppc { Line 426  struct cpu_ppc {
426     mips_insn_t *njm_exec_ptr;     mips_insn_t *njm_exec_ptr;
427    
428     /* Performance counter (non-JIT) */     /* Performance counter (non-JIT) */
429     m_uint64_t perf_counter;     m_uint32_t perf_counter;
430    
431     /* non-JIT mode instruction counter */     /* non-JIT mode instruction counter */
432     m_uint64_t insn_exec_count;     m_uint64_t insn_exec_count;
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