--- upstream/dynamips-0.2.7-RC1/ppc32.h	2007/10/06 16:23:47	7
+++ upstream/dynamips-0.2.8-RC1/ppc32.h	2007/10/06 16:33:40	11
@@ -26,6 +26,9 @@
 #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)
 #define PPC32_MIN_PAGE_MASK    0xFFFFF000
 
+/* Number of instructions per page */
+#define PPC32_INSN_PER_PAGE    (PPC32_MIN_PAGE_SIZE/sizeof(ppc_insn_t))
+
 /* Starting point for ROM */
 #define PPC32_ROM_START  0xfff00100
 #define PPC32_ROM_SP     0x00006000
@@ -68,6 +71,16 @@
 #define PPC32_EXC_TRACE     0x00000D00   /* Trace */
 #define PPC32_EXC_FPU_HLP   0x00000E00   /* Floating-Point Assist */
 
+/* Condition Register (CR) is accessed through 8 fields of 4 bits */
+#define ppc32_get_cr_field(n)  ((n) >> 2)
+#define ppc32_get_cr_bit(n)    (~(n) & 0x03)
+
+/* Positions of LT, GT, EQ and SO bits in CR fields */
+#define PPC32_CR_LT_BIT  3
+#define PPC32_CR_GT_BIT  2
+#define PPC32_CR_EQ_BIT  1
+#define PPC32_CR_SO_BIT  0
+
 /* CR0 (Condition Register Field 0) bits */
 #define PPC32_CR0_LT_BIT    31
 #define PPC32_CR0_LT        (1 << PPC32_CR0_LT_BIT)   /* Negative */
@@ -237,8 +250,8 @@
 typedef struct cpu_ppc cpu_ppc_t;
 
 /* Memory operation function prototype */
-typedef fastcall u_int (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
-                                       u_int reg);
+typedef fastcall void (*ppc_memop_fn)(cpu_ppc_t *cpu,m_uint32_t vaddr,
+                                      u_int reg);
 
 /* BAT type indexes */
 enum {
@@ -269,6 +282,12 @@
 /* Maximum number of breakpoints */
 #define PPC32_MAX_BREAKPOINTS  8
 
+/* zzz */
+struct ppc32_vtlb_entry {
+   m_uint32_t vaddr;
+   m_uint32_t haddr;
+};
+
 /* PowerPC CPU definition */
 struct cpu_ppc {
    /* Instruction address */
@@ -277,18 +296,23 @@
    /* General Purpose registers */
    m_uint32_t gpr[PPC32_GPR_NR];
 
+   struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];
+
    /* Pending IRQ */
    volatile m_uint32_t irq_pending,irq_check;
 
    /* XER, Condition Register, Link Register, Count Register */
-   m_uint32_t xer,cr,lr,ctr,reserve;
+   m_uint32_t xer,lr,ctr,reserve;
    m_uint32_t xer_ca;
 
+   /* Condition Register (CR) fields */
+   u_int cr_fields[8];
+
    /* MTS caches (Instruction+Data) */
    mts32_entry_t *mts_cache[2];
 
-   /* Code page translation cache */
-   ppc32_jit_tcb_t **exec_phys_map;
+   /* Code page translation cache and physical page mapping */
+   ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;
 
    /* Virtual address to physical page translation */
    fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
@@ -304,7 +328,7 @@
    mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
                                      u_int cid,u_int op_code,u_int op_size,
                                      u_int op_type,m_uint64_t *data,
-                                     u_int *exc,mts32_entry_t *alt_entry);
+                                     mts32_entry_t *alt_entry);
 
    /* IRQ counters */
    m_uint64_t irq_count,timer_irq_count,irq_fp_count;
@@ -370,6 +394,9 @@
    struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
    m_uint32_t ppc405_pid;
 
+   /* MPC860 IMMR register */
+   m_uint32_t mpc860_immr;
+
    /* FPU */
    ppc_fpu_t fpu;
 
@@ -391,15 +418,15 @@
    /* Fast memory operations use */
    u_int fast_memop;
 
-   /* IRQ idling preemption */
-   u_int irq_idle_preempt[32];
+   /* Direct block jump */
+   u_int exec_blk_direct_jump;
 
    /* Current exec page (non-JIT) info */
    m_uint64_t njm_exec_page;
    mips_insn_t *njm_exec_ptr;
 
    /* Performance counter (non-JIT) */
-   m_uint64_t perf_counter;
+   m_uint32_t perf_counter;
 
    /* non-JIT mode instruction counter */
    m_uint64_t insn_exec_count;
@@ -407,8 +434,59 @@
    /* Breakpoints */
    m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
    u_int breakpoints_enabled;
+
+   /* JIT host register allocation */
+   char *jit_hreg_seq_name;
+   int ppc_reg_map[PPC32_GPR_NR];
+   struct hreg_map *hreg_map_list,*hreg_lru;
+   struct hreg_map hreg_map[JIT_HOST_NREG];
 };
 
+#define PPC32_CR_FIELD_OFFSET(f) \
+   (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))
+
+/* Get the full CR register */
+static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
+{
+   m_uint32_t cr = 0;
+   int i;
+
+   for(i=0;i<8;i++)
+      cr |= cpu->cr_fields[i] << (28 - (i << 2));
+
+   return(cr);
+}
+
+/* Set the CR fields given a CR value */
+static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
+{
+   int i;
+
+   for(i=0;i<8;i++)
+      cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
+}
+
+/* Get a CR bit */
+static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
+{
+   m_uint32_t res;
+
+   res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
+   return(res & 0x01);
+}
+
+/* Set a CR bit */
+static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
+{
+   cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
+}
+
+/* Clear a CR bit */
+static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
+{
+   cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
+}
+
 /* Reset a PowerPC CPU */
 int ppc32_reset(cpu_ppc_t *cpu);