/[dynamips]/trunk/mips_mts.c
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upstream/dynamips-0.2.6-RC5/mips_mts.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC trunk/mips_mts.c revision 12 by dpavlin, Sat Oct 6 16:45:40 2007 UTC
# Line 5  Line 5 
5   * Template code for MTS.   * Template code for MTS.
6   */   */
7    
8  #define MTS_ENTRY  MTS_PROTO(entry_t)  #define MTS_ENTRY  MTS_NAME(entry_t)
9  #define MTS_CHUNK  MTS_PROTO(chunk_t)  #define MTS_CACHE(cpu)  ( cpu->mts_u. MTS_NAME(cache) )
10    
11  /* Forward declarations */  /* Forward declarations */
12  static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr,  static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr,
13                                               u_int op_code,u_int op_size,                                               u_int op_code,u_int op_size,
14                                               u_int op_type,m_uint64_t *data,                                               u_int op_type,m_uint64_t *data);
                                              u_int *exc);  
15    
16  static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr,  static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
17                                           m_uint32_t *phys_page);                                           m_uint32_t *phys_page);
# Line 23  int MTS_PROTO(init)(cpu_mips_t *cpu) Line 22  int MTS_PROTO(init)(cpu_mips_t *cpu)
22     size_t len;     size_t len;
23    
24     /* Initialize the cache entries to 0 (empty) */     /* Initialize the cache entries to 0 (empty) */
25     len = MTS_PROTO_UP(HASH_SIZE) * sizeof(MTS_ENTRY *);     len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY);
26     if (!(cpu->mts_cache = malloc(len)))     if (!(MTS_CACHE(cpu) = malloc(len)))
27        return(-1);        return(-1);
28    
29     memset(cpu->mts_cache,0,len);     memset(MTS_CACHE(cpu),0xFF,len);
30     cpu->mts_lookups = 0;     cpu->mts_lookups = 0;
31     cpu->mts_misses  = 0;     cpu->mts_misses  = 0;
   
    /* Reset the TLB reverse map (used for selective invalidations) */  
    memset(cpu->mts_rmap,0,(cpu->cp0.tlb_entries * sizeof(MTS_ENTRY *)));  
32     return(0);     return(0);
33  }  }
34    
35  /* Free memory used by MTS */  /* Free memory used by MTS */
36  void MTS_PROTO(shutdown)(cpu_mips_t *cpu)  void MTS_PROTO(shutdown)(cpu_mips_t *cpu)
37  {  {
    MTS_CHUNK *chunk,*next;  
    int i;  
   
    /* Reset the reverse map */  
    for(i=0;i<cpu->cp0.tlb_entries;i++)  
       cpu->mts_rmap[i] = NULL;  
   
38     /* Free the cache itself */     /* Free the cache itself */
39     free(cpu->mts_cache);     free(MTS_CACHE(cpu));
40     cpu->mts_cache = NULL;     MTS_CACHE(cpu) = NULL;
   
    /* Free the chunks */  
    for(chunk=cpu->mts_chunk_list;chunk;chunk=next) {  
       next = chunk->next;  
       free(chunk);  
    }  
   
    for(chunk=cpu->mts_chunk_free_list;chunk;chunk=next) {  
       next = chunk->next;  
       free(chunk);  
    }  
     
    cpu->mts_chunk_list = cpu->mts_chunk_free_list = NULL;  
    cpu->mts_entry_free_list = NULL;  
41  }  }
42    
43  /* Show MTS detailed information (debugging only!) */  /* Show MTS detailed information (debugging only!) */
44  void MTS_PROTO(show_stats)(cpu_mips_t *cpu)  void MTS_PROTO(show_stats)(cpu_gen_t *gen_cpu)
45  {  {
46     MTS_CHUNK *chunk;     cpu_mips_t *cpu = CPU_MIPS64(gen_cpu);
47  #if DEBUG_MTS_MAP_VIRT  #if DEBUG_MTS_MAP_VIRT
48     MTS_ENTRY *entry;     MTS_ENTRY *entry;
49     u_int i;     u_int i,count;
50  #endif  #endif
    u_int count;  
51    
52     printf("\nCPU%u: MTS%d statistics:\n",cpu->id,MTS_ADDR_SIZE);     printf("\nCPU%u: MTS%d statistics:\n",cpu->gen->id,MTS_ADDR_SIZE);
   
    printf("   Total lookups: %llu, misses: %llu, efficiency: %g%%\n",  
           cpu->mts_lookups, cpu->mts_misses,  
           100 - ((double)(cpu->mts_misses*100)/  
                  (double)cpu->mts_lookups));  
53    
54  #if DEBUG_MTS_MAP_VIRT  #if DEBUG_MTS_MAP_VIRT
55     /* Valid hash entries */     /* Valid hash entries */
56     for(count=0,i=0;i<MTS_PROTO_UP(HASH_SIZE);i++) {     for(count=0,i=0;i<MTS_NAME_UP(HASH_SIZE);i++) {
57        if ((entry = cpu->mts_cache[i]) != NULL) {        entry = &(MTS_CACHE(cpu)[i]);
58           printf("    %4u: entry=%p, start=0x%16.16llx, "  
59                  "len=0x%8.8x, action=0x%8.8llx\n",        if (!(entry->gvpa & MTS_INV_ENTRY_MASK)) {
60                  i,entry,(m_uint64_t)entry->start,entry->mask,           printf("    %4u: vaddr=0x%8.8llx, paddr=0x%8.8llx, hpa=%p\n",
61                  (m_uint64_t)entry->action);                  i,(m_uint64_t)entry->gvpa,(m_uint64_t)entry->gppa,
62                    (void *)entry->hpa);
63           count++;           count++;
64        }        }
65     }     }
66    
67     printf("   %u/%u valid hash entries.\n",count,MTS_PROTO_UP(HASH_SIZE));     printf("   %u/%u valid hash entries.\n",count,MTS_NAME_UP(HASH_SIZE));
68  #endif  #endif
69    
70     /* Number of chunks */     printf("   Total lookups: %llu, misses: %llu, efficiency: %g%%\n",
71     for(count=0,chunk=cpu->mts_chunk_list;chunk;chunk=chunk->next)            cpu->mts_lookups, cpu->mts_misses,
72        count++;            100 - ((double)(cpu->mts_misses*100)/
73                     (double)cpu->mts_lookups));
    printf("   Number of chunks: %u\n",count);  
   
 #if DEBUG_MTS_MAP_VIRT  
    /* Reverse map */  
    for(i=0;i<MIPS64_TLB_MAX_ENTRIES;i++) {  
       for(count=0,entry=cpu->mts_rmap[i];entry;entry=entry->next)  
          count++;  
   
       if (count > 0)  
          printf("   tlb_rmap[%u]: %u entries\n",i,count);  
    }  
 #endif  
 }  
   
 /* Allocate a new chunk */  
 static int MTS_PROTO(alloc_chunk)(cpu_mips_t *cpu)  
 {  
    MTS_CHUNK *chunk;  
   
    /* Try the free list first, then use standard allocation procedure */  
    if ((chunk = cpu->mts_chunk_free_list) != NULL) {  
       cpu->mts_chunk_free_list = chunk->next;  
    } else {  
       if (!(chunk = malloc(sizeof(*chunk))))  
          return(-1);  
    }  
   
    chunk->count = 0;  
    chunk->next = cpu->mts_chunk_list;  
    cpu->mts_chunk_list = chunk;  
    return(0);  
 }  
   
 /* Allocate a new entry */  
 static MTS_ENTRY *MTS_PROTO(alloc_entry)(cpu_mips_t *cpu)  
 {  
    MTS_CHUNK *chunk = cpu->mts_chunk_list;  
    MTS_ENTRY *entry;  
   
    /* First, try to allocate the entry from the free list */  
    if ((entry = cpu->mts_entry_free_list) != NULL) {  
       cpu->mts_entry_free_list = ((MTS_ENTRY *)cpu->mts_entry_free_list)->next;  
       return entry;  
    }  
   
    /* A new chunk is required */  
    if (!chunk || (chunk->count == MTS_PROTO_UP(CHUNK_SIZE))) {  
       if (MTS_PROTO(alloc_chunk)(cpu) == -1)  
          return NULL;  
   
       chunk = cpu->mts_chunk_list;  
    }  
   
    entry = &chunk->entry[chunk->count];  
    chunk->count++;  
    return entry;  
74  }  }
75    
76  /* Invalidate the complete MTS cache */  /* Invalidate the complete MTS cache */
77  void MTS_PROTO(invalidate_cache)(cpu_mips_t *cpu)  void MTS_PROTO(invalidate_cache)(cpu_mips_t *cpu)
78  {  {
    MTS_CHUNK *chunk;  
79     size_t len;     size_t len;
    u_int i;  
   
    len = MTS_PROTO_UP(HASH_SIZE) * sizeof(MTS_ENTRY *);  
    memset(cpu->mts_cache,0,len);  
   
    /* Move all chunks to the free list */  
    while((chunk = cpu->mts_chunk_list) != NULL) {  
       cpu->mts_chunk_list = chunk->next;  
       chunk->next = cpu->mts_chunk_free_list;  
       cpu->mts_chunk_free_list = chunk;  
    }  
80    
81     /* Reset the free list of entries (since they are located in chunks) */     len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY);
82     cpu->mts_entry_free_list = NULL;     memset(MTS_CACHE(cpu),0xFF,len);
   
    /* Reset the reverse map */  
    for(i=0;i<cpu->cp0.tlb_entries;i++)  
       cpu->mts_rmap[i] = NULL;  
83  }  }
84    
85  /* Invalidate partially the MTS cache, given a TLB entry index */  /* Invalidate partially the MTS cache, given a TLB entry index */
86  void MTS_PROTO(invalidate_tlb_entry)(cpu_mips_t *cpu,u_int tlb_index)  void MTS_PROTO(invalidate_tlb_entry)(cpu_mips_t *cpu,u_int tlb_index)
87  {  {
88     MTS_ENTRY *entry;     MTS_PROTO(invalidate_cache)(cpu);
   
    for(entry=cpu->mts_rmap[tlb_index];entry;entry=entry->next) {  
       *(entry->pself) = NULL;  
       if (!entry->next) {  
          entry->next = cpu->mts_entry_free_list;  
          break;  
       }  
    }  
   
    cpu->mts_entry_free_list = cpu->mts_rmap[tlb_index];  
    cpu->mts_rmap[tlb_index] = NULL;  
89  }  }
90    
91  /*  /*
# Line 206  void MTS_PROTO(invalidate_tlb_entry)(cpu Line 93  void MTS_PROTO(invalidate_tlb_entry)(cpu
93   *   *
94   * It is NOT inlined since it triggers a GCC bug on my config (x86, GCC 3.3.5)   * It is NOT inlined since it triggers a GCC bug on my config (x86, GCC 3.3.5)
95   */   */
96  static no_inline int MTS_PROTO(map)(cpu_mips_t *cpu,m_uint64_t vaddr,  static no_inline MTS_ENTRY *
97                                      mts_map_t *map,MTS_ENTRY *entry)  MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_type,mts_map_t *map,
98                   MTS_ENTRY *entry,MTS_ENTRY *alt_entry)
99  {  {
100     struct vdevice *dev;     struct vdevice *dev;
101     m_uint64_t lk_addr;     m_uint32_t offset;
102     m_uint32_t poffset;     m_iptr_t host_ptr;
103       int cow;
104     lk_addr = map->paddr + (vaddr - map->vaddr);  
105       if (!(dev = dev_lookup(cpu->vm,map->paddr,map->cached)))
106          return NULL;
107    
108       if (dev->flags & VDEVICE_FLAG_SPARSE) {
109          host_ptr = dev_sparse_get_host_addr(cpu->vm,dev,map->paddr,op_type,&cow);
110    
111          entry->gvpa  = map->vaddr;
112          entry->gppa  = map->paddr;
113          entry->hpa   = host_ptr;
114          entry->flags = (cow) ? MTS_FLAG_COW : 0;
115          return entry;
116       }
117    
118     if (!(dev = dev_lookup(cpu->vm,lk_addr,map->cached)))     if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) {
119        return(FALSE);        offset = (map->paddr + map->offset) - dev->phys_addr;
120    
121     if (map->paddr > dev->phys_addr) {        /* device entries are never stored in virtual TLB */
122        poffset = map->paddr - dev->phys_addr;        alt_entry->hpa   = (dev->id << MTS_DEVID_SHIFT) + offset;
123        entry->start     = map->vaddr;        alt_entry->flags = MTS_FLAG_DEV;
124        entry->phys_page = map->paddr >> MIPS_MIN_PAGE_SHIFT;        return alt_entry;
       entry->mask      = ~((m_min(map->len,dev->phys_len - poffset)) - 1);  
       entry->action    = poffset;  
    } else {  
       poffset = dev->phys_addr - map->paddr;  
       entry->start     = map->vaddr + poffset;  
       entry->phys_page = (map->paddr + poffset) >> MIPS_MIN_PAGE_SHIFT;  
       entry->mask      = ~((m_min(map->len - poffset,dev->phys_len)) - 1);  
       entry->action    = 0;  
125     }     }
126    
127     if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP))     entry->gvpa  = map->vaddr;
128        entry->action += (dev->id << MTS_DEVID_SHIFT) | MTS_DEV_MASK;     entry->gppa  = map->paddr;
129     else     entry->hpa   = dev->host_addr + (map->paddr - dev->phys_addr);
130        entry->action += dev->host_addr;     entry->flags = 0;
131    
132     return(TRUE);     return entry;
133  }  }
134    
135  /* MTS lookup */  /* MTS lookup */
136  static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr)  static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr)
137  {  {
138     m_uint64_t data;     m_uint64_t data;
139     u_int exc;     return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ,&data));
    return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ,  
                             &data,&exc));  
140  }  }
141    
142  /* === MIPS Memory Operations ============================================= */  /* === MIPS Memory Operations ============================================= */
143    
144  /* LB: Load Byte */  /* LB: Load Byte */
145  fastcall u_int MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
146  {  {
147     m_uint64_t data;     m_uint64_t data;
148     void *haddr;     void *haddr;
    u_int exc;  
149    
150     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data);
151     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;
152     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,8);     cpu->gpr[reg] = sign_extend(data,8);
    return(exc);  
153  }  }
154    
155  /* LBU: Load Byte Unsigned */  /* LBU: Load Byte Unsigned */
156  fastcall u_int MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
157  {  {
158     m_uint64_t data;     m_uint64_t data;
159     void *haddr;     void *haddr;
    u_int exc;  
160    
161     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data);
162     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;
163     if (likely(!exc)) cpu->gpr[reg] = data & 0xff;     cpu->gpr[reg] = data & 0xff;
    return(exc);  
164  }  }
165    
166  /* LH: Load Half-Word */  /* LH: Load Half-Word */
167  fastcall u_int MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
168  {  {
169     m_uint64_t data;     m_uint64_t data;
170     void *haddr;     void *haddr;
    u_int exc;  
171    
172     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data);
173     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);
174     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,16);     cpu->gpr[reg] = sign_extend(data,16);
    return(exc);  
175  }  }
176    
177  /* LHU: Load Half-Word Unsigned */  /* LHU: Load Half-Word Unsigned */
178  fastcall u_int MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
179  {  {
180     m_uint64_t data;     m_uint64_t data;
181     void *haddr;     void *haddr;
    u_int exc;  
182    
183     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data);
184     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);
185     if (likely(!exc)) cpu->gpr[reg] = data & 0xffff;     cpu->gpr[reg] = data & 0xffff;
    return(exc);  
186  }  }
187    
188  /* LW: Load Word */  /* LW: Load Word */
189  fastcall u_int MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
190  {  {
191     m_uint64_t data;     m_uint64_t data;
192     void *haddr;     void *haddr;
    u_int exc;  
193    
194     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data);
195     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
196     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,32);     cpu->gpr[reg] = sign_extend(data,32);
    return(exc);  
197  }  }
198    
199  /* LWU: Load Word Unsigned */  /* LWU: Load Word Unsigned */
200  fastcall u_int MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
201  {  {
202     m_uint64_t data;     m_uint64_t data;
203     void *haddr;     void *haddr;
    u_int exc;  
204    
205     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data);
206     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
207     if (likely(!exc)) cpu->gpr[reg] = data & 0xffffffff;     cpu->gpr[reg] = data & 0xffffffff;
    return(exc);  
208  }  }
209    
210  /* LD: Load Double-Word */  /* LD: Load Double-Word */
211  fastcall u_int MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
212  {  {
213     m_uint64_t data;     m_uint64_t data;
214     void *haddr;     void *haddr;
    u_int exc;  
215    
216     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data);
217     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);
218     if (likely(!exc)) cpu->gpr[reg] = data;     cpu->gpr[reg] = data;
    return(exc);  
219  }  }
220    
221  /* SB: Store Byte */  /* SB: Store Byte */
222  fastcall u_int MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
223  {  {
224     m_uint64_t data;     m_uint64_t data;
225     void *haddr;     void *haddr;
    u_int exc;  
226    
227     data = cpu->gpr[reg] & 0xff;     data = cpu->gpr[reg] & 0xff;
228     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data);
229     if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data;     if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data;
    return(exc);  
230  }  }
231    
232  /* SH: Store Half-Word */  /* SH: Store Half-Word */
233  fastcall u_int MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
234  {  {
235     m_uint64_t data;     m_uint64_t data;
236     void *haddr;     void *haddr;
    u_int exc;  
237    
238     data = cpu->gpr[reg] & 0xffff;     data = cpu->gpr[reg] & 0xffff;
239     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data);
240     if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data);     if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data);
    return(exc);  
241  }  }
242    
243  /* SW: Store Word */  /* SW: Store Word */
244  fastcall u_int MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
245  {  {
246     m_uint64_t data;     m_uint64_t data;
247     void *haddr;     void *haddr;
    u_int exc;  
248    
249     data = cpu->gpr[reg] & 0xffffffff;     data = cpu->gpr[reg] & 0xffffffff;
250     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data);
251     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
252  }  }
253    
254  /* SD: Store Double-Word */  /* SD: Store Double-Word */
255  fastcall u_int MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
256  {  {
257     m_uint64_t data;     m_uint64_t data;
258     void *haddr;     void *haddr;
    u_int exc;  
259    
260     data = cpu->gpr[reg];     data = cpu->gpr[reg];
261     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data);
262     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
263  }  }
264    
265  /* LDC1: Load Double-Word To Coprocessor 1 */  /* LDC1: Load Double-Word To Coprocessor 1 */
266  fastcall u_int MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
267  {  {
268     m_uint64_t data;     m_uint64_t data;
269     void *haddr;     void *haddr;
    u_int exc;  
270    
271     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data);
272     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);
273     if (likely(!exc)) cpu->fpu.reg[reg] = data;     cpu->fpu.reg[reg] = data;
    return(exc);  
274  }  }
275    
276  /* LWL: Load Word Left */  /* LWL: Load Word Left */
277  fastcall u_int MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
278  {  {
279     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
280     m_uint64_t data;     m_uint64_t data;
281     u_int m_shift;     u_int m_shift;
282     void *haddr;     void *haddr;
    u_int exc;  
283    
284     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
285     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data);
286    
287     if (likely(haddr != NULL))     if (likely(haddr != NULL))
288        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
289    
290     if (likely(!exc)) {     m_shift = (vaddr & 0x03) << 3;
291        m_shift = (vaddr & 0x03) << 3;     r_mask = (1ULL << m_shift) - 1;
292        r_mask = (1ULL << m_shift) - 1;     data <<= m_shift;
293        data <<= m_shift;  
294       cpu->gpr[reg] &= r_mask;
295        cpu->gpr[reg] &= r_mask;     cpu->gpr[reg] |= data;
296        cpu->gpr[reg] |= data;     cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32);
       cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32);  
    }  
    return(exc);  
297  }  }
298    
299  /* LWR: Load Word Right */  /* LWR: Load Word Right */
300  fastcall u_int MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
301  {  {
302     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
303     m_uint64_t data;     m_uint64_t data;
304     u_int m_shift;     u_int m_shift;
305     void *haddr;     void *haddr;
    u_int exc;  
306    
307     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
308     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data);
309    
310     if (likely(haddr != NULL))     if (likely(haddr != NULL))
311        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
312    
313     if (likely(!exc)) {     m_shift = ((vaddr & 0x03) + 1) << 3;
314        m_shift = ((vaddr & 0x03) + 1) << 3;     r_mask = (1ULL << m_shift) - 1;
       r_mask = (1ULL << m_shift) - 1;  
315    
316        data = sign_extend(data >> (32 - m_shift),32);     data = sign_extend(data >> (32 - m_shift),32);
317        r_mask = sign_extend(r_mask,32);     r_mask = sign_extend(r_mask,32);
318    
319        cpu->gpr[reg] &= ~r_mask;     cpu->gpr[reg] &= ~r_mask;
320        cpu->gpr[reg] |= data;     cpu->gpr[reg] |= data;
    }  
    return(exc);  
321  }  }
322    
323  /* LDL: Load Double-Word Left */  /* LDL: Load Double-Word Left */
324  fastcall u_int MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
325  {  {
326     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
327     m_uint64_t data;     m_uint64_t data;
328     u_int m_shift;     u_int m_shift;
329     void *haddr;     void *haddr;
    u_int exc;  
330    
331     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
332     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data);
333    
334     if (likely(haddr != NULL))     if (likely(haddr != NULL))
335        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
336    
337     if (likely(!exc)) {     m_shift = (vaddr & 0x07) << 3;
338        m_shift = (vaddr & 0x07) << 3;     r_mask = (1ULL << m_shift) - 1;
339        r_mask = (1ULL << m_shift) - 1;     data <<= m_shift;
       data <<= m_shift;  
340    
341        cpu->gpr[reg] &= r_mask;     cpu->gpr[reg] &= r_mask;
342        cpu->gpr[reg] |= data;     cpu->gpr[reg] |= data;
    }  
    return(exc);  
343  }  }
344    
345  /* LDR: Load Double-Word Right */  /* LDR: Load Double-Word Right */
346  fastcall u_int MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
347  {  {
348     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
349     m_uint64_t data;     m_uint64_t data;
350     u_int m_shift;     u_int m_shift;
351     void *haddr;     void *haddr;
    u_int exc;  
352    
353     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
354     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data);
355    
356     if (likely(haddr != NULL))     if (likely(haddr != NULL))
357        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
358    
359     if (likely(!exc)) {     m_shift = ((vaddr & 0x07) + 1) << 3;
360        m_shift = ((vaddr & 0x07) + 1) << 3;     r_mask = (1ULL << m_shift) - 1;
361        r_mask = (1ULL << m_shift) - 1;     data >>= (64 - m_shift);
362        data >>= (64 - m_shift);    
363       cpu->gpr[reg] &= ~r_mask;
364        cpu->gpr[reg] &= ~r_mask;     cpu->gpr[reg] |= data;
       cpu->gpr[reg] |= data;  
    }  
    return(exc);  
365  }  }
366    
367  /* SWL: Store Word Left */  /* SWL: Store Word Left */
368  fastcall u_int MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
369  {  {
370     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
371     m_uint64_t data;     m_uint64_t data;
372     u_int r_shift;     u_int r_shift;
373     void *haddr;     void *haddr;
    u_int exc;  
374    
375     naddr = vaddr & ~(0x03ULL);     naddr = vaddr & ~(0x03ULL);
376     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
377    
378     if (likely(haddr != NULL))     if (likely(haddr != NULL))
379        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
# Line 536  fastcall u_int MTS_PROTO(swl)(cpu_mips_t Line 384  fastcall u_int MTS_PROTO(swl)(cpu_mips_t
384     data &= ~d_mask;     data &= ~d_mask;
385     data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift;     data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift;
386    
387     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data);
388     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
389  }  }
390    
391  /* SWR: Store Word Right */  /* SWR: Store Word Right */
392  fastcall u_int MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
393  {  {
394     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
395     m_uint64_t data;     m_uint64_t data;
396     u_int r_shift;     u_int r_shift;
397     void *haddr;     void *haddr;
    u_int exc;  
398    
399     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
400     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
401    
402     if (likely(haddr != NULL))     if (likely(haddr != NULL))
403        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
# Line 563  fastcall u_int MTS_PROTO(swr)(cpu_mips_t Line 408  fastcall u_int MTS_PROTO(swr)(cpu_mips_t
408     data &= d_mask;     data &= d_mask;
409     data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff;     data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff;
410    
411     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data);
412     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
413  }  }
414    
415  /* SDL: Store Double-Word Left */  /* SDL: Store Double-Word Left */
416  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
417  {  {
418     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
419     m_uint64_t data;     m_uint64_t data;
420     u_int r_shift;     u_int r_shift;
421     void *haddr;     void *haddr;
    u_int exc;  
422    
423     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
424     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
425    
426     if (likely(haddr != NULL))     if (likely(haddr != NULL))
427        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
# Line 590  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t Line 432  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t
432     data &= ~d_mask;     data &= ~d_mask;
433     data |= cpu->gpr[reg] >> r_shift;     data |= cpu->gpr[reg] >> r_shift;
434    
435     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data);
436     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
437  }  }
438    
439  /* SDR: Store Double-Word Right */  /* SDR: Store Double-Word Right */
440  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
441  {  {
442     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
443     m_uint64_t data;     m_uint64_t data;
444     u_int r_shift;     u_int r_shift;
445     void *haddr;     void *haddr;
    u_int exc;  
446    
447     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
448     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
449    
450     if (likely(haddr != NULL))     if (likely(haddr != NULL))
451        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
# Line 617  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t Line 456  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t
456     data &= d_mask;     data &= d_mask;
457     data |= cpu->gpr[reg] << (64 - r_shift);     data |= cpu->gpr[reg] << (64 - r_shift);
458    
459     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data);
460     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
461  }  }
462    
463  /* LL: Load Linked */  /* LL: Load Linked */
464  fastcall u_int MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
465  {  {
466     m_uint64_t data;     m_uint64_t data;
467     void *haddr;     void *haddr;
    u_int exc;  
468    
469     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data);
470     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
471    
472     if (likely(!exc)) {     cpu->gpr[reg] = sign_extend(data,32);
473        cpu->gpr[reg] = sign_extend(data,32);     cpu->ll_bit = 1;
       cpu->ll_bit = 1;  
    }  
   
    return(exc);  
474  }  }
475    
476  /* SC: Store Conditional */  /* SC: Store Conditional */
477  fastcall u_int MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
478  {  {
479     m_uint64_t data;     m_uint64_t data;
480     void *haddr;     void *haddr;
    u_int exc = 0;  
481    
482     if (cpu->ll_bit) {     if (cpu->ll_bit) {
483        data = cpu->gpr[reg] & 0xffffffff;        data = cpu->gpr[reg] & 0xffffffff;
484        haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE,        haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE,&data);
                                 &data,&exc);  
485        if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);        if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
486     }     }
487    
488     if (likely(!exc))     cpu->gpr[reg] = cpu->ll_bit;
       cpu->gpr[reg] = cpu->ll_bit;  
    return(exc);  
489  }  }
490    
491  /* SDC1: Store Double-Word from Coprocessor 1 */  /* SDC1: Store Double-Word from Coprocessor 1 */
492  fastcall u_int MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
493  {  {
494     m_uint64_t data;     m_uint64_t data;
495     void *haddr;     void *haddr;
    u_int exc;  
496    
497     data = cpu->fpu.reg[reg];     data = cpu->fpu.reg[reg];
498     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,&data);
                              &data,&exc);  
499     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
500  }  }
501    
502  /* CACHE: Cache operation */  /* CACHE: Cache operation */
503  fastcall u_int MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op)  fastcall void MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op)
504  {  {
505     struct insn_block *block;     mips64_jit_tcb_t *block;
506     m_uint32_t phys_page;     m_uint32_t pc_hash;
507    
508  #if DEBUG_CACHE  #if DEBUG_CACHE
509     cpu_log(cpu,"MTS","CACHE: PC=0x%llx, vaddr=0x%llx, cache=%u, code=%u\n",     cpu_log(cpu->gen,
510               "MTS","CACHE: PC=0x%llx, vaddr=0x%llx, cache=%u, code=%u\n",
511             cpu->pc, vaddr, op & 0x3, op >> 2);             cpu->pc, vaddr, op & 0x3, op >> 2);
512  #endif  #endif
513    
514     if (!cpu->translate(cpu,vaddr,&phys_page)) {     if (cpu->exec_blk_map) {
515        if ((phys_page < 1048576) && cpu->exec_phys_map) {        pc_hash = mips64_jit_get_pc_hash(vaddr);
516           block = cpu->exec_phys_map[phys_page];        block = cpu->exec_blk_map[pc_hash];
517    
518           if (block) {        if (block && (block->start_pc == (vaddr & MIPS_MIN_PAGE_MASK))) {
             if ((cpu->pc < block->start_pc) ||  
                 ((cpu->pc - block->start_pc) >= MIPS_MIN_PAGE_SIZE))  
             {  
519  #if DEBUG_CACHE  #if DEBUG_CACHE
520                 cpu_log(cpu,"MTS",           cpu_log(cpu->gen,"MTS",
521                         "CACHE: removing compiled page at 0x%llx, pc=0x%llx\n",                   "CACHE: removing compiled page at 0x%llx, pc=0x%llx\n",
522                         block->start_pc,cpu->pc);                   block->start_pc,cpu->pc);
523  #endif  #endif
524                 cpu->exec_phys_map[phys_page] = NULL;           cpu->exec_blk_map[pc_hash] = NULL;
525                 insn_block_free(cpu,block,TRUE);           mips64_jit_tcb_free(cpu,block,TRUE);
526              }        }
527              else        else
528              {        {
529  #if DEBUG_CACHE  #if DEBUG_CACHE
530                 cpu_log(cpu,"MTS",           cpu_log(cpu->gen,"MTS",
531                         "CACHE: trying to remove page 0x%llx with pc=0x%llx\n",                   "CACHE: trying to remove page 0x%llx with pc=0x%llx\n",
532                         block->start_pc,cpu->pc);                   vaddr, cpu->pc);
533  #endif  #endif        
             }  
          }  
534        }        }
535     }     }
   
    return(0);  
536  }  }
537    
538  /* === MTS Cache Management ============================================= */  /* === MTS Cache Management ============================================= */
# Line 734  void MTS_PROTO(api_unmap)(cpu_mips_t *cp Line 554  void MTS_PROTO(api_unmap)(cpu_mips_t *cp
554        MTS_PROTO(invalidate_cache)(cpu);        MTS_PROTO(invalidate_cache)(cpu);
555  }  }
556    
557  void MTS_PROTO(api_rebuild)(cpu_mips_t *cpu)  void MTS_PROTO(api_rebuild)(cpu_gen_t *cpu)
558  {  {
559     MTS_PROTO(invalidate_cache)(cpu);     MTS_PROTO(invalidate_cache)(CPU_MIPS64(cpu));
560  }  }
561    
562  /* ======================================================================== */  /* ======================================================================== */
# Line 753  void MTS_PROTO(init_memop_vectors)(cpu_m Line 573  void MTS_PROTO(init_memop_vectors)(cpu_m
573     /* API vectors */     /* API vectors */
574     cpu->mts_map     = MTS_PROTO(api_map);     cpu->mts_map     = MTS_PROTO(api_map);
575     cpu->mts_unmap   = MTS_PROTO(api_unmap);     cpu->mts_unmap   = MTS_PROTO(api_unmap);
    cpu->mts_rebuild = MTS_PROTO(api_rebuild);  
576    
577     /* memory lookup operation */     /* Memory lookup operation */
578     cpu->mem_op_lookup = MTS_PROTO(lookup);     cpu->mem_op_lookup = MTS_PROTO(lookup);
579    
580     /* Translation operation */     /* Translation operation */
# Line 764  void MTS_PROTO(init_memop_vectors)(cpu_m Line 583  void MTS_PROTO(init_memop_vectors)(cpu_m
583     /* Shutdown operation */     /* Shutdown operation */
584     cpu->mts_shutdown = MTS_PROTO(shutdown);     cpu->mts_shutdown = MTS_PROTO(shutdown);
585    
586       /* Rebuild MTS data structures */
587       cpu->gen->mts_rebuild = MTS_PROTO(api_rebuild);
588    
589     /* Show statistics */     /* Show statistics */
590     cpu->mts_show_stats = MTS_PROTO(show_stats);     cpu->gen->mts_show_stats = MTS_PROTO(show_stats);
591    
592     /* Load Operations */     /* Load Operations */
593     cpu->mem_op_fn[MIPS_MEMOP_LB] = MTS_PROTO(lb);     cpu->mem_op_fn[MIPS_MEMOP_LB] = MTS_PROTO(lb);
# Line 809  void MTS_PROTO(init_memop_vectors)(cpu_m Line 631  void MTS_PROTO(init_memop_vectors)(cpu_m
631  }  }
632    
633  #undef MTS_ADDR_SIZE  #undef MTS_ADDR_SIZE
634    #undef MTS_NAME
635    #undef MTS_NAME_UP
636  #undef MTS_PROTO  #undef MTS_PROTO
637  #undef MTS_PROTO_UP  #undef MTS_PROTO_UP
638  #undef MTS_ENTRY  #undef MTS_ENTRY
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