/[dynamips]/trunk/mips_mts.c
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upstream/dynamips-0.2.7/mips_mts.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/mips_mts.c revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 11  Line 11 
11  /* Forward declarations */  /* Forward declarations */
12  static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr,  static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr,
13                                               u_int op_code,u_int op_size,                                               u_int op_code,u_int op_size,
14                                               u_int op_type,m_uint64_t *data,                                               u_int op_type,m_uint64_t *data);
                                              u_int *exc);  
15    
16  static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr,  static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
17                                           m_uint32_t *phys_page);                                           m_uint32_t *phys_page);
# Line 117  MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_ Line 116  MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_
116     }     }
117    
118     if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) {     if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) {
119        offset = map->paddr - dev->phys_addr;        offset = (map->paddr + map->offset) - dev->phys_addr;
120    
121        alt_entry->gvpa  = map->vaddr;        /* device entries are never stored in virtual TLB */
       alt_entry->gppa  = map->paddr;  
122        alt_entry->hpa   = (dev->id << MTS_DEVID_SHIFT) + offset;        alt_entry->hpa   = (dev->id << MTS_DEVID_SHIFT) + offset;
123        alt_entry->flags = MTS_FLAG_DEV;        alt_entry->flags = MTS_FLAG_DEV;
124        return alt_entry;        return alt_entry;
# Line 138  MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_ Line 136  MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_
136  static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr)  static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr)
137  {  {
138     m_uint64_t data;     m_uint64_t data;
139     u_int exc;     return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ,&data));
    return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ,  
                             &data,&exc));  
140  }  }
141    
142  /* === MIPS Memory Operations ============================================= */  /* === MIPS Memory Operations ============================================= */
143    
144  /* LB: Load Byte */  /* LB: Load Byte */
145  fastcall u_int MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
146  {  {
147     m_uint64_t data;     m_uint64_t data;
148     void *haddr;     void *haddr;
    u_int exc;  
149    
150     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data);
151     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;
152     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,8);     cpu->gpr[reg] = sign_extend(data,8);
    return(exc);  
153  }  }
154    
155  /* LBU: Load Byte Unsigned */  /* LBU: Load Byte Unsigned */
156  fastcall u_int MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
157  {  {
158     m_uint64_t data;     m_uint64_t data;
159     void *haddr;     void *haddr;
    u_int exc;  
160    
161     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data);
162     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;     if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr;
163     if (likely(!exc)) cpu->gpr[reg] = data & 0xff;     cpu->gpr[reg] = data & 0xff;
    return(exc);  
164  }  }
165    
166  /* LH: Load Half-Word */  /* LH: Load Half-Word */
167  fastcall u_int MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
168  {  {
169     m_uint64_t data;     m_uint64_t data;
170     void *haddr;     void *haddr;
    u_int exc;  
171    
172     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data);
173     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);
174     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,16);     cpu->gpr[reg] = sign_extend(data,16);
    return(exc);  
175  }  }
176    
177  /* LHU: Load Half-Word Unsigned */  /* LHU: Load Half-Word Unsigned */
178  fastcall u_int MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
179  {  {
180     m_uint64_t data;     m_uint64_t data;
181     void *haddr;     void *haddr;
    u_int exc;  
182    
183     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data);
184     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr);
185     if (likely(!exc)) cpu->gpr[reg] = data & 0xffff;     cpu->gpr[reg] = data & 0xffff;
    return(exc);  
186  }  }
187    
188  /* LW: Load Word */  /* LW: Load Word */
189  fastcall u_int MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
190  {  {
191     m_uint64_t data;     m_uint64_t data;
192     void *haddr;     void *haddr;
    u_int exc;  
193    
194     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data);
195     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
196     if (likely(!exc)) cpu->gpr[reg] = sign_extend(data,32);     cpu->gpr[reg] = sign_extend(data,32);
    return(exc);  
197  }  }
198    
199  /* LWU: Load Word Unsigned */  /* LWU: Load Word Unsigned */
200  fastcall u_int MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
201  {  {
202     m_uint64_t data;     m_uint64_t data;
203     void *haddr;     void *haddr;
    u_int exc;  
204    
205     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data);
206     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
207     if (likely(!exc)) cpu->gpr[reg] = data & 0xffffffff;     cpu->gpr[reg] = data & 0xffffffff;
    return(exc);  
208  }  }
209    
210  /* LD: Load Double-Word */  /* LD: Load Double-Word */
211  fastcall u_int MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
212  {  {
213     m_uint64_t data;     m_uint64_t data;
214     void *haddr;     void *haddr;
    u_int exc;  
215    
216     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data);
217     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);
218     if (likely(!exc)) cpu->gpr[reg] = data;     cpu->gpr[reg] = data;
    return(exc);  
219  }  }
220    
221  /* SB: Store Byte */  /* SB: Store Byte */
222  fastcall u_int MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
223  {  {
224     m_uint64_t data;     m_uint64_t data;
225     void *haddr;     void *haddr;
    u_int exc;  
226    
227     data = cpu->gpr[reg] & 0xff;     data = cpu->gpr[reg] & 0xff;
228     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data);
229     if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data;     if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data;
    return(exc);  
230  }  }
231    
232  /* SH: Store Half-Word */  /* SH: Store Half-Word */
233  fastcall u_int MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
234  {  {
235     m_uint64_t data;     m_uint64_t data;
236     void *haddr;     void *haddr;
    u_int exc;  
237    
238     data = cpu->gpr[reg] & 0xffff;     data = cpu->gpr[reg] & 0xffff;
239     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data);
240     if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data);     if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data);
    return(exc);  
241  }  }
242    
243  /* SW: Store Word */  /* SW: Store Word */
244  fastcall u_int MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
245  {  {
246     m_uint64_t data;     m_uint64_t data;
247     void *haddr;     void *haddr;
    u_int exc;  
248    
249     data = cpu->gpr[reg] & 0xffffffff;     data = cpu->gpr[reg] & 0xffffffff;
250     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data);
251     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
252  }  }
253    
254  /* SD: Store Double-Word */  /* SD: Store Double-Word */
255  fastcall u_int MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
256  {  {
257     m_uint64_t data;     m_uint64_t data;
258     void *haddr;     void *haddr;
    u_int exc;  
259    
260     data = cpu->gpr[reg];     data = cpu->gpr[reg];
261     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data);
262     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
263  }  }
264    
265  /* LDC1: Load Double-Word To Coprocessor 1 */  /* LDC1: Load Double-Word To Coprocessor 1 */
266  fastcall u_int MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
267  {  {
268     m_uint64_t data;     m_uint64_t data;
269     void *haddr;     void *haddr;
    u_int exc;  
270    
271     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data);
272     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr);
273     if (likely(!exc)) cpu->fpu.reg[reg] = data;     cpu->fpu.reg[reg] = data;
    return(exc);  
274  }  }
275    
276  /* LWL: Load Word Left */  /* LWL: Load Word Left */
277  fastcall u_int MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
278  {  {
279     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
280     m_uint64_t data;     m_uint64_t data;
281     u_int m_shift;     u_int m_shift;
282     void *haddr;     void *haddr;
    u_int exc;  
283    
284     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
285     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data);
286    
287     if (likely(haddr != NULL))     if (likely(haddr != NULL))
288        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
289    
290     if (likely(!exc)) {     m_shift = (vaddr & 0x03) << 3;
291        m_shift = (vaddr & 0x03) << 3;     r_mask = (1ULL << m_shift) - 1;
292        r_mask = (1ULL << m_shift) - 1;     data <<= m_shift;
293        data <<= m_shift;  
294       cpu->gpr[reg] &= r_mask;
295        cpu->gpr[reg] &= r_mask;     cpu->gpr[reg] |= data;
296        cpu->gpr[reg] |= data;     cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32);
       cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32);  
    }  
    return(exc);  
297  }  }
298    
299  /* LWR: Load Word Right */  /* LWR: Load Word Right */
300  fastcall u_int MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
301  {  {
302     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
303     m_uint64_t data;     m_uint64_t data;
304     u_int m_shift;     u_int m_shift;
305     void *haddr;     void *haddr;
    u_int exc;  
306    
307     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
308     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data);
309    
310     if (likely(haddr != NULL))     if (likely(haddr != NULL))
311        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
312    
313     if (likely(!exc)) {     m_shift = ((vaddr & 0x03) + 1) << 3;
314        m_shift = ((vaddr & 0x03) + 1) << 3;     r_mask = (1ULL << m_shift) - 1;
       r_mask = (1ULL << m_shift) - 1;  
315    
316        data = sign_extend(data >> (32 - m_shift),32);     data = sign_extend(data >> (32 - m_shift),32);
317        r_mask = sign_extend(r_mask,32);     r_mask = sign_extend(r_mask,32);
318    
319        cpu->gpr[reg] &= ~r_mask;     cpu->gpr[reg] &= ~r_mask;
320        cpu->gpr[reg] |= data;     cpu->gpr[reg] |= data;
    }  
    return(exc);  
321  }  }
322    
323  /* LDL: Load Double-Word Left */  /* LDL: Load Double-Word Left */
324  fastcall u_int MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
325  {  {
326     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
327     m_uint64_t data;     m_uint64_t data;
328     u_int m_shift;     u_int m_shift;
329     void *haddr;     void *haddr;
    u_int exc;  
330    
331     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
332     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data);
333    
334     if (likely(haddr != NULL))     if (likely(haddr != NULL))
335        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
336    
337     if (likely(!exc)) {     m_shift = (vaddr & 0x07) << 3;
338        m_shift = (vaddr & 0x07) << 3;     r_mask = (1ULL << m_shift) - 1;
339        r_mask = (1ULL << m_shift) - 1;     data <<= m_shift;
       data <<= m_shift;  
340    
341        cpu->gpr[reg] &= r_mask;     cpu->gpr[reg] &= r_mask;
342        cpu->gpr[reg] |= data;     cpu->gpr[reg] |= data;
    }  
    return(exc);  
343  }  }
344    
345  /* LDR: Load Double-Word Right */  /* LDR: Load Double-Word Right */
346  fastcall u_int MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
347  {  {
348     m_uint64_t r_mask,naddr;     m_uint64_t r_mask,naddr;
349     m_uint64_t data;     m_uint64_t data;
350     u_int m_shift;     u_int m_shift;
351     void *haddr;     void *haddr;
    u_int exc;  
352    
353     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
354     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data);
355    
356     if (likely(haddr != NULL))     if (likely(haddr != NULL))
357        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
358    
359     if (likely(!exc)) {     m_shift = ((vaddr & 0x07) + 1) << 3;
360        m_shift = ((vaddr & 0x07) + 1) << 3;     r_mask = (1ULL << m_shift) - 1;
361        r_mask = (1ULL << m_shift) - 1;     data >>= (64 - m_shift);
362        data >>= (64 - m_shift);    
363       cpu->gpr[reg] &= ~r_mask;
364        cpu->gpr[reg] &= ~r_mask;     cpu->gpr[reg] |= data;
       cpu->gpr[reg] |= data;  
    }  
    return(exc);  
365  }  }
366    
367  /* SWL: Store Word Left */  /* SWL: Store Word Left */
368  fastcall u_int MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
369  {  {
370     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
371     m_uint64_t data;     m_uint64_t data;
372     u_int r_shift;     u_int r_shift;
373     void *haddr;     void *haddr;
    u_int exc;  
374    
375     naddr = vaddr & ~(0x03ULL);     naddr = vaddr & ~(0x03ULL);
376     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
377    
378     if (likely(haddr != NULL))     if (likely(haddr != NULL))
379        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
# Line 430  fastcall u_int MTS_PROTO(swl)(cpu_mips_t Line 384  fastcall u_int MTS_PROTO(swl)(cpu_mips_t
384     data &= ~d_mask;     data &= ~d_mask;
385     data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift;     data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift;
386    
387     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data);
388     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
389  }  }
390    
391  /* SWR: Store Word Right */  /* SWR: Store Word Right */
392  fastcall u_int MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
393  {  {
394     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
395     m_uint64_t data;     m_uint64_t data;
396     u_int r_shift;     u_int r_shift;
397     void *haddr;     void *haddr;
    u_int exc;  
398    
399     naddr = vaddr & ~(0x03);     naddr = vaddr & ~(0x03);
400     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
401    
402     if (likely(haddr != NULL))     if (likely(haddr != NULL))
403        data = vmtoh32(*(m_uint32_t *)haddr);        data = vmtoh32(*(m_uint32_t *)haddr);
# Line 457  fastcall u_int MTS_PROTO(swr)(cpu_mips_t Line 408  fastcall u_int MTS_PROTO(swr)(cpu_mips_t
408     data &= d_mask;     data &= d_mask;
409     data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff;     data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff;
410    
411     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data);
412     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);     if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
    return(exc);  
413  }  }
414    
415  /* SDL: Store Double-Word Left */  /* SDL: Store Double-Word Left */
416  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
417  {  {
418     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
419     m_uint64_t data;     m_uint64_t data;
420     u_int r_shift;     u_int r_shift;
421     void *haddr;     void *haddr;
    u_int exc;  
422    
423     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
424     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
425    
426     if (likely(haddr != NULL))     if (likely(haddr != NULL))
427        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
# Line 484  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t Line 432  fastcall u_int MTS_PROTO(sdl)(cpu_mips_t
432     data &= ~d_mask;     data &= ~d_mask;
433     data |= cpu->gpr[reg] >> r_shift;     data |= cpu->gpr[reg] >> r_shift;
434    
435     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data);
436     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
437  }  }
438    
439  /* SDR: Store Double-Word Right */  /* SDR: Store Double-Word Right */
440  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
441  {  {
442     m_uint64_t d_mask,naddr;     m_uint64_t d_mask,naddr;
443     m_uint64_t data;     m_uint64_t data;
444     u_int r_shift;     u_int r_shift;
445     void *haddr;     void *haddr;
    u_int exc;  
446    
447     naddr = vaddr & ~(0x07);     naddr = vaddr & ~(0x07);
448     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data);
    if (unlikely(exc)) return(exc);  
449    
450     if (likely(haddr != NULL))     if (likely(haddr != NULL))
451        data = vmtoh64(*(m_uint64_t *)haddr);        data = vmtoh64(*(m_uint64_t *)haddr);
# Line 511  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t Line 456  fastcall u_int MTS_PROTO(sdr)(cpu_mips_t
456     data &= d_mask;     data &= d_mask;
457     data |= cpu->gpr[reg] << (64 - r_shift);     data |= cpu->gpr[reg] << (64 - r_shift);
458    
459     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data,&exc);     haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data);
460     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
461  }  }
462    
463  /* LL: Load Linked */  /* LL: Load Linked */
464  fastcall u_int MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
465  {  {
466     m_uint64_t data;     m_uint64_t data;
467     void *haddr;     void *haddr;
    u_int exc;  
468    
469     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data,&exc);     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data);
470     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);     if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr);
471    
472     if (likely(!exc)) {     cpu->gpr[reg] = sign_extend(data,32);
473        cpu->gpr[reg] = sign_extend(data,32);     cpu->ll_bit = 1;
       cpu->ll_bit = 1;  
    }  
   
    return(exc);  
474  }  }
475    
476  /* SC: Store Conditional */  /* SC: Store Conditional */
477  fastcall u_int MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
478  {  {
479     m_uint64_t data;     m_uint64_t data;
480     void *haddr;     void *haddr;
    u_int exc = 0;  
481    
482     if (cpu->ll_bit) {     if (cpu->ll_bit) {
483        data = cpu->gpr[reg] & 0xffffffff;        data = cpu->gpr[reg] & 0xffffffff;
484        haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE,        haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE,&data);
                                 &data,&exc);  
485        if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);        if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data);
486     }     }
487    
488     if (likely(!exc))     cpu->gpr[reg] = cpu->ll_bit;
       cpu->gpr[reg] = cpu->ll_bit;  
    return(exc);  
489  }  }
490    
491  /* SDC1: Store Double-Word from Coprocessor 1 */  /* SDC1: Store Double-Word from Coprocessor 1 */
492  fastcall u_int MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)  fastcall void MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg)
493  {  {
494     m_uint64_t data;     m_uint64_t data;
495     void *haddr;     void *haddr;
    u_int exc;  
496    
497     data = cpu->fpu.reg[reg];     data = cpu->fpu.reg[reg];
498     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,     haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,&data);
                              &data,&exc);  
499     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);     if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);
    return(exc);  
500  }  }
501    
502  /* CACHE: Cache operation */  /* CACHE: Cache operation */
503  fastcall u_int MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op)  fastcall void MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op)
504  {  {
505     mips64_jit_tcb_t *block;     mips64_jit_tcb_t *block;
506     m_uint32_t pc_hash;     m_uint32_t pc_hash;
# Line 598  fastcall u_int MTS_PROTO(cache)(cpu_mips Line 530  fastcall u_int MTS_PROTO(cache)(cpu_mips
530           cpu_log(cpu->gen,"MTS",           cpu_log(cpu->gen,"MTS",
531                   "CACHE: trying to remove page 0x%llx with pc=0x%llx\n",                   "CACHE: trying to remove page 0x%llx with pc=0x%llx\n",
532                   vaddr, cpu->pc);                   vaddr, cpu->pc);
533  #endif  #endif        
           
534        }        }
535     }     }
   
    return(0);  
536  }  }
537    
538  /* === MTS Cache Management ============================================= */  /* === MTS Cache Management ============================================= */
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