1 |
/* |
2 |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
4 |
* |
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* Template code for MTS. |
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*/ |
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|
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#define MTS_ENTRY MTS_NAME(entry_t) |
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#define MTS_CACHE(cpu) ( cpu->mts_u. MTS_NAME(cache) ) |
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|
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/* Forward declarations */ |
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static forced_inline void *MTS_PROTO(access)(cpu_mips_t *cpu,m_uint64_t vaddr, |
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u_int op_code,u_int op_size, |
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u_int op_type,m_uint64_t *data); |
15 |
|
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static fastcall int MTS_PROTO(translate)(cpu_mips_t *cpu,m_uint64_t vaddr, |
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m_uint32_t *phys_page); |
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|
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/* Initialize the MTS subsystem for the specified CPU */ |
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int MTS_PROTO(init)(cpu_mips_t *cpu) |
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{ |
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size_t len; |
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|
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/* Initialize the cache entries to 0 (empty) */ |
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len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY); |
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if (!(MTS_CACHE(cpu) = malloc(len))) |
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return(-1); |
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|
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memset(MTS_CACHE(cpu),0xFF,len); |
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cpu->mts_lookups = 0; |
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cpu->mts_misses = 0; |
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return(0); |
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} |
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|
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/* Free memory used by MTS */ |
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void MTS_PROTO(shutdown)(cpu_mips_t *cpu) |
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{ |
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/* Free the cache itself */ |
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free(MTS_CACHE(cpu)); |
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MTS_CACHE(cpu) = NULL; |
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} |
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|
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/* Show MTS detailed information (debugging only!) */ |
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void MTS_PROTO(show_stats)(cpu_gen_t *gen_cpu) |
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{ |
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cpu_mips_t *cpu = CPU_MIPS64(gen_cpu); |
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#if DEBUG_MTS_MAP_VIRT |
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MTS_ENTRY *entry; |
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u_int i,count; |
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#endif |
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|
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printf("\nCPU%u: MTS%d statistics:\n",cpu->gen->id,MTS_ADDR_SIZE); |
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|
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#if DEBUG_MTS_MAP_VIRT |
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/* Valid hash entries */ |
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for(count=0,i=0;i<MTS_NAME_UP(HASH_SIZE);i++) { |
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entry = &(MTS_CACHE(cpu)[i]); |
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|
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if (!(entry->gvpa & MTS_INV_ENTRY_MASK)) { |
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printf(" %4u: vaddr=0x%8.8llx, paddr=0x%8.8llx, hpa=%p\n", |
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i,(m_uint64_t)entry->gvpa,(m_uint64_t)entry->gppa, |
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(void *)entry->hpa); |
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count++; |
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} |
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} |
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|
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printf(" %u/%u valid hash entries.\n",count,MTS_NAME_UP(HASH_SIZE)); |
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#endif |
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|
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printf(" Total lookups: %llu, misses: %llu, efficiency: %g%%\n", |
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cpu->mts_lookups, cpu->mts_misses, |
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100 - ((double)(cpu->mts_misses*100)/ |
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(double)cpu->mts_lookups)); |
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} |
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|
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/* Invalidate the complete MTS cache */ |
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void MTS_PROTO(invalidate_cache)(cpu_mips_t *cpu) |
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{ |
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size_t len; |
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|
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len = MTS_NAME_UP(HASH_SIZE) * sizeof(MTS_ENTRY); |
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memset(MTS_CACHE(cpu),0xFF,len); |
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} |
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|
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/* Invalidate partially the MTS cache, given a TLB entry index */ |
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void MTS_PROTO(invalidate_tlb_entry)(cpu_mips_t *cpu,u_int tlb_index) |
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{ |
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MTS_PROTO(invalidate_cache)(cpu); |
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} |
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|
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/* |
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* MTS mapping. |
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* |
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* It is NOT inlined since it triggers a GCC bug on my config (x86, GCC 3.3.5) |
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*/ |
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static no_inline MTS_ENTRY * |
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MTS_PROTO(map)(cpu_mips_t *cpu,u_int op_type,mts_map_t *map, |
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MTS_ENTRY *entry,MTS_ENTRY *alt_entry) |
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{ |
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struct vdevice *dev; |
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m_uint32_t offset; |
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m_iptr_t host_ptr; |
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int cow; |
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|
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if (!(dev = dev_lookup(cpu->vm,map->paddr,map->cached))) |
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return NULL; |
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|
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if (dev->flags & VDEVICE_FLAG_SPARSE) { |
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host_ptr = dev_sparse_get_host_addr(cpu->vm,dev,map->paddr,op_type,&cow); |
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|
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entry->gvpa = map->vaddr; |
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entry->gppa = map->paddr; |
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entry->hpa = host_ptr; |
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entry->flags = (cow) ? MTS_FLAG_COW : 0; |
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return entry; |
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} |
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|
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if (!dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) { |
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offset = (map->paddr + map->offset) - dev->phys_addr; |
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|
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/* device entries are never stored in virtual TLB */ |
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alt_entry->hpa = (dev->id << MTS_DEVID_SHIFT) + offset; |
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alt_entry->flags = MTS_FLAG_DEV; |
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return alt_entry; |
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} |
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|
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entry->gvpa = map->vaddr; |
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entry->gppa = map->paddr; |
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entry->hpa = dev->host_addr + (map->paddr - dev->phys_addr); |
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entry->flags = 0; |
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|
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return entry; |
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} |
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|
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/* MTS lookup */ |
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static void *MTS_PROTO(lookup)(cpu_mips_t *cpu,m_uint64_t vaddr) |
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{ |
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m_uint64_t data; |
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return(MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LOOKUP,4,MTS_READ,&data)); |
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} |
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|
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/* === MIPS Memory Operations ============================================= */ |
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|
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/* LB: Load Byte */ |
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fastcall void MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LB,1,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr; |
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cpu->gpr[reg] = sign_extend(data,8); |
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} |
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|
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/* LBU: Load Byte Unsigned */ |
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fastcall void MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LBU,1,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = *(m_uint8_t *)haddr; |
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cpu->gpr[reg] = data & 0xff; |
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} |
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|
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/* LH: Load Half-Word */ |
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fastcall void MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LH,2,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr); |
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cpu->gpr[reg] = sign_extend(data,16); |
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} |
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|
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/* LHU: Load Half-Word Unsigned */ |
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fastcall void MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LHU,2,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = vmtoh16(*(m_uint16_t *)haddr); |
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cpu->gpr[reg] = data & 0xffff; |
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} |
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|
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/* LW: Load Word */ |
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fastcall void MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LW,4,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
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cpu->gpr[reg] = sign_extend(data,32); |
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} |
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|
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/* LWU: Load Word Unsigned */ |
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fastcall void MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LWU,4,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
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cpu->gpr[reg] = data & 0xffffffff; |
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} |
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|
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/* LD: Load Double-Word */ |
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fastcall void MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
215 |
|
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LD,8,MTS_READ,&data); |
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if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr); |
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cpu->gpr[reg] = data; |
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} |
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|
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/* SB: Store Byte */ |
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fastcall void MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
226 |
|
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data = cpu->gpr[reg] & 0xff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SB,1,MTS_WRITE,&data); |
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if (likely(haddr != NULL)) *(m_uint8_t *)haddr = data; |
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} |
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|
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/* SH: Store Half-Word */ |
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fastcall void MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
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|
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data = cpu->gpr[reg] & 0xffff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SH,2,MTS_WRITE,&data); |
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if (likely(haddr != NULL)) *(m_uint16_t *)haddr = htovm16(data); |
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} |
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|
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/* SW: Store Word */ |
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fastcall void MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t data; |
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void *haddr; |
248 |
|
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data = cpu->gpr[reg] & 0xffffffff; |
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haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SW,4,MTS_WRITE,&data); |
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if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
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} |
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|
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/* SD: Store Double-Word */ |
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fastcall void MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
256 |
{ |
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m_uint64_t data; |
258 |
void *haddr; |
259 |
|
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data = cpu->gpr[reg]; |
261 |
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SD,8,MTS_WRITE,&data); |
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if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
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} |
264 |
|
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/* LDC1: Load Double-Word To Coprocessor 1 */ |
266 |
fastcall void MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
267 |
{ |
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m_uint64_t data; |
269 |
void *haddr; |
270 |
|
271 |
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LDC1,8,MTS_READ,&data); |
272 |
if (likely(haddr != NULL)) data = vmtoh64(*(m_uint64_t *)haddr); |
273 |
cpu->fpu.reg[reg] = data; |
274 |
} |
275 |
|
276 |
/* LWL: Load Word Left */ |
277 |
fastcall void MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
278 |
{ |
279 |
m_uint64_t r_mask,naddr; |
280 |
m_uint64_t data; |
281 |
u_int m_shift; |
282 |
void *haddr; |
283 |
|
284 |
naddr = vaddr & ~(0x03); |
285 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWL,4,MTS_READ,&data); |
286 |
|
287 |
if (likely(haddr != NULL)) |
288 |
data = vmtoh32(*(m_uint32_t *)haddr); |
289 |
|
290 |
m_shift = (vaddr & 0x03) << 3; |
291 |
r_mask = (1ULL << m_shift) - 1; |
292 |
data <<= m_shift; |
293 |
|
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cpu->gpr[reg] &= r_mask; |
295 |
cpu->gpr[reg] |= data; |
296 |
cpu->gpr[reg] = sign_extend(cpu->gpr[reg],32); |
297 |
} |
298 |
|
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/* LWR: Load Word Right */ |
300 |
fastcall void MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
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{ |
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m_uint64_t r_mask,naddr; |
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m_uint64_t data; |
304 |
u_int m_shift; |
305 |
void *haddr; |
306 |
|
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naddr = vaddr & ~(0x03); |
308 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LWR,4,MTS_READ,&data); |
309 |
|
310 |
if (likely(haddr != NULL)) |
311 |
data = vmtoh32(*(m_uint32_t *)haddr); |
312 |
|
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m_shift = ((vaddr & 0x03) + 1) << 3; |
314 |
r_mask = (1ULL << m_shift) - 1; |
315 |
|
316 |
data = sign_extend(data >> (32 - m_shift),32); |
317 |
r_mask = sign_extend(r_mask,32); |
318 |
|
319 |
cpu->gpr[reg] &= ~r_mask; |
320 |
cpu->gpr[reg] |= data; |
321 |
} |
322 |
|
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/* LDL: Load Double-Word Left */ |
324 |
fastcall void MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
325 |
{ |
326 |
m_uint64_t r_mask,naddr; |
327 |
m_uint64_t data; |
328 |
u_int m_shift; |
329 |
void *haddr; |
330 |
|
331 |
naddr = vaddr & ~(0x07); |
332 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDL,8,MTS_READ,&data); |
333 |
|
334 |
if (likely(haddr != NULL)) |
335 |
data = vmtoh64(*(m_uint64_t *)haddr); |
336 |
|
337 |
m_shift = (vaddr & 0x07) << 3; |
338 |
r_mask = (1ULL << m_shift) - 1; |
339 |
data <<= m_shift; |
340 |
|
341 |
cpu->gpr[reg] &= r_mask; |
342 |
cpu->gpr[reg] |= data; |
343 |
} |
344 |
|
345 |
/* LDR: Load Double-Word Right */ |
346 |
fastcall void MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
347 |
{ |
348 |
m_uint64_t r_mask,naddr; |
349 |
m_uint64_t data; |
350 |
u_int m_shift; |
351 |
void *haddr; |
352 |
|
353 |
naddr = vaddr & ~(0x07); |
354 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_LDR,8,MTS_READ,&data); |
355 |
|
356 |
if (likely(haddr != NULL)) |
357 |
data = vmtoh64(*(m_uint64_t *)haddr); |
358 |
|
359 |
m_shift = ((vaddr & 0x07) + 1) << 3; |
360 |
r_mask = (1ULL << m_shift) - 1; |
361 |
data >>= (64 - m_shift); |
362 |
|
363 |
cpu->gpr[reg] &= ~r_mask; |
364 |
cpu->gpr[reg] |= data; |
365 |
} |
366 |
|
367 |
/* SWL: Store Word Left */ |
368 |
fastcall void MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
369 |
{ |
370 |
m_uint64_t d_mask,naddr; |
371 |
m_uint64_t data; |
372 |
u_int r_shift; |
373 |
void *haddr; |
374 |
|
375 |
naddr = vaddr & ~(0x03ULL); |
376 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_READ,&data); |
377 |
|
378 |
if (likely(haddr != NULL)) |
379 |
data = vmtoh32(*(m_uint32_t *)haddr); |
380 |
|
381 |
r_shift = (vaddr & 0x03) << 3; |
382 |
d_mask = 0xffffffff >> r_shift; |
383 |
|
384 |
data &= ~d_mask; |
385 |
data |= (cpu->gpr[reg] & 0xffffffff) >> r_shift; |
386 |
|
387 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWL,4,MTS_WRITE,&data); |
388 |
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
389 |
} |
390 |
|
391 |
/* SWR: Store Word Right */ |
392 |
fastcall void MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
393 |
{ |
394 |
m_uint64_t d_mask,naddr; |
395 |
m_uint64_t data; |
396 |
u_int r_shift; |
397 |
void *haddr; |
398 |
|
399 |
naddr = vaddr & ~(0x03); |
400 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_READ,&data); |
401 |
|
402 |
if (likely(haddr != NULL)) |
403 |
data = vmtoh32(*(m_uint32_t *)haddr); |
404 |
|
405 |
r_shift = ((vaddr & 0x03) + 1) << 3; |
406 |
d_mask = 0xffffffff >> r_shift; |
407 |
|
408 |
data &= d_mask; |
409 |
data |= (cpu->gpr[reg] << (32 - r_shift)) & 0xffffffff; |
410 |
|
411 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SWR,4,MTS_WRITE,&data); |
412 |
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
413 |
} |
414 |
|
415 |
/* SDL: Store Double-Word Left */ |
416 |
fastcall void MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
417 |
{ |
418 |
m_uint64_t d_mask,naddr; |
419 |
m_uint64_t data; |
420 |
u_int r_shift; |
421 |
void *haddr; |
422 |
|
423 |
naddr = vaddr & ~(0x07); |
424 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_READ,&data); |
425 |
|
426 |
if (likely(haddr != NULL)) |
427 |
data = vmtoh64(*(m_uint64_t *)haddr); |
428 |
|
429 |
r_shift = (vaddr & 0x07) << 3; |
430 |
d_mask = 0xffffffffffffffffULL >> r_shift; |
431 |
|
432 |
data &= ~d_mask; |
433 |
data |= cpu->gpr[reg] >> r_shift; |
434 |
|
435 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDL,8,MTS_WRITE,&data); |
436 |
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
437 |
} |
438 |
|
439 |
/* SDR: Store Double-Word Right */ |
440 |
fastcall void MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
441 |
{ |
442 |
m_uint64_t d_mask,naddr; |
443 |
m_uint64_t data; |
444 |
u_int r_shift; |
445 |
void *haddr; |
446 |
|
447 |
naddr = vaddr & ~(0x07); |
448 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_READ,&data); |
449 |
|
450 |
if (likely(haddr != NULL)) |
451 |
data = vmtoh64(*(m_uint64_t *)haddr); |
452 |
|
453 |
r_shift = ((vaddr & 0x07) + 1) << 3; |
454 |
d_mask = 0xffffffffffffffffULL >> r_shift; |
455 |
|
456 |
data &= d_mask; |
457 |
data |= cpu->gpr[reg] << (64 - r_shift); |
458 |
|
459 |
haddr = MTS_PROTO(access)(cpu,naddr,MIPS_MEMOP_SDR,8,MTS_WRITE,&data); |
460 |
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
461 |
} |
462 |
|
463 |
/* LL: Load Linked */ |
464 |
fastcall void MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
465 |
{ |
466 |
m_uint64_t data; |
467 |
void *haddr; |
468 |
|
469 |
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_LL,4,MTS_READ,&data); |
470 |
if (likely(haddr != NULL)) data = vmtoh32(*(m_uint32_t *)haddr); |
471 |
|
472 |
cpu->gpr[reg] = sign_extend(data,32); |
473 |
cpu->ll_bit = 1; |
474 |
} |
475 |
|
476 |
/* SC: Store Conditional */ |
477 |
fastcall void MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
478 |
{ |
479 |
m_uint64_t data; |
480 |
void *haddr; |
481 |
|
482 |
if (cpu->ll_bit) { |
483 |
data = cpu->gpr[reg] & 0xffffffff; |
484 |
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SC,4,MTS_WRITE,&data); |
485 |
if (likely(haddr != NULL)) *(m_uint32_t *)haddr = htovm32(data); |
486 |
} |
487 |
|
488 |
cpu->gpr[reg] = cpu->ll_bit; |
489 |
} |
490 |
|
491 |
/* SDC1: Store Double-Word from Coprocessor 1 */ |
492 |
fastcall void MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) |
493 |
{ |
494 |
m_uint64_t data; |
495 |
void *haddr; |
496 |
|
497 |
data = cpu->fpu.reg[reg]; |
498 |
haddr = MTS_PROTO(access)(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,&data); |
499 |
if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data); |
500 |
} |
501 |
|
502 |
/* CACHE: Cache operation */ |
503 |
fastcall void MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op) |
504 |
{ |
505 |
mips64_jit_tcb_t *block; |
506 |
m_uint32_t pc_hash; |
507 |
|
508 |
#if DEBUG_CACHE |
509 |
cpu_log(cpu->gen, |
510 |
"MTS","CACHE: PC=0x%llx, vaddr=0x%llx, cache=%u, code=%u\n", |
511 |
cpu->pc, vaddr, op & 0x3, op >> 2); |
512 |
#endif |
513 |
|
514 |
if (cpu->exec_blk_map) { |
515 |
pc_hash = mips64_jit_get_pc_hash(vaddr); |
516 |
block = cpu->exec_blk_map[pc_hash]; |
517 |
|
518 |
if (block && (block->start_pc == (vaddr & MIPS_MIN_PAGE_MASK))) { |
519 |
#if DEBUG_CACHE |
520 |
cpu_log(cpu->gen,"MTS", |
521 |
"CACHE: removing compiled page at 0x%llx, pc=0x%llx\n", |
522 |
block->start_pc,cpu->pc); |
523 |
#endif |
524 |
cpu->exec_blk_map[pc_hash] = NULL; |
525 |
mips64_jit_tcb_free(cpu,block,TRUE); |
526 |
} |
527 |
else |
528 |
{ |
529 |
#if DEBUG_CACHE |
530 |
cpu_log(cpu->gen,"MTS", |
531 |
"CACHE: trying to remove page 0x%llx with pc=0x%llx\n", |
532 |
vaddr, cpu->pc); |
533 |
#endif |
534 |
} |
535 |
} |
536 |
} |
537 |
|
538 |
/* === MTS Cache Management ============================================= */ |
539 |
|
540 |
/* MTS map/unmap/rebuild "API" functions */ |
541 |
void MTS_PROTO(api_map)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint64_t paddr, |
542 |
m_uint32_t len,int cache_access,int tlb_index) |
543 |
{ |
544 |
/* nothing to do, the cache will be filled on-the-fly */ |
545 |
} |
546 |
|
547 |
void MTS_PROTO(api_unmap)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len, |
548 |
m_uint32_t val,int tlb_index) |
549 |
{ |
550 |
/* Invalidate the TLB entry or the full cache if no index is specified */ |
551 |
if (tlb_index != -1) |
552 |
MTS_PROTO(invalidate_tlb_entry)(cpu,tlb_index); |
553 |
else |
554 |
MTS_PROTO(invalidate_cache)(cpu); |
555 |
} |
556 |
|
557 |
void MTS_PROTO(api_rebuild)(cpu_gen_t *cpu) |
558 |
{ |
559 |
MTS_PROTO(invalidate_cache)(CPU_MIPS64(cpu)); |
560 |
} |
561 |
|
562 |
/* ======================================================================== */ |
563 |
|
564 |
/* Initialize memory access vectors */ |
565 |
void MTS_PROTO(init_memop_vectors)(cpu_mips_t *cpu) |
566 |
{ |
567 |
/* XXX TODO: |
568 |
* - LD/SD forbidden in Supervisor/User modes with 32-bit addresses. |
569 |
*/ |
570 |
|
571 |
cpu->addr_mode = MTS_ADDR_SIZE; |
572 |
|
573 |
/* API vectors */ |
574 |
cpu->mts_map = MTS_PROTO(api_map); |
575 |
cpu->mts_unmap = MTS_PROTO(api_unmap); |
576 |
|
577 |
/* Memory lookup operation */ |
578 |
cpu->mem_op_lookup = MTS_PROTO(lookup); |
579 |
|
580 |
/* Translation operation */ |
581 |
cpu->translate = MTS_PROTO(translate); |
582 |
|
583 |
/* Shutdown operation */ |
584 |
cpu->mts_shutdown = MTS_PROTO(shutdown); |
585 |
|
586 |
/* Rebuild MTS data structures */ |
587 |
cpu->gen->mts_rebuild = MTS_PROTO(api_rebuild); |
588 |
|
589 |
/* Show statistics */ |
590 |
cpu->gen->mts_show_stats = MTS_PROTO(show_stats); |
591 |
|
592 |
/* Load Operations */ |
593 |
cpu->mem_op_fn[MIPS_MEMOP_LB] = MTS_PROTO(lb); |
594 |
cpu->mem_op_fn[MIPS_MEMOP_LBU] = MTS_PROTO(lbu); |
595 |
cpu->mem_op_fn[MIPS_MEMOP_LH] = MTS_PROTO(lh); |
596 |
cpu->mem_op_fn[MIPS_MEMOP_LHU] = MTS_PROTO(lhu); |
597 |
cpu->mem_op_fn[MIPS_MEMOP_LW] = MTS_PROTO(lw); |
598 |
cpu->mem_op_fn[MIPS_MEMOP_LWU] = MTS_PROTO(lwu); |
599 |
cpu->mem_op_fn[MIPS_MEMOP_LD] = MTS_PROTO(ld); |
600 |
cpu->mem_op_fn[MIPS_MEMOP_LDL] = MTS_PROTO(ldl); |
601 |
cpu->mem_op_fn[MIPS_MEMOP_LDR] = MTS_PROTO(ldr); |
602 |
|
603 |
/* Store Operations */ |
604 |
cpu->mem_op_fn[MIPS_MEMOP_SB] = MTS_PROTO(sb); |
605 |
cpu->mem_op_fn[MIPS_MEMOP_SH] = MTS_PROTO(sh); |
606 |
cpu->mem_op_fn[MIPS_MEMOP_SW] = MTS_PROTO(sw); |
607 |
cpu->mem_op_fn[MIPS_MEMOP_SD] = MTS_PROTO(sd); |
608 |
|
609 |
/* Load Left/Right operations */ |
610 |
cpu->mem_op_fn[MIPS_MEMOP_LWL] = MTS_PROTO(lwl); |
611 |
cpu->mem_op_fn[MIPS_MEMOP_LWR] = MTS_PROTO(lwr); |
612 |
cpu->mem_op_fn[MIPS_MEMOP_LDL] = MTS_PROTO(ldl); |
613 |
cpu->mem_op_fn[MIPS_MEMOP_LDR] = MTS_PROTO(ldr); |
614 |
|
615 |
/* Store Left/Right operations */ |
616 |
cpu->mem_op_fn[MIPS_MEMOP_SWL] = MTS_PROTO(swl); |
617 |
cpu->mem_op_fn[MIPS_MEMOP_SWR] = MTS_PROTO(swr); |
618 |
cpu->mem_op_fn[MIPS_MEMOP_SDL] = MTS_PROTO(sdl); |
619 |
cpu->mem_op_fn[MIPS_MEMOP_SDR] = MTS_PROTO(sdr); |
620 |
|
621 |
/* LL/SC - Load Linked / Store Conditional */ |
622 |
cpu->mem_op_fn[MIPS_MEMOP_LL] = MTS_PROTO(ll); |
623 |
cpu->mem_op_fn[MIPS_MEMOP_SC] = MTS_PROTO(sc); |
624 |
|
625 |
/* Coprocessor 1 memory access functions */ |
626 |
cpu->mem_op_fn[MIPS_MEMOP_LDC1] = MTS_PROTO(ldc1); |
627 |
cpu->mem_op_fn[MIPS_MEMOP_SDC1] = MTS_PROTO(sdc1); |
628 |
|
629 |
/* Cache Operation */ |
630 |
cpu->mem_op_fn[MIPS_MEMOP_CACHE] = MTS_PROTO(cache); |
631 |
} |
632 |
|
633 |
#undef MTS_ADDR_SIZE |
634 |
#undef MTS_NAME |
635 |
#undef MTS_NAME_UP |
636 |
#undef MTS_PROTO |
637 |
#undef MTS_PROTO_UP |
638 |
#undef MTS_ENTRY |
639 |
#undef MTS_CHUNK |