/[dynamips]/trunk/mips64_exec.c
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upstream/dynamips-0.2.6-RC5/mips64_exec.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/mips64_exec.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * MIPS64 Step-by-step execution.   * MIPS64 Step-by-step execution.
# Line 16  Line 16 
16  #include <sys/mman.h>  #include <sys/mman.h>
17  #include <fcntl.h>  #include <fcntl.h>
18    
 #include "rbtree.h"  
 #include "mips64.h"  
 #include "dynamips.h"  
 #include "vm.h"  
 #include "memory.h"  
19  #include "cpu.h"  #include "cpu.h"
20  #include "cp0.h"  #include "vm.h"
21  #include "mips64_exec.h"  #include "mips64_exec.h"
22    #include "memory.h"
23  #include "insn_lookup.h"  #include "insn_lookup.h"
24    #include "dynamips.h"
25    
26  /* Forward declaration of instruction array */  /* Forward declaration of instruction array */
27  static struct insn_exec_tag mips64_exec_tags[];  static struct mips64_insn_exec_tag mips64_exec_tags[];
28  static insn_lookup_t *ilt = NULL;  static insn_lookup_t *ilt = NULL;
29    
30  /* ILT */  /* ILT */
# Line 36  static forced_inline void *mips64_exec_g Line 33  static forced_inline void *mips64_exec_g
33     return(&mips64_exec_tags[index]);     return(&mips64_exec_tags[index]);
34  }  }
35    
36  static int mips64_exec_chk_lo(struct insn_exec_tag *tag,int value)  static int mips64_exec_chk_lo(struct mips64_insn_exec_tag *tag,int value)
37  {  {
38     return((value & tag->mask) == (tag->value & 0xFFFF));     return((value & tag->mask) == (tag->value & 0xFFFF));
39  }  }
40    
41  static int mips64_exec_chk_hi(struct insn_exec_tag *tag,int value)  static int mips64_exec_chk_hi(struct mips64_insn_exec_tag *tag,int value)
42  {  {
43     return((value & (tag->mask >> 16)) == (tag->value >> 16));     return((value & (tag->mask >> 16)) == (tag->value >> 16));
44  }  }
# Line 54  void mips64_exec_create_ilt(void) Line 51  void mips64_exec_create_ilt(void)
51     for(i=0,count=0;mips64_exec_tags[i].exec;i++)     for(i=0,count=0;mips64_exec_tags[i].exec;i++)
52        count++;        count++;
53    
54     ilt = ilt_create(count,     ilt = ilt_create(count+1,
55                      (ilt_get_insn_cbk_t)mips64_exec_get_insn,                      (ilt_get_insn_cbk_t)mips64_exec_get_insn,
56                      (ilt_check_cbk_t)mips64_exec_chk_lo,                      (ilt_check_cbk_t)mips64_exec_chk_lo,
57                      (ilt_check_cbk_t)mips64_exec_chk_hi);                      (ilt_check_cbk_t)mips64_exec_chk_hi);
# Line 84  int mips64_dump_insn(char *buffer,size_t Line 81  int mips64_dump_insn(char *buffer,size_t
81  {  {
82     char insn_name[64],insn_format[32],*name;     char insn_name[64],insn_format[32],*name;
83     int base,rs,rd,rt,sa,offset,imm;     int base,rs,rd,rt,sa,offset,imm;
84     struct insn_exec_tag *tag;     struct mips64_insn_exec_tag *tag;
85     m_uint64_t new_pc;     m_uint64_t new_pc;
86     int index;     int index;
87    
# Line 330  static forced_inline int Line 327  static forced_inline int
327  mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction)  mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction)
328  {  {
329     register fastcall int (*exec)(cpu_mips_t *,mips_insn_t) = NULL;     register fastcall int (*exec)(cpu_mips_t *,mips_insn_t) = NULL;
330     struct insn_exec_tag *tag;     struct mips64_insn_exec_tag *tag;
331     int index;     int index;
332    
333  #if DEBUG_PERF_COUNTER  #if DEBUG_INSN_PERF_CNT
334     cpu->perf_counter++;     cpu->perf_counter++;
335  #endif  #endif
336        
# Line 364  mips64_exec_single_instruction(cpu_mips_ Line 361  mips64_exec_single_instruction(cpu_mips_
361    
362     printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n",     printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n",
363            instruction,cpu->pc);            instruction,cpu->pc);
364     mips64_dump_regs(cpu);     mips64_dump_regs(cpu->gen);
365     return(0);     return(0);
366  }  }
367    
368  /* Single-step execution */  /* Single-step execution */
369  void mips64_exec_single_step(cpu_mips_t *cpu,mips_insn_t instruction)  fastcall void mips64_exec_single_step(cpu_mips_t *cpu,mips_insn_t instruction)
370  {  {
371     int res;     int res;
372    
# Line 380  void mips64_exec_single_step(cpu_mips_t Line 377  void mips64_exec_single_step(cpu_mips_t
377  }  }
378    
379  /* Run MIPS code in step-by-step mode */  /* Run MIPS code in step-by-step mode */
380  void *mips64_exec_run_cpu(cpu_mips_t *cpu)  void *mips64_exec_run_cpu(cpu_gen_t *gen)
381  {    {  
382       cpu_mips_t *cpu = CPU_MIPS64(gen);
383     pthread_t timer_irq_thread;     pthread_t timer_irq_thread;
    mips_insn_t insn;  
384     int timer_irq_check = 0;     int timer_irq_check = 0;
385       mips_insn_t insn;
386     int res;     int res;
387    
388     if (pthread_create(&timer_irq_thread,NULL,     if (pthread_create(&timer_irq_thread,NULL,
389                        (void *)mips64_timer_irq_run,cpu))                        (void *)mips64_timer_irq_run,cpu))
390     {     {
391        fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n",        fprintf(stderr,"VM '%s': unable to create Timer IRQ thread for CPU%u.\n",
392                cpu->vm->name,cpu->id);                cpu->vm->name,gen->id);
393        cpu_stop(cpu);        cpu_stop(gen);
394        return NULL;        return NULL;
395     }     }
396    
397     cpu->cpu_thread_running = TRUE;     gen->cpu_thread_running = TRUE;
398    
399   start_cpu:   start_cpu:
400     cpu->idle_count = 0;     gen->idle_count = 0;
401    
402     for(;;) {     for(;;) {
403        if (unlikely(cpu->state != MIPS_CPU_RUNNING))        if (unlikely(gen->state != CPU_STATE_RUNNING))
404           break;           break;
405    
406        /* Handle virtual idle loop */        /* Handle virtual idle loop */
407        if (unlikely(cpu->pc == cpu->idle_pc)) {        if (unlikely(cpu->pc == cpu->idle_pc)) {
408           if (++cpu->idle_count == cpu->idle_max) {           if (++gen->idle_count == gen->idle_max) {
409              mips64_idle_loop(cpu);              cpu_idle_loop(gen);
410              cpu->idle_count = 0;              gen->idle_count = 0;
411           }           }
412        }        }
413    
# Line 438  void *mips64_exec_run_cpu(cpu_mips_t *cp Line 436  void *mips64_exec_run_cpu(cpu_mips_t *cp
436        res = mips64_exec_single_instruction(cpu,insn);        res = mips64_exec_single_instruction(cpu,insn);
437    
438        /* Normal flow ? */        /* Normal flow ? */
439        if (likely(!res)) cpu->pc += 4;        if (likely(!res)) cpu->pc += sizeof(mips_insn_t);
440     }     }
441    
442     if (!cpu->pc) {     if (!cpu->pc) {
443        cpu_stop(cpu);        cpu_stop(gen);
444        cpu_log(cpu,"SLOW_EXEC","PC=0, halting CPU.\n");        cpu_log(gen,"SLOW_EXEC","PC=0, halting CPU.\n");
445     }     }
446    
447     /* Check regularly if the CPU has been restarted */     /* Check regularly if the CPU has been restarted */
448     while(cpu->cpu_thread_running) {     while(gen->cpu_thread_running) {
449        cpu->seq_state++;        gen->seq_state++;
450    
451        switch(cpu->state) {        switch(gen->state) {
452           case MIPS_CPU_RUNNING:           case CPU_STATE_RUNNING:
453              cpu->state = MIPS_CPU_RUNNING;              gen->state = CPU_STATE_RUNNING;
454              goto start_cpu;              goto start_cpu;
455    
456           case MIPS_CPU_HALTED:               case CPU_STATE_HALTED:    
457              cpu->cpu_thread_running = FALSE;              gen->cpu_thread_running = FALSE;
458              pthread_join(timer_irq_thread,NULL);              pthread_join(timer_irq_thread,NULL);
459              break;              break;
460        }        }
# Line 1086  static fastcall int mips64_exec_CFC0(cpu Line 1084  static fastcall int mips64_exec_CFC0(cpu
1084     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1085     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1086    
1087     cp0_exec_cfc0(cpu,rt,rd);     mips64_cp0_exec_cfc0(cpu,rt,rd);
1088     return(0);     return(0);
1089  }  }
1090    
# Line 1096  static fastcall int mips64_exec_CTC0(cpu Line 1094  static fastcall int mips64_exec_CTC0(cpu
1094     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1095     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1096    
1097     cp0_exec_ctc0(cpu,rt,rd);     mips64_cp0_exec_ctc0(cpu,rt,rd);
1098     return(0);     return(0);
1099  }  }
1100    
# Line 1160  static fastcall int mips64_exec_DMFC0(cp Line 1158  static fastcall int mips64_exec_DMFC0(cp
1158     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1159     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1160    
1161     cp0_exec_dmfc0(cpu,rt,rd);     mips64_cp0_exec_dmfc0(cpu,rt,rd);
1162     return(0);     return(0);
1163  }  }
1164    
# Line 1180  static fastcall int mips64_exec_DMTC0(cp Line 1178  static fastcall int mips64_exec_DMTC0(cp
1178     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1179     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1180    
1181     cp0_exec_dmtc0(cpu,rt,rd);     mips64_cp0_exec_dmtc0(cpu,rt,rd);
1182     return(0);     return(0);
1183  }  }
1184    
# Line 1544  static fastcall int mips64_exec_MFC0(cpu Line 1542  static fastcall int mips64_exec_MFC0(cpu
1542     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1543     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1544    
1545     cp0_exec_mfc0(cpu,rt,rd);     mips64_cp0_exec_mfc0(cpu,rt,rd);
1546     return(0);     return(0);
1547  }  }
1548    
# Line 1592  static fastcall int mips64_exec_MTC0(cpu Line 1590  static fastcall int mips64_exec_MTC0(cpu
1590     int rt = bits(insn,16,20);     int rt = bits(insn,16,20);
1591     int rd = bits(insn,11,15);     int rd = bits(insn,11,15);
1592    
1593     cp0_exec_mtc0(cpu,rt,rd);     mips64_cp0_exec_mtc0(cpu,rt,rd);
1594     return(0);     return(0);
1595  }  }
1596    
# Line 2030  static fastcall int mips64_exec_TEQI(cpu Line 2028  static fastcall int mips64_exec_TEQI(cpu
2028  /* TLBP */  /* TLBP */
2029  static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn)  static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn)
2030  {  {
2031     cp0_exec_tlbp(cpu);     mips64_cp0_exec_tlbp(cpu);
2032     return(0);     return(0);
2033  }  }
2034    
2035  /* TLBR */  /* TLBR */
2036  static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn)  static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn)
2037  {  {
2038     cp0_exec_tlbr(cpu);     mips64_cp0_exec_tlbr(cpu);
2039     return(0);     return(0);
2040  }  }
2041    
2042  /* TLBWI */  /* TLBWI */
2043  static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn)  static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn)
2044  {  {
2045     cp0_exec_tlbwi(cpu);     mips64_cp0_exec_tlbwi(cpu);
2046     return(0);     return(0);
2047  }  }
2048    
2049  /* TLBWR */  /* TLBWR */
2050  static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn)  static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn)
2051  {  {
2052     cp0_exec_tlbwr(cpu);     mips64_cp0_exec_tlbwr(cpu);
2053     return(0);     return(0);
2054  }  }
2055    
# Line 2078  static fastcall int mips64_exec_XORI(cpu Line 2076  static fastcall int mips64_exec_XORI(cpu
2076  }  }
2077    
2078  /* MIPS instruction array */  /* MIPS instruction array */
2079  static struct insn_exec_tag mips64_exec_tags[] = {  static struct mips64_insn_exec_tag mips64_exec_tags[] = {
2080     { "li"     , mips64_exec_LI      , 0xffe00000 , 0x24000000, 1, 16 },     { "li"     , mips64_exec_LI      , 0xffe00000 , 0x24000000, 1, 16 },
2081     { "move"   , mips64_exec_MOVE    , 0xfc1f07ff , 0x00000021, 1, 15 },     { "move"   , mips64_exec_MOVE    , 0xfc1f07ff , 0x00000021, 1, 15 },
2082     { "b"      , mips64_exec_B       , 0xffff0000 , 0x10000000, 0, 10 },     { "b"      , mips64_exec_B       , 0xffff0000 , 0x10000000, 0, 10 },
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