/[dynamips]/trunk/mips64_cp0.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/mips64_cp0.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 12 - (hide annotations)
Sat Oct 6 16:45:40 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 1922 byte(s)
make working copy

1 dpavlin 7 /*
2     * Cisco router simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #ifndef __CP0_H__
7     #define __CP0_H__
8    
9     #include "utils.h"
10    
11     /* CP0 register names */
12     extern char *mips64_cp0_reg_names[];
13    
14     /* Get cp0 register index given its name */
15     int mips64_cp0_get_reg_index(char *name);
16    
17     /* Get the CPU operating mode (User,Supervisor or Kernel) */
18     u_int mips64_cp0_get_mode(cpu_mips_t *cpu);
19    
20     /* Get a cp0 register */
21     m_uint64_t mips64_cp0_get_reg(cpu_mips_t *cpu,u_int cp0_reg);
22    
23     /* DMFC0 */
24     fastcall void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,
25     u_int cp0_reg);
26    
27     /* DMTC0 */
28     fastcall void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,
29     u_int cp0_reg);
30    
31     /* MFC0 */
32     fastcall void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
33    
34     /* MTC0 */
35     fastcall void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
36    
37     /* CFC0 */
38     fastcall void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
39    
40     /* CTC0 */
41     fastcall void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
42    
43     /* TLB lookup */
44     int mips64_cp0_tlb_lookup(cpu_mips_t *cpu,m_uint64_t vaddr,mts_map_t *res);
45    
46     /* Map all TLB entries into the MTS */
47     void mips64_cp0_map_all_tlb_to_mts(cpu_mips_t *cpu);
48    
49     /* TLBP: Probe a TLB entry */
50     fastcall void mips64_cp0_exec_tlbp(cpu_mips_t *cpu);
51    
52     /* TLBR: Read Indexed TLB entry */
53     fastcall void mips64_cp0_exec_tlbr(cpu_mips_t *cpu);
54    
55     /* TLBWI: Write Indexed TLB entry */
56     fastcall void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu);
57    
58     /* TLBWR: Write Random TLB entry */
59     fastcall void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu);
60    
61     /* Raw dump of the TLB */
62     void mips64_tlb_raw_dump(cpu_gen_t *cpu);
63    
64     /* Dump the specified TLB entry */
65     void mips64_tlb_dump_entry(cpu_mips_t *cpu,u_int index);
66    
67     /* Human-Readable dump of the TLB */
68     void mips64_tlb_dump(cpu_gen_t *cpu);
69    
70     #endif

  ViewVC Help
Powered by ViewVC 1.1.26