/[dynamips]/trunk/mips64_amd64_trans.c
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Annotation of /trunk/mips64_amd64_trans.c

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Revision 10 - (hide annotations)
Sat Oct 6 16:29:14 2007 UTC (16 years, 5 months ago) by dpavlin
Original Path: upstream/dynamips-0.2.7/mips64_amd64_trans.c
File MIME type: text/plain
File size: 77968 byte(s)
dynamips-0.2.7

1 dpavlin 7 /*
2     * Cisco router simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #include <stdio.h>
7     #include <stdlib.h>
8     #include <unistd.h>
9     #include <string.h>
10     #include <sys/types.h>
11     #include <sys/stat.h>
12     #include <sys/mman.h>
13     #include <fcntl.h>
14    
15     #include "cpu.h"
16     #include "mips64_jit.h"
17     #include "mips64_amd64_trans.h"
18     #include "mips64_cp0.h"
19     #include "memory.h"
20    
21     /* Macros for CPU structure access */
22     #define REG_OFFSET(reg) (OFFSET(cpu_mips_t,gpr[(reg)]))
23     #define CP0_REG_OFFSET(c0reg) (OFFSET(cpu_mips_t,cp0.reg[(c0reg)]))
24     #define MEMOP_OFFSET(op) (OFFSET(cpu_mips_t,mem_op_fn[(op)]))
25    
26     #define DECLARE_INSN(name) \
27     static int mips64_emit_##name(cpu_mips_t *cpu,mips64_jit_tcb_t *b, \
28     mips_insn_t insn)
29    
30     /* Set an IRQ */
31     void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq)
32     {
33     m_uint32_t m;
34     m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;
35     atomic_or(&cpu->irq_cause,m);
36     }
37    
38     /* Clear an IRQ */
39     void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq)
40     {
41     m_uint32_t m;
42     m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;
43     atomic_and(&cpu->irq_cause,~m);
44    
45     if (!cpu->irq_cause)
46     cpu->irq_pending = 0;
47     }
48    
49     /* Load a 64 bit immediate value */
50     static inline void mips64_load_imm(mips64_jit_tcb_t *b,u_int reg,
51     m_uint64_t value)
52     {
53     if (value > 0xffffffffULL)
54     amd64_mov_reg_imm_size(b->jit_ptr,reg,value,8);
55     else
56     amd64_mov_reg_imm(b->jit_ptr,reg,value);
57     }
58    
59     /* Set the Pointer Counter (PC) register */
60     void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc)
61     {
62     mips64_load_imm(b,AMD64_RAX,new_pc);
63     amd64_mov_membase_reg(b->jit_ptr,
64     AMD64_R15,OFFSET(cpu_mips_t,pc),
65     AMD64_RAX,8);
66     }
67    
68     /* Set the Return Address (RA) register */
69     void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc)
70     {
71     mips64_load_imm(b,AMD64_RAX,ret_pc);
72     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,
73     REG_OFFSET(MIPS_GPR_RA),
74     AMD64_RAX,8);
75     }
76    
77 dpavlin 8 /*
78     * Try to branch directly to the specified JIT block without returning to
79     * main loop.
80     */
81     static void mips64_try_direct_far_jump(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
82     m_uint64_t new_pc)
83     {
84     m_uint64_t new_page;
85     m_uint32_t pc_hash,pc_offset;
86     u_char *test1,*test2,*test3;
87    
88     new_page = new_pc & MIPS_MIN_PAGE_MASK;
89     pc_offset = (new_pc & MIPS_MIN_PAGE_IMASK) >> 2;
90     pc_hash = mips64_jit_get_pc_hash(new_pc);
91    
92     /* Get JIT block info in %rdx */
93     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
94     AMD64_R15,OFFSET(cpu_mips_t,exec_blk_map),8);
95     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
96     AMD64_RBX,pc_hash*sizeof(void *),8);
97    
98     /* no JIT block found ? */
99     amd64_test_reg_reg(b->jit_ptr,AMD64_RDX,AMD64_RDX);
100     test1 = b->jit_ptr;
101     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
102    
103     /* Check block IA */
104     mips64_load_imm(b,AMD64_RAX,new_page);
105     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,X86_EAX,AMD64_RDX,
106     OFFSET(mips64_jit_tcb_t,start_pc),4);
107     test2 = b->jit_ptr;
108     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
109    
110     /* Jump to the code */
111     amd64_mov_reg_membase(b->jit_ptr,AMD64_RSI,
112     AMD64_RDX,OFFSET(mips64_jit_tcb_t,jit_insn_ptr),8);
113     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
114     AMD64_RSI,pc_offset * sizeof(void *),8);
115    
116     amd64_test_reg_reg(b->jit_ptr,AMD64_RBX,AMD64_RBX);
117     test3 = b->jit_ptr;
118     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
119     amd64_jump_reg(b->jit_ptr,AMD64_RBX);
120    
121     /* Returns to caller... */
122     amd64_patch(test1,b->jit_ptr);
123     amd64_patch(test2,b->jit_ptr);
124     amd64_patch(test3,b->jit_ptr);
125    
126     mips64_set_pc(b,new_pc);
127     mips64_jit_tcb_push_epilog(b);
128     }
129    
130 dpavlin 7 /* Set Jump */
131     static void mips64_set_jump(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
132     m_uint64_t new_pc,int local_jump)
133     {
134     int return_to_caller = FALSE;
135     u_char *jump_ptr;
136    
137     if (cpu->sym_trace && !local_jump)
138     return_to_caller = TRUE;
139    
140     if (!return_to_caller && mips64_jit_tcb_local_addr(b,new_pc,&jump_ptr)) {
141     if (jump_ptr) {
142     amd64_jump_code(b->jit_ptr,jump_ptr);
143     } else {
144 dpavlin 8 /* Never jump directly to code in a delay slot */
145     if (mips64_jit_is_delay_slot(b,new_pc)) {
146     mips64_set_pc(b,new_pc);
147     mips64_jit_tcb_push_epilog(b);
148     return;
149     }
150    
151 dpavlin 7 mips64_jit_tcb_record_patch(b,b->jit_ptr,new_pc);
152     amd64_jump32(b->jit_ptr,0);
153     }
154     } else {
155 dpavlin 8 if (cpu->exec_blk_direct_jump) {
156     /* Block lookup optimization */
157     mips64_try_direct_far_jump(cpu,b,new_pc);
158     } else {
159     mips64_set_pc(b,new_pc);
160     mips64_jit_tcb_push_epilog(b);
161     }
162 dpavlin 7 }
163     }
164    
165     /* Basic C call */
166     static forced_inline
167     void mips64_emit_basic_c_call(mips64_jit_tcb_t *b,void *f)
168     {
169     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,f);
170     amd64_call_reg(b->jit_ptr,AMD64_RCX);
171     }
172    
173     /* Emit a simple call to a C function without any parameter */
174     static void mips64_emit_c_call(mips64_jit_tcb_t *b,void *f)
175     {
176     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
177     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,f);
178     amd64_call_reg(b->jit_ptr,AMD64_RCX);
179     }
180    
181     /* Single-step operation */
182     void mips64_emit_single_step(mips64_jit_tcb_t *b,mips_insn_t insn)
183     {
184     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
185     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,insn);
186     mips64_emit_basic_c_call(b,mips64_exec_single_step);
187     }
188    
189     /* Fast memory operation prototype */
190     typedef void (*memop_fast_access)(mips64_jit_tcb_t *b,int target);
191    
192     /* Fast LW */
193     static void mips64_memop_fast_lw(mips64_jit_tcb_t *b,int target)
194     {
195     amd64_mov_reg_memindex(b->jit_ptr,AMD64_RAX,AMD64_RBX,0,AMD64_RSI,0,4);
196     amd64_bswap32(b->jit_ptr,X86_EAX);
197     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EAX);
198    
199     /* Save value in register */
200     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(target),AMD64_RDX,8);
201     }
202    
203     /* Fast SW */
204     static void mips64_memop_fast_sw(mips64_jit_tcb_t *b,int target)
205     {
206     /* Load value from register */
207     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(target),4);
208     amd64_bswap32(b->jit_ptr,X86_EAX);
209     amd64_mov_memindex_reg(b->jit_ptr,AMD64_RBX,0,AMD64_RSI,0,AMD64_RAX,4);
210     }
211    
212     /* Fast memory operation (64-bit) */
213     static void mips64_emit_memop_fast64(mips64_jit_tcb_t *b,int write_op,
214     int opcode,int base,int offset,
215     int target,int keep_ll_bit,
216     memop_fast_access op_handler)
217     {
218     m_uint32_t val = sign_extend(offset,16);
219     u_char *test1,*test2,*p_exception,*p_exit;
220    
221     test2 = NULL;
222    
223     /* RSI = GPR[base] + sign-extended offset */
224     mips64_load_imm(b,AMD64_RSI,val);
225     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,
226     AMD64_RSI,AMD64_R15,REG_OFFSET(base));
227    
228     /* RBX = mts64_entry index */
229     amd64_mov_reg_reg_size(b->jit_ptr,X86_EBX,X86_ESI,4);
230     amd64_shift_reg_imm_size(b->jit_ptr,X86_SHR,X86_EBX,MTS64_HASH_SHIFT,4);
231     amd64_alu_reg_imm_size(b->jit_ptr,X86_AND,X86_EBX,MTS64_HASH_MASK,4);
232    
233     /* RCX = mts32 entry */
234     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,
235     AMD64_R15,
236     OFFSET(cpu_mips_t,mts_u.mts64_cache),8);
237     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RBX,5); /* TO FIX */
238     amd64_alu_reg_reg(b->jit_ptr,X86_ADD,AMD64_RCX,AMD64_RBX);
239    
240     /* Compare virtual page address (EAX = vpage) */
241     amd64_mov_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RSI,8);
242     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RAX,MIPS_MIN_PAGE_MASK);
243    
244     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX,
245     OFFSET(mts64_entry_t,gvpa),8);
246     test1 = b->jit_ptr;
247     x86_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
248    
249     /* Test if we are writing to a COW page */
250     if (write_op) {
251     amd64_test_membase_imm_size(b->jit_ptr,
252     AMD64_RCX,OFFSET(mts64_entry_t,flags),
253     MTS_FLAG_COW,4);
254     test2 = b->jit_ptr;
255     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
256     }
257    
258     /* ESI = offset in page, RBX = Host Page Address */
259     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_ESI,MIPS_MIN_PAGE_IMASK);
260     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
261     AMD64_RCX,OFFSET(mts64_entry_t,hpa),8);
262    
263     /* Memory access */
264     op_handler(b,target);
265    
266     p_exit = b->jit_ptr;
267     amd64_jump8(b->jit_ptr,0);
268     if (test2)
269     amd64_patch(test2,b->jit_ptr);
270    
271     /* === Slow lookup === */
272     amd64_patch(test1,b->jit_ptr);
273    
274     /* Save PC for exception handling */
275     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
276    
277     /* Sign-extend virtual address */
278     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RSI,X86_ESI);
279    
280     /* RDX = target register */
281     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
282    
283     /* RDI = CPU instance */
284     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
285    
286     /* Call memory access function */
287     amd64_call_membase(b->jit_ptr,AMD64_R15,MEMOP_OFFSET(opcode));
288    
289     /* Exception ? */
290     amd64_test_reg_reg_size(b->jit_ptr,AMD64_RAX,AMD64_RAX,4);
291     p_exception = b->jit_ptr;
292     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
293     mips64_jit_tcb_push_epilog(b);
294    
295     amd64_patch(p_exit,b->jit_ptr);
296     amd64_patch(p_exception,b->jit_ptr);
297     }
298    
299     /* Fast memory operation (32-bit) */
300     static void mips64_emit_memop_fast32(mips64_jit_tcb_t *b,int write_op,
301     int opcode,int base,int offset,
302     int target,int keep_ll_bit,
303     memop_fast_access op_handler)
304     {
305     m_uint32_t val = sign_extend(offset,16);
306     u_char *test1,*test2,*p_exception,*p_exit;
307    
308     test2 = NULL;
309    
310     /* ESI = GPR[base] + sign-extended offset */
311     amd64_mov_reg_imm(b->jit_ptr,X86_ESI,val);
312     amd64_alu_reg_membase_size(b->jit_ptr,X86_ADD,
313     X86_ESI,AMD64_R15,REG_OFFSET(base),4);
314    
315     /* RBX = mts32_entry index */
316     amd64_mov_reg_reg_size(b->jit_ptr,X86_EBX,X86_ESI,4);
317     amd64_shift_reg_imm_size(b->jit_ptr,X86_SHR,X86_EBX,MTS32_HASH_SHIFT,4);
318     amd64_alu_reg_imm_size(b->jit_ptr,X86_AND,X86_EBX,MTS32_HASH_MASK,4);
319    
320     /* RCX = mts32 entry */
321     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,
322     AMD64_R15,
323     OFFSET(cpu_mips_t,mts_u.mts32_cache),8);
324     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RBX,5); /* TO FIX */
325     amd64_alu_reg_reg(b->jit_ptr,X86_ADD,AMD64_RCX,AMD64_RBX);
326    
327     /* Compare virtual page address (EAX = vpage) */
328     amd64_mov_reg_reg(b->jit_ptr,X86_EAX,X86_ESI,4);
329     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_EAX,MIPS_MIN_PAGE_MASK);
330    
331     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,X86_EAX,AMD64_RCX,
332     OFFSET(mts32_entry_t,gvpa),4);
333     test1 = b->jit_ptr;
334     x86_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
335    
336     /* Test if we are writing to a COW page */
337     if (write_op) {
338     amd64_test_membase_imm_size(b->jit_ptr,
339     AMD64_RCX,OFFSET(mts32_entry_t,flags),
340     MTS_FLAG_COW,4);
341     test2 = b->jit_ptr;
342     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
343     }
344    
345     /* ESI = offset in page, RBX = Host Page Address */
346     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_ESI,MIPS_MIN_PAGE_IMASK);
347     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
348     AMD64_RCX,OFFSET(mts32_entry_t,hpa),8);
349    
350     /* Memory access */
351     op_handler(b,target);
352    
353     p_exit = b->jit_ptr;
354     amd64_jump8(b->jit_ptr,0);
355    
356     /* === Slow lookup === */
357     amd64_patch(test1,b->jit_ptr);
358     if (test2)
359     amd64_patch(test2,b->jit_ptr);
360    
361     /* Save PC for exception handling */
362     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
363    
364     /* Sign-extend virtual address */
365     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RSI,X86_ESI);
366    
367     /* RDX = target register */
368     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
369    
370     /* RDI = CPU instance */
371     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
372    
373     /* Call memory access function */
374     amd64_call_membase(b->jit_ptr,AMD64_R15,MEMOP_OFFSET(opcode));
375    
376     /* Exception ? */
377     amd64_test_reg_reg_size(b->jit_ptr,AMD64_RAX,AMD64_RAX,4);
378     p_exception = b->jit_ptr;
379     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
380     mips64_jit_tcb_push_epilog(b);
381    
382     amd64_patch(p_exit,b->jit_ptr);
383     amd64_patch(p_exception,b->jit_ptr);
384     }
385    
386     /* Fast memory operation */
387     static void mips64_emit_memop_fast(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
388     int write_op,int opcode,
389     int base,int offset,
390     int target,int keep_ll_bit,
391     memop_fast_access op_handler)
392     {
393     switch(cpu->addr_mode) {
394     case 32:
395     mips64_emit_memop_fast32(b,write_op,opcode,base,offset,target,
396     keep_ll_bit,op_handler);
397     break;
398     case 64:
399     mips64_emit_memop_fast64(b,write_op,opcode,base,offset,target,
400     keep_ll_bit,op_handler);
401     break;
402     }
403     }
404    
405     /* Memory operation */
406     static void mips64_emit_memop(mips64_jit_tcb_t *b,int op,int base,int offset,
407     int target,int keep_ll_bit)
408     {
409     m_uint64_t val = sign_extend(offset,16);
410     u_char *test1;
411    
412     /* Save PC for exception handling */
413     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
414    
415     /* RDI = CPU instance */
416     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
417    
418     if (!keep_ll_bit) {
419     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
420     amd64_mov_membase_reg(b->jit_ptr,AMD64_RDI,OFFSET(cpu_mips_t,ll_bit),
421     X86_ECX,4);
422     }
423    
424     /* RSI = GPR[base] + sign-extended offset */
425     mips64_load_imm(b,AMD64_RSI,val);
426     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,
427     AMD64_RSI,AMD64_RDI,REG_OFFSET(base));
428    
429     /* RDX = target register */
430     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
431    
432     /* Call memory access function */
433     amd64_call_membase(b->jit_ptr,AMD64_RDI,MEMOP_OFFSET(op));
434    
435     /* Exception ? */
436     amd64_test_reg_reg_size(b->jit_ptr,AMD64_RAX,AMD64_RAX,4);
437     test1 = b->jit_ptr;
438     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
439     mips64_jit_tcb_push_epilog(b);
440     amd64_patch(test1,b->jit_ptr);
441     }
442    
443     /* Coprocessor Register transfert operation */
444     static void mips64_emit_cp_xfr_op(mips64_jit_tcb_t *b,int rt,int rd,void *f)
445     {
446     /* update pc */
447     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
448    
449     /* cp0 register */
450     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,rd);
451    
452     /* gpr */
453     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,rt);
454    
455     /* cpu instance */
456     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
457    
458     mips64_emit_basic_c_call(b,f);
459     }
460    
461     /* Virtual Breakpoint */
462     void mips64_emit_breakpoint(mips64_jit_tcb_t *b)
463     {
464     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
465     mips64_emit_c_call(b,mips64_run_breakpoint);
466     }
467    
468     /* Unknown opcode handler */
469     static fastcall void mips64_unknown_opcode(cpu_mips_t *cpu,m_uint32_t opcode)
470     {
471     printf("CPU = %p\n",cpu);
472    
473     printf("MIPS64: unhandled opcode 0x%8.8x at 0x%llx (ra=0x%llx)\n",
474     opcode,cpu->pc,cpu->gpr[MIPS_GPR_RA]);
475    
476     mips64_dump_regs(cpu->gen);
477     }
478    
479     /* Emit unhandled instruction code */
480     static int mips64_emit_unknown(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
481     mips_insn_t opcode)
482     {
483     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,opcode);
484     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
485    
486     mips64_emit_c_call(b,mips64_unknown_opcode);
487     return(0);
488     }
489    
490     /* Invalid delay slot handler */
491     static fastcall void mips64_invalid_delay_slot(cpu_mips_t *cpu)
492     {
493     printf("MIPS64: invalid instruction in delay slot at 0x%llx (ra=0x%llx)\n",
494     cpu->pc,cpu->gpr[MIPS_GPR_RA]);
495    
496     mips64_dump_regs(cpu->gen);
497    
498     /* Halt the virtual CPU */
499     cpu->pc = 0;
500     }
501    
502     /* Emit unhandled instruction code */
503     int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b)
504     {
505     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
506     mips64_emit_c_call(b,mips64_invalid_delay_slot);
507     return(0);
508     }
509    
510     /*
511     * Increment count register and trigger the timer IRQ if value in compare
512     * register is the same.
513     */
514     void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b)
515     {
516     amd64_inc_membase(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cnt_reg));
517    
518     #if 0 /* TIMER_IRQ */
519     u_char *test1;
520    
521     /* increment the virtual count register */
522     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,
523     AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cnt_reg),4);
524     amd64_inc_reg_size(b->jit_ptr,AMD64_RAX,4);
525     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,
526     OFFSET(cpu_mips_t,cp0_virt_cnt_reg),
527     AMD64_RAX,4);
528    
529     /* check with the virtual compare register */
530     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,AMD64_RAX,
531     AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cmp_reg),4);
532     test1 = b->jit_ptr;
533     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
534    
535     /* we have to trigger the timer irq */
536     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
537     mips64_emit_basic_c_call(b,mips64_trigger_timer_irq);
538    
539     amd64_patch(test1,b->jit_ptr);
540     #endif
541     }
542    
543     /* Check if there are pending IRQ */
544     void mips64_check_pending_irq(mips64_jit_tcb_t *b)
545     {
546     u_char *test1;
547    
548     /* Check the pending IRQ flag */
549     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,
550     AMD64_R15,OFFSET(cpu_mips_t,irq_pending),4);
551    
552     amd64_test_reg_reg_size(b->jit_ptr,AMD64_RAX,AMD64_RAX,4);
553     test1 = b->jit_ptr;
554     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
555    
556     /* Update PC */
557     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
558    
559     /* Trigger the IRQ */
560     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
561     mips64_emit_basic_c_call(b,mips64_trigger_irq);
562     mips64_jit_tcb_push_epilog(b);
563    
564     amd64_patch(test1,b->jit_ptr);
565     }
566    
567     /* Increment the number of executed instructions (performance debugging) */
568     void mips64_inc_perf_counter(mips64_jit_tcb_t *b)
569     {
570     amd64_inc_membase(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,perf_counter));
571     }
572    
573     /* ADD */
574     DECLARE_INSN(ADD)
575     {
576     int rs = bits(insn,21,25);
577     int rt = bits(insn,16,20);
578     int rd = bits(insn,11,15);
579    
580     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
581     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,AMD64_R15,
582     REG_OFFSET(rt));
583    
584     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
585     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
586     return(0);
587     }
588    
589     /* ADDI */
590     DECLARE_INSN(ADDI)
591     {
592     int rs = bits(insn,21,25);
593     int rt = bits(insn,16,20);
594     int imm = bits(insn,0,15);
595     m_uint64_t val = sign_extend(imm,16);
596    
597     /* TODO: Exception handling */
598    
599     mips64_load_imm(b,AMD64_RAX,val);
600     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,
601     AMD64_R15,REG_OFFSET(rs));
602    
603     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
604     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
605     return(0);
606     }
607    
608     /* ADDIU */
609     DECLARE_INSN(ADDIU)
610     {
611     int rs = bits(insn,21,25);
612     int rt = bits(insn,16,20);
613     int imm = bits(insn,0,15);
614     m_uint64_t val = sign_extend(imm,16);
615    
616     mips64_load_imm(b,AMD64_RAX,val);
617    
618     if (rs != 0) {
619     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,
620     AMD64_R15,REG_OFFSET(rs));
621     }
622    
623     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EAX);
624     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RDX,8);
625     return(0);
626     }
627    
628     /* ADDU */
629     DECLARE_INSN(ADDU)
630     {
631     int rs = bits(insn,21,25);
632     int rt = bits(insn,16,20);
633     int rd = bits(insn,11,15);
634    
635     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
636     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,AMD64_R15,
637     REG_OFFSET(rt));
638    
639     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
640     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
641     return(0);
642     }
643    
644     /* AND */
645     DECLARE_INSN(AND)
646     {
647     int rs = bits(insn,21,25);
648     int rt = bits(insn,16,20);
649     int rd = bits(insn,11,15);
650    
651     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
652     amd64_alu_reg_membase(b->jit_ptr,X86_AND,AMD64_RAX,AMD64_R15,
653     REG_OFFSET(rt));
654     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
655     return(0);
656     }
657    
658     /* ANDI */
659     DECLARE_INSN(ANDI)
660     {
661     int rs = bits(insn,21,25);
662     int rt = bits(insn,16,20);
663     int imm = bits(insn,0,15);
664    
665     mips64_load_imm(b,AMD64_RAX,imm);
666    
667     amd64_alu_reg_membase(b->jit_ptr,X86_AND,AMD64_RAX,
668     AMD64_R15,REG_OFFSET(rs));
669    
670     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
671     return(0);
672     }
673    
674     /* B (Branch, virtual instruction) */
675     DECLARE_INSN(B)
676     {
677     int offset = bits(insn,0,15);
678     m_uint64_t new_pc;
679    
680     /* compute the new pc */
681     new_pc = b->start_pc + (b->mips_trans_pos << 2);
682     new_pc += sign_extend(offset << 2,18);
683    
684     /* insert the instruction in the delay slot */
685     mips64_jit_fetch_and_emit(cpu,b,1);
686    
687     /* set the new pc in cpu structure */
688     mips64_set_jump(cpu,b,new_pc,1);
689     return(0);
690     }
691    
692     /* BAL (Branch and Link, virtual instruction) */
693     DECLARE_INSN(BAL)
694     {
695     int offset = bits(insn,0,15);
696     m_uint64_t new_pc;
697    
698     /* compute the new pc */
699     new_pc = b->start_pc + (b->mips_trans_pos << 2);
700     new_pc += sign_extend(offset << 2,18);
701    
702     /* set the return address (instruction after the delay slot) */
703     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
704    
705     /* insert the instruction in the delay slot */
706     mips64_jit_fetch_and_emit(cpu,b,1);
707    
708     /* set the new pc in cpu structure */
709     mips64_set_jump(cpu,b,new_pc,0);
710     return(0);
711     }
712    
713     /* BEQ (Branch On Equal) */
714     DECLARE_INSN(BEQ)
715     {
716     int rs = bits(insn,21,25);
717     int rt = bits(insn,16,20);
718     int offset = bits(insn,0,15);
719     u_char *test1;
720     m_uint64_t new_pc;
721    
722     /* compute the new pc */
723     new_pc = b->start_pc + (b->mips_trans_pos << 2);
724     new_pc += sign_extend(offset << 2,18);
725    
726     /*
727     * compare gpr[rs] and gpr[rt].
728     */
729     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
730     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
731     AMD64_R15,REG_OFFSET(rt));
732     test1 = b->jit_ptr;
733     amd64_branch32(b->jit_ptr, X86_CC_NE, 0, 1);
734    
735     /* insert the instruction in the delay slot */
736     mips64_jit_fetch_and_emit(cpu,b,2);
737    
738     /* set the new pc in cpu structure */
739     mips64_set_jump(cpu,b,new_pc,1);
740    
741     amd64_patch(test1,b->jit_ptr);
742    
743     /* if the branch is not taken, we have to execute the delay slot too */
744     mips64_jit_fetch_and_emit(cpu,b,1);
745     return(0);
746     }
747    
748     /* BEQL (Branch On Equal Likely) */
749     DECLARE_INSN(BEQL)
750     {
751     int rs = bits(insn,21,25);
752     int rt = bits(insn,16,20);
753     int offset = bits(insn,0,15);
754     u_char *test1;
755     m_uint64_t new_pc;
756    
757     /* compute the new pc */
758     new_pc = b->start_pc + (b->mips_trans_pos << 2);
759     new_pc += sign_extend(offset << 2,18);
760    
761     /*
762     * compare gpr[rs] and gpr[rt].
763     */
764     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
765     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
766     AMD64_R15,REG_OFFSET(rt));
767     test1 = b->jit_ptr;
768     amd64_branch32(b->jit_ptr, X86_CC_NE, 0, 1);
769    
770     /* insert the instruction in the delay slot */
771     mips64_jit_fetch_and_emit(cpu,b,1);
772    
773     /* set the new pc in cpu structure */
774     mips64_set_jump(cpu,b,new_pc,1);
775    
776     amd64_patch(test1,b->jit_ptr);
777     return(0);
778     }
779    
780     /* BEQZ (Branch On Equal Zero) */
781     DECLARE_INSN(BEQZ)
782     {
783     int rs = bits(insn,21,25);
784     int offset = bits(insn,0,15);
785     u_char *test1;
786     m_uint64_t new_pc;
787    
788     /* compute the new pc */
789     new_pc = b->start_pc + (b->mips_trans_pos << 2);
790     new_pc += sign_extend(offset << 2,18);
791    
792     /*
793     * compare gpr[rs] with 0.
794     */
795     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
796     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
797     test1 = b->jit_ptr;
798     amd64_branch32(b->jit_ptr, X86_CC_NZ, 0, 1);
799    
800     /* insert the instruction in the delay slot */
801     mips64_jit_fetch_and_emit(cpu,b,2);
802    
803     /* set the new pc in cpu structure */
804     mips64_set_jump(cpu,b,new_pc,1);
805    
806     amd64_patch(test1,b->jit_ptr);
807    
808     /* if the branch is not taken, we have to execute the delay slot too */
809     mips64_jit_fetch_and_emit(cpu,b,1);
810     return(0);
811     }
812    
813     /* BNEZ (Branch On Not Equal Zero) */
814     DECLARE_INSN(BNEZ)
815     {
816     int rs = bits(insn,21,25);
817     int offset = bits(insn,0,15);
818     u_char *test1;
819     m_uint64_t new_pc;
820    
821     /* compute the new pc */
822     new_pc = b->start_pc + (b->mips_trans_pos << 2);
823     new_pc += sign_extend(offset << 2,18);
824    
825     /*
826     * compare gpr[rs] with 0.
827     */
828     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
829     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
830     test1 = b->jit_ptr;
831     amd64_branch32(b->jit_ptr, X86_CC_Z, 0, 1);
832    
833     /* insert the instruction in the delay slot */
834     mips64_jit_fetch_and_emit(cpu,b,2);
835    
836     /* set the new pc in cpu structure */
837     mips64_set_jump(cpu,b,new_pc,1);
838    
839     amd64_patch(test1,b->jit_ptr);
840    
841     /* if the branch is not taken, we have to execute the delay slot too */
842     mips64_jit_fetch_and_emit(cpu,b,1);
843     return(0);
844     }
845    
846     /* BGEZ (Branch On Greater or Equal Than Zero) */
847     DECLARE_INSN(BGEZ)
848     {
849     int rs = bits(insn,21,25);
850     int offset = bits(insn,0,15);
851     u_char *test1;
852     m_uint64_t new_pc;
853    
854     /* compute the new pc */
855     new_pc = b->start_pc + (b->mips_trans_pos << 2);
856     new_pc += sign_extend(offset << 2,18);
857    
858     /* If sign bit is set, don't take the branch */
859     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
860     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
861     test1 = b->jit_ptr;
862     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
863    
864     /* insert the instruction in the delay slot */
865     mips64_jit_fetch_and_emit(cpu,b,2);
866    
867     /* set the new pc in cpu structure */
868     mips64_set_jump(cpu,b,new_pc,1);
869    
870     amd64_patch(test1,b->jit_ptr);
871    
872     /* if the branch is not taken, we have to execute the delay slot too */
873     mips64_jit_fetch_and_emit(cpu,b,1);
874     return(0);
875     }
876    
877     /* BGEZAL (Branch On Greater or Equal Than Zero And Link) */
878     DECLARE_INSN(BGEZAL)
879     {
880     int rs = bits(insn,21,25);
881     int offset = bits(insn,0,15);
882     u_char *test1;
883     m_uint64_t new_pc;
884    
885     /* compute the new pc */
886     new_pc = b->start_pc + (b->mips_trans_pos << 2);
887     new_pc += sign_extend(offset << 2,18);
888    
889     /* set the return address (instruction after the delay slot) */
890     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
891    
892     /* If sign bit is set, don't take the branch */
893     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
894     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
895     test1 = b->jit_ptr;
896     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
897    
898     /* insert the instruction in the delay slot */
899     mips64_jit_fetch_and_emit(cpu,b,2);
900    
901     /* set the new pc in cpu structure */
902     mips64_set_jump(cpu,b,new_pc,1);
903    
904     amd64_patch(test1,b->jit_ptr);
905    
906     /* if the branch is not taken, we have to execute the delay slot too */
907     mips64_jit_fetch_and_emit(cpu,b,1);
908     return(0);
909     }
910    
911     /* BGEZALL (Branch On Greater or Equal Than Zero And Link Likely) */
912     DECLARE_INSN(BGEZALL)
913     {
914     int rs = bits(insn,21,25);
915     int offset = bits(insn,0,15);
916     u_char *test1;
917     m_uint64_t new_pc;
918    
919     /* compute the new pc */
920     new_pc = b->start_pc + (b->mips_trans_pos << 2);
921     new_pc += sign_extend(offset << 2,18);
922    
923     /* set the return address (instruction after the delay slot) */
924     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
925    
926     /* If sign bit is set, don't take the branch */
927     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
928     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
929     test1 = b->jit_ptr;
930     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
931    
932     /* insert the instruction in the delay slot */
933     mips64_jit_fetch_and_emit(cpu,b,1);
934    
935     /* set the new pc in cpu structure */
936     mips64_set_jump(cpu,b,new_pc,1);
937    
938     amd64_patch(test1,b->jit_ptr);
939     return(0);
940     }
941    
942     /* BGEZL (Branch On Greater or Equal Than Zero Likely) */
943     DECLARE_INSN(BGEZL)
944     {
945     int rs = bits(insn,21,25);
946     int offset = bits(insn,0,15);
947     u_char *test1;
948     m_uint64_t new_pc;
949    
950     /* compute the new pc */
951     new_pc = b->start_pc + (b->mips_trans_pos << 2);
952     new_pc += sign_extend(offset << 2,18);
953    
954     /* If sign bit is set, don't take the branch */
955     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
956     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
957     test1 = b->jit_ptr;
958     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
959    
960     /* insert the instruction in the delay slot */
961     mips64_jit_fetch_and_emit(cpu,b,1);
962    
963     /* set the new pc in cpu structure */
964     mips64_set_jump(cpu,b,new_pc,1);
965    
966     amd64_patch(test1,b->jit_ptr);
967     return(0);
968     }
969    
970     /* BGTZ (Branch On Greater Than Zero) */
971     DECLARE_INSN(BGTZ)
972     {
973     int rs = bits(insn,21,25);
974     int offset = bits(insn,0,15);
975     u_char *test1;
976     m_uint64_t new_pc;
977    
978     /* compute the new pc */
979     new_pc = b->start_pc + (b->mips_trans_pos << 2);
980     new_pc += sign_extend(offset << 2,18);
981    
982     /* compare reg to zero */
983     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
984     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
985    
986     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
987     test1 = b->jit_ptr;
988     amd64_branch32(b->jit_ptr, X86_CC_LE, 0, 1);
989    
990     /* insert the instruction in the delay slot */
991     mips64_jit_fetch_and_emit(cpu,b,2);
992    
993     /* set the new pc in cpu structure */
994     mips64_set_jump(cpu,b,new_pc,1);
995    
996     amd64_patch(test1,b->jit_ptr);
997    
998     /* if the branch is not taken, we have to execute the delay slot too */
999     mips64_jit_fetch_and_emit(cpu,b,1);
1000     return(0);
1001     }
1002    
1003     /* BGTZL (Branch On Greater Than Zero Likely) */
1004     DECLARE_INSN(BGTZL)
1005     {
1006     int rs = bits(insn,21,25);
1007     int offset = bits(insn,0,15);
1008     u_char *test1;
1009     m_uint64_t new_pc;
1010    
1011     /* compute the new pc */
1012     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1013     new_pc += sign_extend(offset << 2,18);
1014    
1015     /* compare reg to zero */
1016     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1017     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
1018    
1019     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
1020     test1 = b->jit_ptr;
1021     amd64_branch32(b->jit_ptr, X86_CC_LE, 0, 1);
1022    
1023     /* insert the instruction in the delay slot */
1024     mips64_jit_fetch_and_emit(cpu,b,1);
1025    
1026     /* set the new pc in cpu structure */
1027     mips64_set_jump(cpu,b,new_pc,1);
1028    
1029     amd64_patch(test1,b->jit_ptr);
1030     return(0);
1031     }
1032    
1033     /* BLEZ (Branch On Less or Equal Than Zero) */
1034     DECLARE_INSN(BLEZ)
1035     {
1036     int rs = bits(insn,21,25);
1037     int offset = bits(insn,0,15);
1038     u_char *test1;
1039     m_uint64_t new_pc;
1040    
1041     /* compute the new pc */
1042     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1043     new_pc += sign_extend(offset << 2,18);
1044    
1045     /* compare reg to zero */
1046     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1047     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
1048    
1049     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
1050     test1 = b->jit_ptr;
1051     amd64_branch32(b->jit_ptr, X86_CC_GT, 0, 1);
1052    
1053     /* insert the instruction in the delay slot */
1054     mips64_jit_fetch_and_emit(cpu,b,2);
1055    
1056     /* set the new pc in cpu structure */
1057     mips64_set_jump(cpu,b,new_pc,1);
1058    
1059     amd64_patch(test1,b->jit_ptr);
1060    
1061     /* if the branch is not taken, we have to execute the delay slot too */
1062     mips64_jit_fetch_and_emit(cpu,b,1);
1063     return(0);
1064     }
1065    
1066     /* BLEZL (Branch On Less or Equal Than Zero Likely) */
1067     DECLARE_INSN(BLEZL)
1068     {
1069     int rs = bits(insn,21,25);
1070     int offset = bits(insn,0,15);
1071     u_char *test1;
1072     m_uint64_t new_pc;
1073    
1074     /* compute the new pc */
1075     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1076     new_pc += sign_extend(offset << 2,18);
1077    
1078     /* compare reg to zero */
1079     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1080     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
1081    
1082     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
1083     test1 = b->jit_ptr;
1084     amd64_branch32(b->jit_ptr, X86_CC_GT, 0, 1);
1085    
1086     /* insert the instruction in the delay slot */
1087     mips64_jit_fetch_and_emit(cpu,b,1);
1088    
1089     /* set the new pc in cpu structure */
1090     mips64_set_jump(cpu,b,new_pc,1);
1091    
1092     amd64_patch(test1,b->jit_ptr);
1093     return(0);
1094     }
1095    
1096     /* BLTZ (Branch On Less Than Zero) */
1097     DECLARE_INSN(BLTZ)
1098     {
1099     int rs = bits(insn,21,25);
1100     int offset = bits(insn,0,15);
1101     u_char *test1;
1102     m_uint64_t new_pc;
1103    
1104     /* compute the new pc */
1105     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1106     new_pc += sign_extend(offset << 2,18);
1107    
1108     /* If sign bit isn't set, don't take the branch */
1109     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1110     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1111     test1 = b->jit_ptr;
1112     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1113    
1114     /* insert the instruction in the delay slot */
1115     mips64_jit_fetch_and_emit(cpu,b,2);
1116    
1117     /* set the new pc in cpu structure */
1118     mips64_set_jump(cpu,b,new_pc,1);
1119    
1120     amd64_patch(test1,b->jit_ptr);
1121    
1122     /* if the branch is not taken, we have to execute the delay slot too */
1123     mips64_jit_fetch_and_emit(cpu,b,1);
1124     return(0);
1125     }
1126    
1127     /* BLTZAL (Branch On Less Than Zero And Link) */
1128     DECLARE_INSN(BLTZAL)
1129     {
1130     int rs = bits(insn,21,25);
1131     int offset = bits(insn,0,15);
1132     u_char *test1;
1133     m_uint64_t new_pc;
1134    
1135     /* compute the new pc */
1136     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1137     new_pc += sign_extend(offset << 2,18);
1138    
1139     /* set the return address (instruction after the delay slot) */
1140     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1141    
1142     /* If sign bit isn't set, don't take the branch */
1143     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1144     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1145     test1 = b->jit_ptr;
1146     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1147    
1148     /* insert the instruction in the delay slot */
1149     mips64_jit_fetch_and_emit(cpu,b,2);
1150    
1151     /* set the new pc in cpu structure */
1152     mips64_set_jump(cpu,b,new_pc,1);
1153    
1154     amd64_patch(test1,b->jit_ptr);
1155    
1156     /* if the branch is not taken, we have to execute the delay slot too */
1157     mips64_jit_fetch_and_emit(cpu,b,1);
1158     return(0);
1159     }
1160    
1161     /* BLTZALL (Branch On Less Than Zero And Link Likely) */
1162     DECLARE_INSN(BLTZALL)
1163     {
1164     int rs = bits(insn,21,25);
1165     int offset = bits(insn,0,15);
1166     u_char *test1;
1167     m_uint64_t new_pc;
1168    
1169     /* compute the new pc */
1170     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1171     new_pc += sign_extend(offset << 2,18);
1172    
1173     /* set the return address (instruction after the delay slot) */
1174     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1175    
1176     /* If sign bit isn't set, don't take the branch */
1177     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1178     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1179     test1 = b->jit_ptr;
1180     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1181    
1182     /* insert the instruction in the delay slot */
1183     mips64_jit_fetch_and_emit(cpu,b,1);
1184    
1185     /* set the new pc in cpu structure */
1186     mips64_set_jump(cpu,b,new_pc,1);
1187    
1188     amd64_patch(test1,b->jit_ptr);
1189     return(0);
1190     }
1191    
1192     /* BLTZL (Branch On Less Than Zero Likely) */
1193     DECLARE_INSN(BLTZL)
1194     {
1195     int rs = bits(insn,21,25);
1196     int offset = bits(insn,0,15);
1197     u_char *test1;
1198     m_uint64_t new_pc;
1199    
1200     /* compute the new pc */
1201     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1202     new_pc += sign_extend(offset << 2,18);
1203    
1204     /* If sign bit isn't set, don't take the branch */
1205     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1206     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1207     test1 = b->jit_ptr;
1208     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1209    
1210     /* insert the instruction in the delay slot */
1211     mips64_jit_fetch_and_emit(cpu,b,1);
1212    
1213     /* set the new pc in cpu structure */
1214     mips64_set_jump(cpu,b,new_pc,1);
1215    
1216     amd64_patch(test1,b->jit_ptr);
1217     return(0);
1218     }
1219    
1220     /* BNE (Branch On Not Equal) */
1221     DECLARE_INSN(BNE)
1222     {
1223     int rs = bits(insn,21,25);
1224     int rt = bits(insn,16,20);
1225     int offset = bits(insn,0,15);
1226     u_char *test1;
1227     m_uint64_t new_pc;
1228    
1229     /* compute the new pc */
1230     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1231     new_pc += sign_extend(offset << 2,18);
1232    
1233     /*
1234     * compare gpr[rs] and gpr[rt].
1235     */
1236     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1237     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
1238     AMD64_R15,REG_OFFSET(rt));
1239     test1 = b->jit_ptr;
1240     amd64_branch32(b->jit_ptr, X86_CC_E, 0, 1);
1241    
1242     /* insert the instruction in the delay slot */
1243     mips64_jit_fetch_and_emit(cpu,b,2);
1244    
1245     /* set the new pc in cpu structure */
1246     mips64_set_jump(cpu,b,new_pc,1);
1247    
1248     amd64_patch(test1,b->jit_ptr);
1249    
1250     /* if the branch is not taken, we have to execute the delay slot too */
1251     mips64_jit_fetch_and_emit(cpu,b,1);
1252     return(0);
1253     }
1254    
1255     /* BNEL (Branch On Not Equal Likely) */
1256     DECLARE_INSN(BNEL)
1257     {
1258     int rs = bits(insn,21,25);
1259     int rt = bits(insn,16,20);
1260     int offset = bits(insn,0,15);
1261     u_char *test1;
1262     m_uint64_t new_pc;
1263    
1264     /* compute the new pc */
1265     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1266     new_pc += sign_extend(offset << 2,18);
1267    
1268     /*
1269     * compare gpr[rs] and gpr[rt].
1270     */
1271     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1272     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
1273     AMD64_R15,REG_OFFSET(rt));
1274     test1 = b->jit_ptr;
1275     amd64_branch32(b->jit_ptr, X86_CC_E, 0, 1);
1276    
1277     /* insert the instruction in the delay slot */
1278     mips64_jit_fetch_and_emit(cpu,b,1);
1279    
1280     /* set the new pc in cpu structure */
1281     mips64_set_jump(cpu,b,new_pc,1);
1282    
1283     amd64_patch(test1,b->jit_ptr);
1284     return(0);
1285     }
1286    
1287     /* BREAK */
1288     DECLARE_INSN(BREAK)
1289     {
1290     u_int code = bits(insn,6,25);
1291    
1292     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,code);
1293     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1294     mips64_emit_basic_c_call(b,mips64_exec_break);
1295     mips64_jit_tcb_push_epilog(b);
1296     return(0);
1297     }
1298    
1299     /* CACHE */
1300     DECLARE_INSN(CACHE)
1301     {
1302     int base = bits(insn,21,25);
1303     int op = bits(insn,16,20);
1304     int offset = bits(insn,0,15);
1305    
1306     mips64_emit_memop(b,MIPS_MEMOP_CACHE,base,offset,op,0);
1307     return(0);
1308     }
1309    
1310     /* CFC0 */
1311     DECLARE_INSN(CFC0)
1312     {
1313     int rt = bits(insn,16,20);
1314     int rd = bits(insn,11,15);
1315    
1316     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_cfc0);
1317     return(0);
1318     }
1319    
1320     /* CTC0 */
1321     DECLARE_INSN(CTC0)
1322     {
1323     int rt = bits(insn,16,20);
1324     int rd = bits(insn,11,15);
1325    
1326     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_ctc0);
1327     return(0);
1328     }
1329    
1330     /* DADDIU */
1331     DECLARE_INSN(DADDIU)
1332     {
1333     int rs = bits(insn,21,25);
1334     int rt = bits(insn,16,20);
1335     int imm = bits(insn,0,15);
1336     m_uint64_t val = sign_extend(imm,16);
1337    
1338     mips64_load_imm(b,AMD64_RCX,val);
1339     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RCX,
1340     AMD64_R15,REG_OFFSET(rs));
1341     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1342     return(0);
1343     }
1344    
1345     /* DADDU: rd = rs + rt */
1346     DECLARE_INSN(DADDU)
1347     {
1348     int rs = bits(insn,21,25);
1349     int rt = bits(insn,16,20);
1350     int rd = bits(insn,11,15);
1351    
1352     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),8);
1353     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RCX,
1354     AMD64_R15,REG_OFFSET(rt));
1355     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
1356     return(0);
1357     }
1358    
1359     /* DIV */
1360     DECLARE_INSN(DIV)
1361     {
1362     int rs = bits(insn,21,25);
1363     int rt = bits(insn,16,20);
1364    
1365     /* eax = gpr[rs] */
1366     amd64_clear_reg(b->jit_ptr,AMD64_RDX);
1367     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
1368    
1369     /* ecx = gpr[rt] */
1370     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
1371    
1372     /* eax = quotient (LO), edx = remainder (HI) */
1373     amd64_div_reg_size(b->jit_ptr,AMD64_RCX,1,4);
1374    
1375     /* store LO */
1376     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
1377     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
1378     AMD64_RAX,8);
1379    
1380     /* store HI */
1381     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1382     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
1383     AMD64_RDX,8);
1384     return(0);
1385     }
1386    
1387     /* DIVU */
1388     DECLARE_INSN(DIVU)
1389     {
1390     int rs = bits(insn,21,25);
1391     int rt = bits(insn,16,20);
1392    
1393     /* eax = gpr[rs] */
1394     amd64_clear_reg(b->jit_ptr,AMD64_RDX);
1395     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
1396    
1397     /* ecx = gpr[rt] */
1398     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
1399    
1400     /* eax = quotient (LO), edx = remainder (HI) */
1401     amd64_div_reg_size(b->jit_ptr,AMD64_RCX,0,4);
1402    
1403     /* store LO */
1404     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
1405     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
1406     AMD64_RAX,8);
1407    
1408     /* store HI */
1409     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1410     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
1411     AMD64_RDX,8);
1412     return(0);
1413     }
1414    
1415     /* DMFC0 */
1416     DECLARE_INSN(DMFC0)
1417     {
1418     int rt = bits(insn,16,20);
1419     int rd = bits(insn,11,15);
1420    
1421     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_dmfc0);
1422     return(0);
1423     }
1424    
1425     /* DMFC1 */
1426     DECLARE_INSN(DMFC1)
1427     {
1428     int rt = bits(insn,16,20);
1429     int rd = bits(insn,11,15);
1430    
1431     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmfc1);
1432     return(0);
1433     }
1434    
1435     /* DMTC0 */
1436     DECLARE_INSN(DMTC0)
1437     {
1438     int rt = bits(insn,16,20);
1439     int rd = bits(insn,11,15);
1440    
1441     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_dmtc0);
1442     return(0);
1443     }
1444    
1445     /* DMTC1 */
1446     DECLARE_INSN(DMTC1)
1447     {
1448     int rt = bits(insn,16,20);
1449     int rd = bits(insn,11,15);
1450    
1451     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmtc1);
1452     return(0);
1453     }
1454    
1455     /* DSLL */
1456     DECLARE_INSN(DSLL)
1457     {
1458     int rt = bits(insn,16,20);
1459     int rd = bits(insn,11,15);
1460     int sa = bits(insn,6,10);
1461    
1462     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1463     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa);
1464     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1465     return(0);
1466     }
1467    
1468     /* DSLL32 */
1469     DECLARE_INSN(DSLL32)
1470     {
1471     int rt = bits(insn,16,20);
1472     int rd = bits(insn,11,15);
1473     int sa = bits(insn,6,10);
1474    
1475     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1476     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa+32);
1477     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1478     return(0);
1479     }
1480    
1481     /* DSLLV */
1482     DECLARE_INSN(DSLLV)
1483     {
1484     int rs = bits(insn,21,25);
1485     int rt = bits(insn,16,20);
1486     int rd = bits(insn,11,15);
1487    
1488     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1489     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1490    
1491     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1492     amd64_shift_reg(b->jit_ptr,X86_SHL,AMD64_RAX);
1493     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1494     return(0);
1495     }
1496    
1497     /* DSRA */
1498     DECLARE_INSN(DSRA)
1499     {
1500     int rt = bits(insn,16,20);
1501     int rd = bits(insn,11,15);
1502     int sa = bits(insn,6,10);
1503    
1504     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1505     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RAX,sa);
1506     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1507     return(0);
1508     }
1509    
1510     /* DSRA32 */
1511     DECLARE_INSN(DSRA32)
1512     {
1513     int rt = bits(insn,16,20);
1514     int rd = bits(insn,11,15);
1515     int sa = bits(insn,6,10);
1516    
1517     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1518     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RAX,sa+32);
1519     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1520     return(0);
1521     }
1522    
1523     /* DSRAV */
1524     DECLARE_INSN(DSRAV)
1525     {
1526     int rs = bits(insn,21,25);
1527     int rt = bits(insn,16,20);
1528     int rd = bits(insn,11,15);
1529    
1530     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1531     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1532    
1533     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1534     amd64_shift_reg(b->jit_ptr,X86_SAR,AMD64_RAX);
1535     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1536     return(0);
1537     }
1538    
1539     /* DSRL */
1540     DECLARE_INSN(DSRL)
1541     {
1542     int rt = bits(insn,16,20);
1543     int rd = bits(insn,11,15);
1544     int sa = bits(insn,6,10);
1545    
1546     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1547     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa);
1548     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1549     return(0);
1550     }
1551    
1552     /* DSRL32 */
1553     DECLARE_INSN(DSRL32)
1554     {
1555     int rt = bits(insn,16,20);
1556     int rd = bits(insn,11,15);
1557     int sa = bits(insn,6,10);
1558    
1559     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1560     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa+32);
1561     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1562     return(0);
1563     }
1564    
1565     /* DSRLV */
1566     DECLARE_INSN(DSRLV)
1567     {
1568     int rs = bits(insn,21,25);
1569     int rt = bits(insn,16,20);
1570     int rd = bits(insn,11,15);
1571    
1572     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1573     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1574    
1575     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1576     amd64_shift_reg(b->jit_ptr,X86_SHR,AMD64_RAX);
1577     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1578     return(0);
1579     }
1580    
1581     /* DSUBU: rd = rs - rt */
1582     DECLARE_INSN(DSUBU)
1583     {
1584     int rs = bits(insn,21,25);
1585     int rt = bits(insn,16,20);
1586     int rd = bits(insn,11,15);
1587    
1588     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1589     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,
1590     AMD64_R15,REG_OFFSET(rt));
1591     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1592     return(0);
1593     }
1594    
1595     /* ERET */
1596     DECLARE_INSN(ERET)
1597     {
1598     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
1599     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1600     mips64_emit_basic_c_call(b,mips64_exec_eret);
1601     mips64_jit_tcb_push_epilog(b);
1602     return(0);
1603     }
1604    
1605     /* J (Jump) */
1606     DECLARE_INSN(J)
1607     {
1608     u_int instr_index = bits(insn,0,25);
1609     m_uint64_t new_pc;
1610    
1611     /* compute the new pc */
1612     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1613     new_pc &= ~((1 << 28) - 1);
1614     new_pc |= instr_index << 2;
1615    
1616     /* insert the instruction in the delay slot */
1617     mips64_jit_fetch_and_emit(cpu,b,1);
1618    
1619     /* set the new pc in cpu structure */
1620     mips64_set_jump(cpu,b,new_pc,1);
1621     return(0);
1622     }
1623    
1624     /* JAL (Jump And Link) */
1625     DECLARE_INSN(JAL)
1626     {
1627     u_int instr_index = bits(insn,0,25);
1628     m_uint64_t new_pc;
1629    
1630     /* compute the new pc */
1631     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1632     new_pc &= ~((1 << 28) - 1);
1633     new_pc |= instr_index << 2;
1634    
1635     /* set the return address (instruction after the delay slot) */
1636     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1637    
1638     /* insert the instruction in the delay slot */
1639     mips64_jit_fetch_and_emit(cpu,b,1);
1640    
1641     /* set the new pc in cpu structure */
1642     mips64_set_jump(cpu,b,new_pc,0);
1643     return(0);
1644     }
1645    
1646     /* JALR (Jump and Link Register) */
1647     DECLARE_INSN(JALR)
1648     {
1649     int rs = bits(insn,21,25);
1650     int rd = bits(insn,11,15);
1651     m_uint64_t ret_pc;
1652    
1653     /* set the return pc (instruction after the delay slot) in GPR[rd] */
1654     ret_pc = b->start_pc + ((b->mips_trans_pos + 1) << 2);
1655     mips64_load_imm(b,AMD64_RAX,ret_pc);
1656     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1657    
1658     /* get the new pc */
1659     amd64_mov_reg_membase(b->jit_ptr,AMD64_R14,AMD64_R15,REG_OFFSET(rs),8);
1660    
1661     #if DEBUG_JR0
1662     {
1663     u_char *test1;
1664    
1665     amd64_test_reg_reg(b->jit_ptr,AMD64_R14,AMD64_R14);
1666     test1 = b->jit_ptr;
1667     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
1668     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1669     mips64_emit_c_call(b,mips64_debug_jr0);
1670     amd64_patch(test1,b->jit_ptr);
1671     }
1672     #endif
1673    
1674     /* insert the instruction in the delay slot */
1675     mips64_jit_fetch_and_emit(cpu,b,1);
1676    
1677     /* set the new pc */
1678     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,pc),
1679     AMD64_R14,8);
1680    
1681     /* returns to the caller which will determine the next path */
1682     mips64_jit_tcb_push_epilog(b);
1683     return(0);
1684     }
1685    
1686     /* JR (Jump Register) */
1687     DECLARE_INSN(JR)
1688     {
1689     int rs = bits(insn,21,25);
1690    
1691     /* get the new pc */
1692     amd64_mov_reg_membase(b->jit_ptr,AMD64_R14,AMD64_R15,REG_OFFSET(rs),8);
1693    
1694     #if DEBUG_JR0
1695     {
1696     u_char *test1;
1697    
1698     amd64_test_reg_reg(b->jit_ptr,AMD64_RCX,AMD64_RCX);
1699     test1 = b->jit_ptr;
1700     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
1701     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1702     mips64_emit_c_call(b,mips64_debug_jr0);
1703     amd64_patch(test1,b->jit_ptr);
1704     }
1705     #endif
1706    
1707     /* insert the instruction in the delay slot */
1708     mips64_jit_fetch_and_emit(cpu,b,1);
1709    
1710     /* set the new pc */
1711     amd64_mov_membase_reg(b->jit_ptr,
1712     AMD64_R15,OFFSET(cpu_mips_t,pc),
1713     AMD64_R14,8);
1714    
1715     /* returns to the caller which will determine the next path */
1716     mips64_jit_tcb_push_epilog(b);
1717     return(0);
1718     }
1719    
1720     /* LB (Load Byte) */
1721     DECLARE_INSN(LB)
1722     {
1723     int base = bits(insn,21,25);
1724     int rt = bits(insn,16,20);
1725     int offset = bits(insn,0,15);
1726    
1727     mips64_emit_memop(b,MIPS_MEMOP_LB,base,offset,rt,TRUE);
1728     return(0);
1729     }
1730    
1731     /* LBU (Load Byte Unsigned) */
1732     DECLARE_INSN(LBU)
1733     {
1734     int base = bits(insn,21,25);
1735     int rt = bits(insn,16,20);
1736     int offset = bits(insn,0,15);
1737    
1738     mips64_emit_memop(b,MIPS_MEMOP_LBU,base,offset,rt,TRUE);
1739     return(0);
1740     }
1741    
1742     /* LD (Load Double-Word) */
1743     DECLARE_INSN(LD)
1744     {
1745     int base = bits(insn,21,25);
1746     int rt = bits(insn,16,20);
1747     int offset = bits(insn,0,15);
1748    
1749     mips64_emit_memop(b,MIPS_MEMOP_LD,base,offset,rt,TRUE);
1750     return(0);
1751     }
1752    
1753     /* LDC1 (Load Double-Word to Coprocessor 1) */
1754     DECLARE_INSN(LDC1)
1755     {
1756     int base = bits(insn,21,25);
1757     int ft = bits(insn,16,20);
1758     int offset = bits(insn,0,15);
1759    
1760     mips64_emit_memop(b,MIPS_MEMOP_LDC1,base,offset,ft,TRUE);
1761     return(0);
1762     }
1763    
1764     /* LDL (Load Double-Word Left) */
1765     DECLARE_INSN(LDL)
1766     {
1767     int base = bits(insn,21,25);
1768     int rt = bits(insn,16,20);
1769     int offset = bits(insn,0,15);
1770    
1771     mips64_emit_memop(b,MIPS_MEMOP_LDL,base,offset,rt,TRUE);
1772     return(0);
1773     }
1774    
1775     /* LDR (Load Double-Word Right) */
1776     DECLARE_INSN(LDR)
1777     {
1778     int base = bits(insn,21,25);
1779     int rt = bits(insn,16,20);
1780     int offset = bits(insn,0,15);
1781    
1782     mips64_emit_memop(b,MIPS_MEMOP_LDR,base,offset,rt,TRUE);
1783     return(0);
1784     }
1785    
1786     /* LH (Load Half-Word) */
1787     DECLARE_INSN(LH)
1788     {
1789     int base = bits(insn,21,25);
1790     int rt = bits(insn,16,20);
1791     int offset = bits(insn,0,15);
1792    
1793     mips64_emit_memop(b,MIPS_MEMOP_LH,base,offset,rt,TRUE);
1794     return(0);
1795     }
1796    
1797     /* LHU (Load Half-Word Unsigned) */
1798     DECLARE_INSN(LHU)
1799     {
1800     int base = bits(insn,21,25);
1801     int rt = bits(insn,16,20);
1802     int offset = bits(insn,0,15);
1803    
1804     mips64_emit_memop(b,MIPS_MEMOP_LHU,base,offset,rt,TRUE);
1805     return(0);
1806     }
1807    
1808     /* LI (virtual) */
1809     DECLARE_INSN(LI)
1810     {
1811     int rt = bits(insn,16,20);
1812     int imm = bits(insn,0,15);
1813     m_uint64_t val = sign_extend(imm,16);
1814    
1815     mips64_load_imm(b,AMD64_RCX,val);
1816     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1817     return(0);
1818     }
1819    
1820     /* LL (Load Linked) */
1821     DECLARE_INSN(LL)
1822     {
1823     int base = bits(insn,21,25);
1824     int rt = bits(insn,16,20);
1825     int offset = bits(insn,0,15);
1826    
1827     mips64_emit_memop(b,MIPS_MEMOP_LL,base,offset,rt,TRUE);
1828     return(0);
1829     }
1830    
1831     /* LUI */
1832     DECLARE_INSN(LUI)
1833     {
1834     int rt = bits(insn,16,20);
1835     int imm = bits(insn,0,15);
1836     m_uint64_t val = sign_extend(imm,16) << 16;
1837    
1838     #if 1
1839     mips64_load_imm(b,AMD64_RCX,val);
1840     #else
1841     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,imm);
1842     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RCX,48);
1843     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RCX,32);
1844     #endif
1845    
1846     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1847     return(0);
1848     }
1849    
1850     /* LW (Load Word) */
1851     DECLARE_INSN(LW)
1852     {
1853     int base = bits(insn,21,25);
1854     int rt = bits(insn,16,20);
1855     int offset = bits(insn,0,15);
1856    
1857     if (cpu->fast_memop) {
1858     mips64_emit_memop_fast(cpu,b,0,MIPS_MEMOP_LW,base,offset,rt,TRUE,
1859     mips64_memop_fast_lw);
1860     } else {
1861     mips64_emit_memop(b,MIPS_MEMOP_LW,base,offset,rt,TRUE);
1862     }
1863     return(0);
1864     }
1865    
1866     /* LWL (Load Word Left) */
1867     DECLARE_INSN(LWL)
1868     {
1869     int base = bits(insn,21,25);
1870     int rt = bits(insn,16,20);
1871     int offset = bits(insn,0,15);
1872    
1873     mips64_emit_memop(b,MIPS_MEMOP_LWL,base,offset,rt,TRUE);
1874     return(0);
1875     }
1876    
1877     /* LWR (Load Word Right) */
1878     DECLARE_INSN(LWR)
1879     {
1880     int base = bits(insn,21,25);
1881     int rt = bits(insn,16,20);
1882     int offset = bits(insn,0,15);
1883    
1884     mips64_emit_memop(b,MIPS_MEMOP_LWR,base,offset,rt,TRUE);
1885     return(0);
1886     }
1887    
1888     /* LWU (Load Word Unsigned) */
1889     DECLARE_INSN(LWU)
1890     {
1891     int base = bits(insn,21,25);
1892     int rt = bits(insn,16,20);
1893     int offset = bits(insn,0,15);
1894    
1895     mips64_emit_memop(b,MIPS_MEMOP_LWU,base,offset,rt,TRUE);
1896     return(0);
1897     }
1898    
1899     /* MFC0 */
1900     DECLARE_INSN(MFC0)
1901     {
1902     int rt = bits(insn,16,20);
1903     int rd = bits(insn,11,15);
1904    
1905     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_mfc0);
1906     return(0);
1907     }
1908    
1909     /* MFC1 */
1910     DECLARE_INSN(MFC1)
1911     {
1912     int rt = bits(insn,16,20);
1913     int rd = bits(insn,11,15);
1914    
1915     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_mfc1);
1916     return(0);
1917     }
1918    
1919     /* MFHI */
1920     DECLARE_INSN(MFHI)
1921     {
1922     int rd = bits(insn,11,15);
1923    
1924     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
1925     AMD64_R15,OFFSET(cpu_mips_t,hi),8);
1926     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1927     return(0);
1928     }
1929    
1930     /* MFLO */
1931     DECLARE_INSN(MFLO)
1932     {
1933     int rd = bits(insn,11,15);
1934    
1935     if (!rd) return(0);
1936    
1937     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
1938     AMD64_R15,OFFSET(cpu_mips_t,lo),8);
1939     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1940     return(0);
1941     }
1942    
1943     /* MOVE (virtual instruction, real: ADDU) */
1944     DECLARE_INSN(MOVE)
1945     {
1946     int rs = bits(insn,21,25);
1947     int rd = bits(insn,11,15);
1948    
1949     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),4);
1950     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1951     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1952     return(0);
1953     }
1954    
1955     /* MTC0 */
1956     DECLARE_INSN(MTC0)
1957     {
1958     int rt = bits(insn,16,20);
1959     int rd = bits(insn,11,15);
1960    
1961     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_mtc0);
1962     return(0);
1963     }
1964    
1965     /* MTC1 */
1966     DECLARE_INSN(MTC1)
1967     {
1968     int rt = bits(insn,16,20);
1969     int rd = bits(insn,11,15);
1970    
1971     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_mtc1);
1972     return(0);
1973     }
1974    
1975     /* MTHI */
1976     DECLARE_INSN(MTHI)
1977     {
1978     int rs = bits(insn,21,25);
1979    
1980     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
1981    
1982     amd64_mov_membase_reg(b->jit_ptr,
1983     AMD64_R15,OFFSET(cpu_mips_t,hi),AMD64_RDX,8);
1984     return(0);
1985     }
1986    
1987     /* MTLO */
1988     DECLARE_INSN(MTLO)
1989     {
1990     int rs = bits(insn,21,25);
1991    
1992     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
1993    
1994     amd64_mov_membase_reg(b->jit_ptr,
1995     AMD64_R15,OFFSET(cpu_mips_t,lo),AMD64_RDX,8);
1996     return(0);
1997     }
1998    
1999     /* MUL */
2000     DECLARE_INSN(MUL)
2001     {
2002     int rs = bits(insn,21,25);
2003     int rt = bits(insn,16,20);
2004     int rd = bits(insn,11,15);
2005    
2006     /* eax = gpr[rs] */
2007     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
2008    
2009     /* ecx = gpr[rt] */
2010     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
2011    
2012     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,1,4);
2013    
2014     /* store result in gpr[rd] */
2015     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2016     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2017     return(0);
2018     }
2019    
2020     /* MULT */
2021     DECLARE_INSN(MULT)
2022     {
2023     int rs = bits(insn,21,25);
2024     int rt = bits(insn,16,20);
2025    
2026     /* eax = gpr[rs] */
2027     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
2028    
2029     /* ecx = gpr[rt] */
2030     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
2031    
2032     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,1,4);
2033    
2034     /* store LO */
2035     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2036     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
2037     AMD64_RAX,8);
2038    
2039     /* store HI */
2040     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
2041     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
2042     AMD64_RDX,8);
2043     return(0);
2044     }
2045    
2046     /* MULTU */
2047     DECLARE_INSN(MULTU)
2048     {
2049     int rs = bits(insn,21,25);
2050     int rt = bits(insn,16,20);
2051    
2052     /* eax = gpr[rs] */
2053     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
2054    
2055     /* ecx = gpr[rt] */
2056     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
2057    
2058     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,0,4);
2059    
2060     /* store LO */
2061     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2062     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
2063     AMD64_RAX,8);
2064    
2065     /* store HI */
2066     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
2067     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
2068     AMD64_RDX,8);
2069     return(0);
2070     }
2071    
2072     /* NOP */
2073     DECLARE_INSN(NOP)
2074     {
2075     return(0);
2076     }
2077    
2078     /* NOR */
2079     DECLARE_INSN(NOR)
2080     {
2081     int rs = bits(insn,21,25);
2082     int rt = bits(insn,16,20);
2083     int rd = bits(insn,11,15);
2084    
2085     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2086     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,AMD64_R15,
2087     REG_OFFSET(rt));
2088     amd64_not_reg(b->jit_ptr,AMD64_RAX);
2089     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2090     return(0);
2091     }
2092    
2093     /* OR */
2094     DECLARE_INSN(OR)
2095     {
2096     int rs = bits(insn,21,25);
2097     int rt = bits(insn,16,20);
2098     int rd = bits(insn,11,15);
2099    
2100     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2101     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,AMD64_R15,
2102     REG_OFFSET(rt));
2103     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2104     return(0);
2105     }
2106    
2107     /* ORI */
2108     DECLARE_INSN(ORI)
2109     {
2110     int rs = bits(insn,21,25);
2111     int rt = bits(insn,16,20);
2112     int imm = bits(insn,0,15);
2113    
2114     mips64_load_imm(b,AMD64_RAX,imm);
2115    
2116     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,
2117     AMD64_R15,REG_OFFSET(rs));
2118    
2119     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
2120     return(0);
2121     }
2122    
2123     /* PREF */
2124     DECLARE_INSN(PREF)
2125     {
2126     amd64_nop(b->jit_ptr);
2127     return(0);
2128     }
2129    
2130     /* PREFI */
2131     DECLARE_INSN(PREFI)
2132     {
2133     amd64_nop(b->jit_ptr);
2134     return(0);
2135     }
2136    
2137     /* SB (Store Byte) */
2138     DECLARE_INSN(SB)
2139     {
2140     int base = bits(insn,21,25);
2141     int rt = bits(insn,16,20);
2142     int offset = bits(insn,0,15);
2143    
2144     mips64_emit_memop(b,MIPS_MEMOP_SB,base,offset,rt,FALSE);
2145     return(0);
2146     }
2147    
2148     /* SC (Store Conditional) */
2149     DECLARE_INSN(SC)
2150     {
2151     int base = bits(insn,21,25);
2152     int rt = bits(insn,16,20);
2153     int offset = bits(insn,0,15);
2154    
2155     mips64_emit_memop(b,MIPS_MEMOP_SC,base,offset,rt,TRUE);
2156     return(0);
2157     }
2158    
2159     /* SD (Store Double-Word) */
2160     DECLARE_INSN(SD)
2161     {
2162     int base = bits(insn,21,25);
2163     int rt = bits(insn,16,20);
2164     int offset = bits(insn,0,15);
2165    
2166     mips64_emit_memop(b,MIPS_MEMOP_SD,base,offset,rt,FALSE);
2167     return(0);
2168     }
2169    
2170     /* SDL (Store Double-Word Left) */
2171     DECLARE_INSN(SDL)
2172     {
2173     int base = bits(insn,21,25);
2174     int rt = bits(insn,16,20);
2175     int offset = bits(insn,0,15);
2176    
2177     mips64_emit_memop(b,MIPS_MEMOP_SDL,base,offset,rt,FALSE);
2178     return(0);
2179     }
2180    
2181     /* SDR (Store Double-Word Right) */
2182     DECLARE_INSN(SDR)
2183     {
2184     int base = bits(insn,21,25);
2185     int rt = bits(insn,16,20);
2186     int offset = bits(insn,0,15);
2187    
2188     mips64_emit_memop(b,MIPS_MEMOP_SDR,base,offset,rt,FALSE);
2189     return(0);
2190     }
2191    
2192     /* SDC1 (Store Double-Word from Coprocessor 1) */
2193     DECLARE_INSN(SDC1)
2194     {
2195     int base = bits(insn,21,25);
2196     int ft = bits(insn,16,20);
2197     int offset = bits(insn,0,15);
2198    
2199     mips64_emit_memop(b,MIPS_MEMOP_SDC1,base,offset,ft,FALSE);
2200     return(0);
2201     }
2202    
2203     /* SH (Store Half-Word) */
2204     DECLARE_INSN(SH)
2205     {
2206     int base = bits(insn,21,25);
2207     int rt = bits(insn,16,20);
2208     int offset = bits(insn,0,15);
2209    
2210     mips64_emit_memop(b,MIPS_MEMOP_SH,base,offset,rt,FALSE);
2211     return(0);
2212     }
2213    
2214     /* SLL */
2215     DECLARE_INSN(SLL)
2216     {
2217     int rt = bits(insn,16,20);
2218     int rd = bits(insn,11,15);
2219     int sa = bits(insn,6,10);
2220    
2221     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2222     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa);
2223    
2224     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2225     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2226     return(0);
2227     }
2228    
2229     /* SLLV */
2230     DECLARE_INSN(SLLV)
2231     {
2232     int rs = bits(insn,21,25);
2233     int rt = bits(insn,16,20);
2234     int rd = bits(insn,11,15);
2235    
2236     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2237     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2238    
2239     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2240     amd64_shift_reg(b->jit_ptr,X86_SHL,AMD64_RAX);
2241    
2242     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2243     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2244     return(0);
2245     }
2246    
2247     /* SLT */
2248     DECLARE_INSN(SLT)
2249     {
2250     int rs = bits(insn,21,25);
2251     int rt = bits(insn,16,20);
2252     int rd = bits(insn,11,15);
2253     u_char *test1;
2254    
2255     /* RDX = gpr[rs] */
2256     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
2257    
2258     /* RAX = gpr[rt] */
2259     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
2260    
2261     /* we set rd to 1 when gpr[rs] < gpr[rt] */
2262     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2263     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
2264    
2265     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RDX,AMD64_RAX);
2266     test1 = b->jit_ptr;
2267     amd64_branch8(b->jit_ptr, X86_CC_GE, 0, 1);
2268    
2269     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rd));
2270    
2271     /* end */
2272     amd64_patch(test1,b->jit_ptr);
2273     return(0);
2274     }
2275    
2276     /* SLTI */
2277     DECLARE_INSN(SLTI)
2278     {
2279     int rs = bits(insn,21,25);
2280     int rt = bits(insn,16,20);
2281     int imm = bits(insn,0,15);
2282     m_uint64_t val = sign_extend(imm,16);
2283     u_char *test1;
2284    
2285     /* RDX = val */
2286     mips64_load_imm(b,AMD64_RDX,val);
2287    
2288     /* RAX = gpr[rs] */
2289     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2290    
2291     /* we set rt to 1 when gpr[rs] < val */
2292     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2293     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
2294    
2295     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2296     test1 = b->jit_ptr;
2297     amd64_branch8(b->jit_ptr, X86_CC_GE, 0, 1);
2298    
2299     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rt));
2300    
2301     /* end */
2302     amd64_patch(test1,b->jit_ptr);
2303     return(0);
2304     }
2305    
2306     /* SLTU */
2307     DECLARE_INSN(SLTU)
2308     {
2309     int rs = bits(insn,21,25);
2310     int rt = bits(insn,16,20);
2311     int rd = bits(insn,11,15);
2312     u_char *test1;
2313    
2314     /* RDX = gpr[rs] */
2315     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
2316    
2317     /* RAX = gpr[rt] */
2318     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
2319    
2320     /* we set rd to 1 when gpr[rs] < gpr[rt] */
2321     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2322     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
2323    
2324     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RDX,AMD64_RAX);
2325     test1 = b->jit_ptr;
2326     amd64_branch8(b->jit_ptr, X86_CC_AE, 0, 0);
2327    
2328     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rd));
2329    
2330     /* end */
2331     amd64_patch(test1,b->jit_ptr);
2332     return(0);
2333     }
2334    
2335     /* SLTIU */
2336     DECLARE_INSN(SLTIU)
2337     {
2338     int rs = bits(insn,21,25);
2339     int rt = bits(insn,16,20);
2340     int imm = bits(insn,0,15);
2341     m_uint64_t val = sign_extend(imm,16);
2342     u_char *test1;
2343    
2344     /* RDX = val */
2345     mips64_load_imm(b,AMD64_RDX,val);
2346    
2347     /* RAX = gpr[rs] */
2348     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2349    
2350     /* we set rt to 1 when gpr[rs] < val */
2351     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2352     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
2353    
2354     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2355     test1 = b->jit_ptr;
2356     amd64_branch8(b->jit_ptr, X86_CC_AE, 0, 0);
2357    
2358     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rt));
2359    
2360     /* end */
2361     amd64_patch(test1,b->jit_ptr);
2362     return(0);
2363     }
2364    
2365     /* SRA */
2366     DECLARE_INSN(SRA)
2367     {
2368     int rt = bits(insn,16,20);
2369     int rd = bits(insn,11,15);
2370     int sa = bits(insn,6,10);
2371    
2372     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2373     amd64_shift_reg_imm_size(b->jit_ptr,X86_SAR,AMD64_RAX,sa,4);
2374    
2375     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2376     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2377     return(0);
2378     }
2379    
2380     /* SRAV */
2381     DECLARE_INSN(SRAV)
2382     {
2383     int rs = bits(insn,21,25);
2384     int rt = bits(insn,16,20);
2385     int rd = bits(insn,11,15);
2386    
2387     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2388     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2389    
2390     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2391     amd64_shift_reg_size(b->jit_ptr,X86_SAR,AMD64_RAX,4);
2392    
2393     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2394     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2395     return(0);
2396     }
2397    
2398     /* SRL */
2399     DECLARE_INSN(SRL)
2400     {
2401     int rt = bits(insn,16,20);
2402     int rd = bits(insn,11,15);
2403     int sa = bits(insn,6,10);
2404    
2405     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2406     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa);
2407    
2408     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2409     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2410     return(0);
2411     }
2412    
2413     /* SRLV */
2414     DECLARE_INSN(SRLV)
2415     {
2416     int rs = bits(insn,21,25);
2417     int rt = bits(insn,16,20);
2418     int rd = bits(insn,11,15);
2419    
2420     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2421     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2422    
2423     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2424     amd64_shift_reg(b->jit_ptr,X86_SHR,AMD64_RAX);
2425    
2426     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2427     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2428     return(0);
2429     }
2430    
2431     /* SUB */
2432     DECLARE_INSN(SUB)
2433     {
2434     int rs = bits(insn,21,25);
2435     int rt = bits(insn,16,20);
2436     int rd = bits(insn,11,15);
2437    
2438     /* TODO: Exception handling */
2439     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2440     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,AMD64_R15,
2441     REG_OFFSET(rt));
2442    
2443     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2444     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2445     return(0);
2446     }
2447    
2448     /* SUBU */
2449     DECLARE_INSN(SUBU)
2450     {
2451     int rs = bits(insn,21,25);
2452     int rt = bits(insn,16,20);
2453     int rd = bits(insn,11,15);
2454    
2455     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2456     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,AMD64_R15,
2457     REG_OFFSET(rt));
2458    
2459     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2460     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2461     return(0);
2462     }
2463    
2464     /* SW (Store Word) */
2465     DECLARE_INSN(SW)
2466     {
2467     int base = bits(insn,21,25);
2468     int rt = bits(insn,16,20);
2469     int offset = bits(insn,0,15);
2470    
2471     if (cpu->fast_memop) {
2472     mips64_emit_memop_fast(cpu,b,1,MIPS_MEMOP_SW,base,offset,rt,FALSE,
2473     mips64_memop_fast_sw);
2474     } else {
2475     mips64_emit_memop(b,MIPS_MEMOP_SW,base,offset,rt,FALSE);
2476     }
2477     return(0);
2478     }
2479    
2480     /* SWL (Store Word Left) */
2481     DECLARE_INSN(SWL)
2482     {
2483     int base = bits(insn,21,25);
2484     int rt = bits(insn,16,20);
2485     int offset = bits(insn,0,15);
2486    
2487     mips64_emit_memop(b,MIPS_MEMOP_SWL,base,offset,rt,FALSE);
2488     return(0);
2489     }
2490    
2491     /* SWR (Store Word Right) */
2492     DECLARE_INSN(SWR)
2493     {
2494     int base = bits(insn,21,25);
2495     int rt = bits(insn,16,20);
2496     int offset = bits(insn,0,15);
2497    
2498     mips64_emit_memop(b,MIPS_MEMOP_SWR,base,offset,rt,FALSE);
2499     return(0);
2500     }
2501    
2502     /* SYNC */
2503     DECLARE_INSN(SYNC)
2504     {
2505     return(0);
2506     }
2507    
2508     /* SYSCALL */
2509     DECLARE_INSN(SYSCALL)
2510     {
2511     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2512     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2513     mips64_emit_basic_c_call(b,mips64_exec_syscall);
2514     mips64_jit_tcb_push_epilog(b);
2515     return(0);
2516     }
2517    
2518     /* TEQ (Trap If Equal) */
2519     DECLARE_INSN(TEQ)
2520     {
2521     int rs = bits(insn,21,25);
2522     int rt = bits(insn,16,20);
2523     u_char *test1;
2524    
2525     /*
2526     * compare gpr[rs] and gpr[rt].
2527     */
2528     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2529     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
2530     AMD64_R15,REG_OFFSET(rt));
2531     test1 = b->jit_ptr;
2532     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2533    
2534     /* Generate trap exception */
2535     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2536     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2537     mips64_jit_tcb_push_epilog(b);
2538    
2539     /* end */
2540     amd64_patch(test1,b->jit_ptr);
2541     return(0);
2542     }
2543    
2544     /* TEQI (Trap If Equal Immediate) */
2545     DECLARE_INSN(TEQI)
2546     {
2547     int rs = bits(insn,21,25);
2548     int imm = bits(insn,0,15);
2549     m_uint64_t val = sign_extend(imm,16);
2550     u_char *test1;
2551    
2552     /* RDX = val */
2553     mips64_load_imm(b,AMD64_RDX,val);
2554    
2555     /* RAX = gpr[rs] */
2556     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2557    
2558     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2559     test1 = b->jit_ptr;
2560     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2561    
2562     /* Generate trap exception */
2563     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2564     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2565     mips64_jit_tcb_push_epilog(b);
2566    
2567     /* end */
2568     amd64_patch(test1,b->jit_ptr);
2569     return(0);
2570     }
2571    
2572     /* TLBP */
2573     DECLARE_INSN(TLBP)
2574     {
2575     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2576     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2577     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbp);
2578     return(0);
2579     }
2580    
2581     /* TLBR */
2582     DECLARE_INSN(TLBR)
2583     {
2584     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2585     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2586     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbr);
2587     return(0);
2588     }
2589    
2590     /* TLBWI */
2591     DECLARE_INSN(TLBWI)
2592     {
2593     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2594     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2595     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbwi);
2596     return(0);
2597     }
2598    
2599     /* TLBWR */
2600     DECLARE_INSN(TLBWR)
2601     {
2602     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2603     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2604     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbwr);
2605     return(0);
2606     }
2607    
2608     /* XOR */
2609     DECLARE_INSN(XOR)
2610     {
2611     int rs = bits(insn,21,25);
2612     int rt = bits(insn,16,20);
2613     int rd = bits(insn,11,15);
2614    
2615     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2616     amd64_alu_reg_membase(b->jit_ptr,X86_XOR,AMD64_RAX,AMD64_R15,
2617     REG_OFFSET(rt));
2618     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2619     return(0);
2620     }
2621    
2622     /* XORI */
2623     DECLARE_INSN(XORI)
2624     {
2625     int rs = bits(insn,21,25);
2626     int rt = bits(insn,16,20);
2627     int imm = bits(insn,0,15);
2628    
2629     mips64_load_imm(b,AMD64_RAX,imm);
2630    
2631     amd64_alu_reg_membase(b->jit_ptr,X86_XOR,AMD64_RAX,
2632     AMD64_R15,REG_OFFSET(rs));
2633    
2634     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
2635     return(0);
2636     }
2637    
2638     /* MIPS instruction array */
2639     struct mips64_insn_tag mips64_insn_tags[] = {
2640     { mips64_emit_LI , 0xffe00000 , 0x24000000, 1 }, /* virtual */
2641     { mips64_emit_MOVE , 0xfc1f07ff , 0x00000021, 1 }, /* virtual */
2642     { mips64_emit_B , 0xffff0000 , 0x10000000, 0 }, /* virtual */
2643     { mips64_emit_BAL , 0xffff0000 , 0x04110000, 0 }, /* virtual */
2644     { mips64_emit_BEQZ , 0xfc1f0000 , 0x10000000, 0 }, /* virtual */
2645     { mips64_emit_BNEZ , 0xfc1f0000 , 0x14000000, 0 }, /* virtual */
2646     { mips64_emit_ADD , 0xfc0007ff , 0x00000020, 1 },
2647     { mips64_emit_ADDI , 0xfc000000 , 0x20000000, 1 },
2648     { mips64_emit_ADDIU , 0xfc000000 , 0x24000000, 1 },
2649     { mips64_emit_ADDU , 0xfc0007ff , 0x00000021, 1 },
2650     { mips64_emit_AND , 0xfc0007ff , 0x00000024, 1 },
2651     { mips64_emit_ANDI , 0xfc000000 , 0x30000000, 1 },
2652     { mips64_emit_BEQ , 0xfc000000 , 0x10000000, 0 },
2653     { mips64_emit_BEQL , 0xfc000000 , 0x50000000, 0 },
2654     { mips64_emit_BGEZ , 0xfc1f0000 , 0x04010000, 0 },
2655     { mips64_emit_BGEZAL , 0xfc1f0000 , 0x04110000, 0 },
2656     { mips64_emit_BGEZALL , 0xfc1f0000 , 0x04130000, 0 },
2657     { mips64_emit_BGEZL , 0xfc1f0000 , 0x04030000, 0 },
2658     { mips64_emit_BGTZ , 0xfc1f0000 , 0x1c000000, 0 },
2659     { mips64_emit_BGTZL , 0xfc1f0000 , 0x5c000000, 0 },
2660     { mips64_emit_BLEZ , 0xfc1f0000 , 0x18000000, 0 },
2661     { mips64_emit_BLEZL , 0xfc1f0000 , 0x58000000, 0 },
2662     { mips64_emit_BLTZ , 0xfc1f0000 , 0x04000000, 0 },
2663     { mips64_emit_BLTZAL , 0xfc1f0000 , 0x04100000, 0 },
2664     { mips64_emit_BLTZALL , 0xfc1f0000 , 0x04120000, 0 },
2665     { mips64_emit_BLTZL , 0xfc1f0000 , 0x04020000, 0 },
2666     { mips64_emit_BNE , 0xfc000000 , 0x14000000, 0 },
2667     { mips64_emit_BNEL , 0xfc000000 , 0x54000000, 0 },
2668     { mips64_emit_BREAK , 0xfc00003f , 0x0000000d, 1 },
2669     { mips64_emit_CACHE , 0xfc000000 , 0xbc000000, 1 },
2670     { mips64_emit_CFC0 , 0xffe007ff , 0x40400000, 1 },
2671     { mips64_emit_CTC0 , 0xffe007ff , 0x40600000, 1 },
2672     { mips64_emit_DADDIU , 0xfc000000 , 0x64000000, 1 },
2673     { mips64_emit_DADDU , 0xfc0007ff , 0x0000002d, 1 },
2674     { mips64_emit_DIV , 0xfc00ffff , 0x0000001a, 1 },
2675     { mips64_emit_DIVU , 0xfc00ffff , 0x0000001b, 1 },
2676     { mips64_emit_DMFC0 , 0xffe007f8 , 0x40200000, 1 },
2677     { mips64_emit_DMFC1 , 0xffe007ff , 0x44200000, 1 },
2678     { mips64_emit_DMTC0 , 0xffe007f8 , 0x40a00000, 1 },
2679     { mips64_emit_DMTC1 , 0xffe007ff , 0x44a00000, 1 },
2680     { mips64_emit_DSLL , 0xffe0003f , 0x00000038, 1 },
2681     { mips64_emit_DSLL32 , 0xffe0003f , 0x0000003c, 1 },
2682     { mips64_emit_DSLLV , 0xfc0007ff , 0x00000014, 1 },
2683     { mips64_emit_DSRA , 0xffe0003f , 0x0000003b, 1 },
2684     { mips64_emit_DSRA32 , 0xffe0003f , 0x0000003f, 1 },
2685     { mips64_emit_DSRAV , 0xfc0007ff , 0x00000017, 1 },
2686     { mips64_emit_DSRL , 0xffe0003f , 0x0000003a, 1 },
2687     { mips64_emit_DSRL32 , 0xffe0003f , 0x0000003e, 1 },
2688     { mips64_emit_DSRLV , 0xfc0007ff , 0x00000016, 1 },
2689     { mips64_emit_DSUBU , 0xfc0007ff , 0x0000002f, 1 },
2690     { mips64_emit_ERET , 0xffffffff , 0x42000018, 0 },
2691     { mips64_emit_J , 0xfc000000 , 0x08000000, 0 },
2692     { mips64_emit_JAL , 0xfc000000 , 0x0c000000, 0 },
2693     { mips64_emit_JALR , 0xfc1f003f , 0x00000009, 0 },
2694     { mips64_emit_JR , 0xfc1ff83f , 0x00000008, 0 },
2695     { mips64_emit_LB , 0xfc000000 , 0x80000000, 1 },
2696     { mips64_emit_LBU , 0xfc000000 , 0x90000000, 1 },
2697     { mips64_emit_LD , 0xfc000000 , 0xdc000000, 1 },
2698     { mips64_emit_LDC1 , 0xfc000000 , 0xd4000000, 1 },
2699     { mips64_emit_LDL , 0xfc000000 , 0x68000000, 1 },
2700     { mips64_emit_LDR , 0xfc000000 , 0x6c000000, 1 },
2701     { mips64_emit_LH , 0xfc000000 , 0x84000000, 1 },
2702     { mips64_emit_LHU , 0xfc000000 , 0x94000000, 1 },
2703     { mips64_emit_LL , 0xfc000000 , 0xc0000000, 1 },
2704     { mips64_emit_LUI , 0xffe00000 , 0x3c000000, 1 },
2705     { mips64_emit_LW , 0xfc000000 , 0x8c000000, 1 },
2706     { mips64_emit_LWL , 0xfc000000 , 0x88000000, 1 },
2707     { mips64_emit_LWR , 0xfc000000 , 0x98000000, 1 },
2708     { mips64_emit_LWU , 0xfc000000 , 0x9c000000, 1 },
2709     { mips64_emit_MFC0 , 0xffe007ff , 0x40000000, 1 },
2710     { mips64_emit_CFC0 , 0xffe007ff , 0x40000001, 1 }, /* MFC0 / Set 1 */
2711     { mips64_emit_MFC1 , 0xffe007ff , 0x44000000, 1 },
2712     { mips64_emit_MFHI , 0xffff07ff , 0x00000010, 1 },
2713     { mips64_emit_MFLO , 0xffff07ff , 0x00000012, 1 },
2714     { mips64_emit_MTC0 , 0xffe007ff , 0x40800000, 1 },
2715     { mips64_emit_MTC1 , 0xffe007ff , 0x44800000, 1 },
2716     { mips64_emit_MTHI , 0xfc1fffff , 0x00000011, 1 },
2717     { mips64_emit_MTLO , 0xfc1fffff , 0x00000013, 1 },
2718     { mips64_emit_MUL , 0xfc0007ff , 0x70000002, 1 },
2719     { mips64_emit_MULT , 0xfc00ffff , 0x00000018, 1 },
2720     { mips64_emit_MULTU , 0xfc00ffff , 0x00000019, 1 },
2721     { mips64_emit_NOP , 0xffffffff , 0x00000000, 1 },
2722     { mips64_emit_NOR , 0xfc0007ff , 0x00000027, 1 },
2723     { mips64_emit_OR , 0xfc0007ff , 0x00000025, 1 },
2724     { mips64_emit_ORI , 0xfc000000 , 0x34000000, 1 },
2725     { mips64_emit_PREF , 0xfc000000 , 0xcc000000, 1 },
2726     { mips64_emit_PREFI , 0xfc0007ff , 0x4c00000f, 1 },
2727     { mips64_emit_SB , 0xfc000000 , 0xa0000000, 1 },
2728     { mips64_emit_SC , 0xfc000000 , 0xe0000000, 1 },
2729     { mips64_emit_SD , 0xfc000000 , 0xfc000000, 1 },
2730     { mips64_emit_SDC1 , 0xfc000000 , 0xf4000000, 1 },
2731     { mips64_emit_SDL , 0xfc000000 , 0xb0000000, 1 },
2732     { mips64_emit_SDR , 0xfc000000 , 0xb4000000, 1 },
2733     { mips64_emit_SH , 0xfc000000 , 0xa4000000, 1 },
2734     { mips64_emit_SLL , 0xffe0003f , 0x00000000, 1 },
2735     { mips64_emit_SLLV , 0xfc0007ff , 0x00000004, 1 },
2736     { mips64_emit_SLT , 0xfc0007ff , 0x0000002a, 1 },
2737     { mips64_emit_SLTI , 0xfc000000 , 0x28000000, 1 },
2738     { mips64_emit_SLTIU , 0xfc000000 , 0x2c000000, 1 },
2739     { mips64_emit_SLTU , 0xfc0007ff , 0x0000002b, 1 },
2740     { mips64_emit_SRA , 0xffe0003f , 0x00000003, 1 },
2741     { mips64_emit_SRAV , 0xfc0007ff , 0x00000007, 1 },
2742     { mips64_emit_SRL , 0xffe0003f , 0x00000002, 1 },
2743     { mips64_emit_SRLV , 0xfc0007ff , 0x00000006, 1 },
2744     { mips64_emit_SUB , 0xfc0007ff , 0x00000022, 1 },
2745     { mips64_emit_SUBU , 0xfc0007ff , 0x00000023, 1 },
2746     { mips64_emit_SW , 0xfc000000 , 0xac000000, 1 },
2747     { mips64_emit_SWL , 0xfc000000 , 0xa8000000, 1 },
2748     { mips64_emit_SWR , 0xfc000000 , 0xb8000000, 1 },
2749     { mips64_emit_SYNC , 0xfffff83f , 0x0000000f, 1 },
2750     { mips64_emit_SYSCALL , 0xfc00003f , 0x0000000c, 1 },
2751     { mips64_emit_TEQ , 0xfc00003f , 0x00000034, 1 },
2752     { mips64_emit_TEQI , 0xfc1f0000 , 0x040c0000, 1 },
2753     { mips64_emit_TLBP , 0xffffffff , 0x42000008, 1 },
2754     { mips64_emit_TLBR , 0xffffffff , 0x42000001, 1 },
2755     { mips64_emit_TLBWI , 0xffffffff , 0x42000002, 1 },
2756     { mips64_emit_TLBWR , 0xffffffff , 0x42000006, 1 },
2757     { mips64_emit_XOR , 0xfc0007ff , 0x00000026, 1 },
2758     { mips64_emit_XORI , 0xfc000000 , 0x38000000, 1 },
2759     { mips64_emit_unknown , 0x00000000 , 0x00000000, 1 },
2760 dpavlin 8 { NULL , 0x00000000 , 0x00000000, 0 },
2761 dpavlin 7 };

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