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/* |
/* |
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* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
*/ |
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/* Device ID mask and shift, device offset mask */ |
/* Device ID mask and shift, device offset mask */ |
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#define MTS_DEVID_MASK 0xfc000000 |
#define MTS_DEVID_MASK 0xfc000000 |
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#define MTS_DEVID_SHIFT 26 |
#define MTS_DEVID_SHIFT 26 |
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#define MTS_DEVOFF_MASK 0x03fffff0 |
#define MTS_DEVOFF_MASK 0x03ffffff |
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/* Memory access flags */ |
/* Memory access flags */ |
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#define MTS_ACC_OK 0x00000000 /* Access OK */ |
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#define MTS_ACC_AE 0x00000002 /* Address Error */ |
#define MTS_ACC_AE 0x00000002 /* Address Error */ |
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#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
#define MTS_ACC_T 0x00000004 /* TLB Exception */ |
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#define MTS_ACC_U 0x00000006 /* Unexistent */ |
#define MTS_ACC_U 0x00000006 /* Unexistent */ |
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/* Hash table size for MTS64 (default: [shift:16,bits:12]) */ |
/* Hash table size for MTS64 (default: [shift:16,bits:12]) */ |
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#define MTS64_HASH_SHIFT 15 |
#define MTS64_HASH_SHIFT 12 |
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#define MTS64_HASH_BITS 15 |
#define MTS64_HASH_BITS 14 |
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#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS) |
#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS) |
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#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1) |
#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1) |
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#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK) |
#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK) |
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/* Hash table size for MTS32 (default: [shift:15,bits:15]) */ |
/* Hash table size for MTS32 (default: [shift:15,bits:15]) */ |
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#define MTS32_HASH_SHIFT 15 |
#define MTS32_HASH_SHIFT 12 |
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#define MTS32_HASH_BITS 15 |
#define MTS32_HASH_BITS 14 |
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#define MTS32_HASH_SIZE (1 << MTS32_HASH_BITS) |
#define MTS32_HASH_SIZE (1 << MTS32_HASH_BITS) |
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#define MTS32_HASH_MASK (MTS32_HASH_SIZE - 1) |
#define MTS32_HASH_MASK (MTS32_HASH_SIZE - 1) |
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u_int count; |
u_int count; |
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}; |
}; |
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/* Show the last memory accesses */ |
/* Record a memory access */ |
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void memlog_dump(cpu_mips_t *cpu); |
void memlog_rec_access(cpu_gen_t *cpu,m_uint64_t vaddr,m_uint64_t data, |
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m_uint32_t op_size,m_uint32_t op_type); |
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/* Shutdown MTS subsystem */ |
/* Show the last memory accesses */ |
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void mts_shutdown(cpu_mips_t *cpu); |
void memlog_dump(cpu_gen_t *cpu); |
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/* Set the address mode */ |
/* Update the data obtained by a read access */ |
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int mts_set_addr_mode(cpu_mips_t *cpu,u_int addr_mode); |
void memlog_update_read(cpu_gen_t *cpu,m_iptr_t raddr); |
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/* Copy a memory block from VM physical RAM to real host */ |
/* Copy a memory block from VM physical RAM to real host */ |
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void physmem_copy_from_vm(vm_instance_t *vm,void *real_buffer, |
void physmem_copy_from_vm(vm_instance_t *vm,void *real_buffer, |
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/* Copy a 16-bit word to the VM physical RAM from real host */ |
/* Copy a 16-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u16_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint16_t val); |
void physmem_copy_u16_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint16_t val); |
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/* Copy a byte from the VM physical RAM to real host */ |
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m_uint8_t physmem_copy_u8_from_vm(vm_instance_t *vm,m_uint64_t paddr); |
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/* Copy a 16-bit word to the VM physical RAM from real host */ |
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void physmem_copy_u8_to_vm(vm_instance_t *vm,m_uint64_t paddr,m_uint8_t val); |
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/* DMA transfer operation */ |
/* DMA transfer operation */ |
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void physmem_dma_transfer(vm_instance_t *vm,m_uint64_t src,m_uint64_t dst, |
void physmem_dma_transfer(vm_instance_t *vm,m_uint64_t src,m_uint64_t dst, |
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size_t len); |
size_t len); |