/[dynamips]/trunk/dev_pa_mc8te1.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_pa_mc8te1.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_pa_mc8te1.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PA-MC-8TE1 card. Doesn't work at this time.   * PA-MC-8TE1 card. Doesn't work at this time.
# Line 13  Line 13 
13  #include <pthread.h>  #include <pthread.h>
14  #include <assert.h>  #include <assert.h>
15    
16  #include "mips64.h"  #include "cpu.h"
17    #include "vm.h"
18  #include "dynamips.h"  #include "dynamips.h"
19  #include "memory.h"  #include "memory.h"
20  #include "device.h"  #include "device.h"
# Line 65  struct pa_mc_data { Line 66  struct pa_mc_data {
66  /*  /*
67   * dev_ssram_access   * dev_ssram_access
68   */   */
69  static void *dev_ssram_access(cpu_mips_t *cpu,struct vdevice *dev,  static void *dev_ssram_access(cpu_gen_t *cpu,struct vdevice *dev,
70                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
71                                m_uint64_t *data)                                m_uint64_t *data)
72  {  {
# Line 81  static void *dev_ssram_access(cpu_mips_t Line 82  static void *dev_ssram_access(cpu_mips_t
82     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
83        cpu_log(cpu,d->name,        cpu_log(cpu,d->name,
84                "read  access to offset = 0x%x, pc = 0x%llx (size=%u)\n",                "read  access to offset = 0x%x, pc = 0x%llx (size=%u)\n",
85                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
86     } else {     } else {
87        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
88                "val = 0x%llx (size=%u)\n",offset,cpu->pc,*data,op_size);                "val = 0x%llx (size=%u)\n",
89                  offset,cpu_get_pc(cpu),*data,op_size);
90     }     }
91  #endif  #endif
92    
# Line 140  static void plx9054_doorbell_callback(st Line 142  static void plx9054_doorbell_callback(st
142  /*  /*
143   * pa_mc8te1_access()   * pa_mc8te1_access()
144   */   */
145  static void *pa_mc8te1_access(cpu_mips_t *cpu,struct vdevice *dev,  static void *pa_mc8te1_access(cpu_gen_t *cpu,struct vdevice *dev,
146                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
147                                m_uint64_t *data)                                m_uint64_t *data)
148  {  {
# Line 152  static void *pa_mc8te1_access(cpu_mips_t Line 154  static void *pa_mc8te1_access(cpu_mips_t
154  #if DEBUG_ACCESS  #if DEBUG_ACCESS
155     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
156        cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx\n",        cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx\n",
157                offset,cpu->pc);                offset,cpu_get_pc(cpu));
158     } else {     } else {
159        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
160                "val = 0x%llx\n",offset,cpu->pc,*data);                "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
161     }     }
162  #endif  #endif
163    
# Line 166  static void *pa_mc8te1_access(cpu_mips_t Line 168  static void *pa_mc8te1_access(cpu_mips_t
168           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
169              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
170                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
171                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
172           } else {           } else {
173              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
174                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
175                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
176                        offset,*data,cpu_get_pc(cpu),op_size);
177           }           }
178  #endif  #endif
179     }     }
# Line 181  static void *pa_mc8te1_access(cpu_mips_t Line 184  static void *pa_mc8te1_access(cpu_mips_t
184  /*  /*
185   * pci_pos_read()   * pci_pos_read()
186   */   */
187  static m_uint32_t pci_pos_read(cpu_mips_t *cpu,struct pci_device *dev,int reg)  static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg)
188  {  {
189     struct pa_mc_data *d = dev->priv_data;     struct pa_mc_data *d = dev->priv_data;
190    
# Line 200  static m_uint32_t pci_pos_read(cpu_mips_ Line 203  static m_uint32_t pci_pos_read(cpu_mips_
203  /*  /*
204   * pci_pos_write()   * pci_pos_write()
205   */   */
206  static void pci_pos_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev,
207                            int reg,m_uint32_t value)                            int reg,m_uint32_t value)
208  {  {
209     struct pa_mc_data *d = dev->priv_data;     struct pa_mc_data *d = dev->priv_data;
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