--- upstream/dynamips-0.2.6-RC4/dev_pa_a1.c	2007/10/06 16:08:03	5
+++ upstream/dynamips-0.2.7-RC3/dev_pa_a1.c	2007/10/06 16:26:06	9
@@ -1,5 +1,5 @@
 /*  
- * Cisco C7200 (Predator) Simulation Platform.
+ * Cisco router simulation platform.
  * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.
  *
  * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.
@@ -35,7 +35,8 @@
 
 #include "crc.h"
 #include "atm.h"
-#include "mips64.h"
+#include "cpu.h"
+#include "vm.h"
 #include "dynamips.h"
 #include "memory.h"
 #include "device.h"
@@ -284,6 +285,9 @@
 struct pa_a1_data {
    char *name;
 
+   /* IRQ clearing counter */
+   u_int irq_clear_count;
+
    /* Control Memory pointer */
    m_uint32_t *ctrl_mem_ptr;
 
@@ -335,10 +339,20 @@
 /* Reset the TI1570 (forward declaration) */
 static void ti1570_reset(struct pa_a1_data *d,int clear_ctrl_mem);
 
+/* Update the interrupt status */
+static inline void dev_pa_a1_update_irq_status(struct pa_a1_data *d)
+{
+   if (d->iregs[TI1570_REG_STATUS] & d->iregs[TI1570_REG_IMASK]) {
+      pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
+   } else {
+      pci_dev_clear_irq(d->vm,d->pci_dev_ti);
+   }
+}
+
 /*
  * dev_pa_a1_access()
  */
-void *dev_pa_a1_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,
+void *dev_pa_a1_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
                        u_int op_size,u_int op_type,m_uint64_t *data)
 {
    struct pa_a1_data *d = dev->priv_data;
@@ -349,15 +363,30 @@
 #if DEBUG_ACCESS
    if (op_type == MTS_READ) {
       cpu_log(cpu,"TI1570","read  access to offset = 0x%x, pc = 0x%llx\n",
-              offset,cpu->pc);
+              offset,cpu_get_pc(cpu));
    } else {
       cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "
-              "val = 0x%llx\n",offset,cpu->pc,*data);
+              "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
    }
 #endif   
 
    /* Specific cases */
    switch(offset) {
+      /* Status register */
+      case 0x3204:
+         if (op_type == MTS_READ) {
+            *data = d->iregs[TI1570_REG_STATUS];
+
+            if (++d->irq_clear_count == 2) {
+               d->iregs[TI1570_REG_STATUS] &= ~0x3FF;
+               d->irq_clear_count = 0;
+            }
+
+            dev_pa_a1_update_irq_status(d);
+         }
+         break;
+
+      /* Software Reset register */
       case 0x3238:
          TI1570_LOG(d,"reset issued.\n");
          ti1570_reset(d,FALSE);
@@ -384,10 +413,10 @@
 #if DEBUG_UNKNOWN
    if (op_type == MTS_READ) {
       cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
-              offset,cpu->pc,op_size);
+              offset,cpu_get_pc(cpu),op_size);
    } else {
       cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "
-              "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);
+              "pc=0x%llx (size=%u)\n",offset,*data,cpu_get_pc(cpu),op_size);
    }
 #endif
    return NULL;
@@ -887,11 +916,11 @@
    /* Generate an interrupt if required */
    if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT) 
    {
-      if (((d->iregs[TI1570_REG_STATUS] & TI1570_CFG_BP_SEL) && buf_end) ||
+      if (((d->iregs[TI1570_REG_CONFIG] & TI1570_CFG_BP_SEL) && buf_end) ||
           pkt_end)
       {
          d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_TX;
-         pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
+         dev_pa_a1_update_irq_status(d);
       }
    }
 
@@ -1024,7 +1053,7 @@
 
       /* generate the appropriate IRQ */
       d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_RX;
-      pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
+      dev_pa_a1_update_irq_status(d);
    } else  {
       rcr_end = (d->iregs[TI1570_REG_RX_CRING_SIZE] >> 16);
       rcr_end &= TI1570_RCR_SIZE_MASK;
@@ -1428,7 +1457,7 @@
 /*
  * pci_ti1570_read()
  */
-static m_uint32_t pci_ti1570_read(cpu_mips_t *cpu,struct pci_device *dev,
+static m_uint32_t pci_ti1570_read(cpu_gen_t *cpu,struct pci_device *dev,
                                   int reg)
 {
    struct pa_a1_data *d = dev->priv_data;
@@ -1448,7 +1477,7 @@
 /*
  * pci_ti1570_write()
  */
-static void pci_ti1570_write(cpu_mips_t *cpu,struct pci_device *dev,
+static void pci_ti1570_write(cpu_gen_t *cpu,struct pci_device *dev,
                              int reg,m_uint32_t value)
 {
    struct pa_a1_data *d = dev->priv_data;
@@ -1468,9 +1497,11 @@
 /*
  * pci_plx9060es_read()
  */
-static m_uint32_t pci_plx9060es_read(cpu_mips_t *cpu,struct pci_device *dev,
+static m_uint32_t pci_plx9060es_read(cpu_gen_t *cpu,struct pci_device *dev,
                                      int reg)
 {
+   struct pa_a1_data *d = dev->priv_data;
+
 #if DEBUG_ACCESS
    TI1570_LOG(d,"PLX9060ES","read reg 0x%x\n",reg);
 #endif
@@ -1483,9 +1514,11 @@
 /*
  * pci_plx9060es_write()
  */
-static void pci_plx9060es_write(cpu_mips_t *cpu,struct pci_device *dev,
+static void pci_plx9060es_write(cpu_gen_t *cpu,struct pci_device *dev,
                                 int reg,m_uint32_t value)
 {
+   struct pa_a1_data *d = dev->priv_data;
+
 #if DEBUG_ACCESS
    TI1570_LOG(d,"PLX9060ES","write reg 0x%x, value 0x%x\n",reg,value);
 #endif
@@ -1532,7 +1565,7 @@
    /* Add PCI device TI1570 */
    pci_dev_ti = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
                             TI1570_PCI_VENDOR_ID,TI1570_PCI_PRODUCT_ID,
-                            0,0,C7200_NETIO_IRQ,d,
+                            0,0,c7200_net_irq_for_slot_port(pa_bay,0),d,
                             NULL,pci_ti1570_read,pci_ti1570_write);
 
    if (!pci_dev_ti) {
@@ -1545,7 +1578,7 @@
    pci_dev_plx = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
                              PLX_9060ES_PCI_VENDOR_ID,
                              PLX_9060ES_PCI_PRODUCT_ID,
-                             1,0,C7200_NETIO_IRQ,d,
+                             1,0,-1,d,
                              NULL,pci_plx9060es_read,pci_plx9060es_write);
 
    if (!pci_dev_plx) {