/[dynamips]/trunk/dev_mueslix.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_mueslix.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_mueslix.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * Serial Interfaces (Mueslix).   * Serial Interfaces (Mueslix).
# Line 36  Line 36 
36  #include <errno.h>  #include <errno.h>
37  #include <assert.h>  #include <assert.h>
38    
39  #include "mips64.h"  #include "cpu.h"
40    #include "vm.h"
41  #include "dynamips.h"  #include "dynamips.h"
42  #include "memory.h"  #include "memory.h"
43  #include "device.h"  #include "device.h"
# Line 216  static inline int dev_mueslix_is_rx_tx_e Line 217  static inline int dev_mueslix_is_rx_tx_e
217  /*  /*
218   * Access to channel registers.   * Access to channel registers.
219   */   */
220  void dev_mueslix_chan_access(cpu_mips_t *cpu,struct mueslix_channel *channel,  void dev_mueslix_chan_access(cpu_gen_t *cpu,struct mueslix_channel *channel,
221                               m_uint32_t offset,u_int op_size,u_int op_type,                               m_uint32_t offset,u_int op_size,u_int op_type,
222                               m_uint64_t *data)                               m_uint64_t *data)
223  {  {
# Line 318  static void tpu_cm1_handle_cmd(struct mu Line 319  static void tpu_cm1_handle_cmd(struct mu
319  /*  /*
320   * dev_mueslix_access()   * dev_mueslix_access()
321   */   */
322  void *dev_mueslix_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_mueslix_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
323                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
324  {  {
325     struct mueslix_data *d = dev->priv_data;     struct mueslix_data *d = dev->priv_data;
# Line 329  void *dev_mueslix_access(cpu_mips_t *cpu Line 330  void *dev_mueslix_access(cpu_mips_t *cpu
330  #if DEBUG_ACCESS >= 2  #if DEBUG_ACCESS >= 2
331     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
332        cpu_log(cpu,d->name,"read  access to offset=0x%x, pc=0x%llx, size=%u\n",        cpu_log(cpu,d->name,"read  access to offset=0x%x, pc=0x%llx, size=%u\n",
333                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
334     } else {     } else {
335        cpu_log(cpu,d->name,"write access to offset=0x%x, pc=0x%llx, "        cpu_log(cpu,d->name,"write access to offset=0x%x, pc=0x%llx, "
336                "val=0x%llx, size=%u\n",offset,cpu->pc,*data,op_size);                "val=0x%llx, size=%u\n",offset,cpu_get_pc(cpu),*data,op_size);
337     }     }
338  #endif  #endif
339    
# Line 415  void *dev_mueslix_access(cpu_mips_t *cpu Line 416  void *dev_mueslix_access(cpu_mips_t *cpu
416  #if DEBUG_ACCESS  #if DEBUG_ACCESS
417              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
418                      "channel_enable_mask = 0x%5.5llx at pc=0x%llx\n",                      "channel_enable_mask = 0x%5.5llx at pc=0x%llx\n",
419                      *data,cpu->pc);                      *data,cpu_get_pc(cpu));
420  #endif  #endif
421              d->channel_enable_mask = *data;              d->channel_enable_mask = *data;
422           }           }
# Line 448  void *dev_mueslix_access(cpu_mips_t *cpu Line 449  void *dev_mueslix_access(cpu_mips_t *cpu
449  #if DEBUG_ACCESS  #if DEBUG_ACCESS
450           if (op_type == MTS_WRITE) {           if (op_type == MTS_WRITE) {
451              cpu_log(cpu,d->name,"cmd_reg = 0x%5.5llx at pc=0x%llx\n",              cpu_log(cpu,d->name,"cmd_reg = 0x%5.5llx at pc=0x%llx\n",
452                      *data,cpu->pc);                      *data,cpu_get_pc(cpu));
453           }           }
454  #endif  #endif
455           switch(d->chip_mode) {           switch(d->chip_mode) {
# Line 475  void *dev_mueslix_access(cpu_mips_t *cpu Line 476  void *dev_mueslix_access(cpu_mips_t *cpu
476           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
477              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
478                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
479                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
480           } else {           } else {
481              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
482                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
483                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
484                        offset,*data,cpu_get_pc(cpu),op_size);
485           }           }
486  #endif  #endif
487     }     }
# Line 825  static int dev_mueslix_handle_txring(str Line 827  static int dev_mueslix_handle_txring(str
827  }  }
828    
829  /* pci_mueslix_read() */  /* pci_mueslix_read() */
830  static m_uint32_t pci_mueslix_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_mueslix_read(cpu_gen_t *cpu,struct pci_device *dev,
831                                     int reg)                                     int reg)
832  {    {  
833     struct mueslix_data *d = dev->priv_data;     struct mueslix_data *d = dev->priv_data;
# Line 841  static m_uint32_t pci_mueslix_read(cpu_m Line 843  static m_uint32_t pci_mueslix_read(cpu_m
843  }  }
844    
845  /* pci_mueslix_write() */  /* pci_mueslix_write() */
846  static void pci_mueslix_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_mueslix_write(cpu_gen_t *cpu,struct pci_device *dev,
847                                int reg,m_uint32_t value)                                int reg,m_uint32_t value)
848  {    {  
849     struct mueslix_data *d = dev->priv_data;     struct mueslix_data *d = dev->priv_data;

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