/[dynamips]/trunk/dev_gt.c
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upstream/dynamips-0.2.6-RC3/dev_gt.c revision 4 by dpavlin, Sat Oct 6 16:06:49 2007 UTC upstream/dynamips-0.2.7-RC3/dev_gt.c revision 9 by dpavlin, Sat Oct 6 16:26:06 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Galileo GT64010/GT64120A/GT96100A system controller.   * Galileo GT64010/GT64120A/GT96100A system controller.
# Line 18  Line 18 
18    
19  #include "utils.h"  #include "utils.h"
20  #include "net.h"  #include "net.h"
21  #include "mips64.h"  #include "cpu.h"
22    #include "vm.h"
23  #include "dynamips.h"  #include "dynamips.h"
24  #include "memory.h"  #include "memory.h"
25  #include "device.h"  #include "device.h"
# Line 386  static void gt_dma_handle_ctrl(struct gt Line 387  static void gt_dma_handle_ctrl(struct gt
387        *data = swap32(gt_data->dma[ch].reg_name);        *data = swap32(gt_data->dma[ch].reg_name);
388    
389  /* Handle a DMA channel */  /* Handle a DMA channel */
390  static int gt_dma_access(cpu_mips_t *cpu,struct vdevice *dev,  static int gt_dma_access(cpu_gen_t *cpu,struct vdevice *dev,
391                              m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
392                              m_uint64_t *data)                           m_uint64_t *data)
393  {  {
394     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
395    
# Line 458  static int gt_dma_access(cpu_mips_t *cpu Line 459  static int gt_dma_access(cpu_mips_t *cpu
459  /*  /*
460   * dev_gt64010_access()   * dev_gt64010_access()
461   */   */
462  void *dev_gt64010_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt64010_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
463                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
464  {  {
465     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 566  void *dev_gt64010_access(cpu_mips_t *cpu Line 567  void *dev_gt64010_access(cpu_mips_t *cpu
567        default:        default:
568           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
569              cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n",
570                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
571           } else {           } else {
572              cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, "
573                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
574           }           }
575  #endif  #endif
576     }     }
# Line 580  void *dev_gt64010_access(cpu_mips_t *cpu Line 581  void *dev_gt64010_access(cpu_mips_t *cpu
581  /*  /*
582   * dev_gt64120_access()   * dev_gt64120_access()
583   */   */
584  void *dev_gt64120_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt64120_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
585                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
586  {  {
587     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 696  void *dev_gt64120_access(cpu_mips_t *cpu Line 697  void *dev_gt64120_access(cpu_mips_t *cpu
697        default:        default:
698           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
699              cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n",
700                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
701           } else {           } else {
702              cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, "
703                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
704           }           }
705  #endif  #endif
706     }     }
# Line 710  void *dev_gt64120_access(cpu_mips_t *cpu Line 711  void *dev_gt64120_access(cpu_mips_t *cpu
711  /* Update the Ethernet port interrupt status */  /* Update the Ethernet port interrupt status */
712  static void gt_eth_update_int_status(struct gt_data *d,struct eth_port *port)  static void gt_eth_update_int_status(struct gt_data *d,struct eth_port *port)
713  {  {
714     if (port->icr & GT_ICR_MASK)     if (port->icr & port->imr & GT_ICR_MASK) {
715        port->icr |= GT_ICR_INT_SUM;        port->icr |= GT_ICR_INT_SUM;
   
    if (port->icr & port->imr & GT_ICR_MASK)  
716        vm_set_irq(d->vm,d->eth_irq);        vm_set_irq(d->vm,d->eth_irq);
717       } else {
718          port->icr &= ~GT_ICR_INT_SUM;
719          vm_clear_irq(d->vm,d->eth_irq);
720       }
721  }  }
722    
723  /* Read a MII register */  /* Read a MII register */
# Line 803  static void gt_mii_write(struct gt_data Line 806  static void gt_mii_write(struct gt_data
806  }  }
807    
808  /* Handle registers of Ethernet ports */  /* Handle registers of Ethernet ports */
809  static int gt_eth_access(cpu_mips_t *cpu,struct vdevice *dev,  static int gt_eth_access(cpu_gen_t *cpu,struct vdevice *dev,
810                           m_uint32_t offset,u_int op_size,u_int op_type,                           m_uint32_t offset,u_int op_size,u_int op_type,
811                           m_uint64_t *data)                           m_uint64_t *data)
812  {  {
# Line 846  static int gt_eth_access(cpu_mips_t *cpu Line 849  static int gt_eth_access(cpu_mips_t *cpu
849        /* ICR: Interrupt Cause Register */        /* ICR: Interrupt Cause Register */
850        case 0x84850:        case 0x84850:
851        case 0x88850:        case 0x88850:
852           if (op_type == MTS_READ)           if (op_type == MTS_READ) {
853              *data = port->icr;              *data = port->icr;
854           else           } else {
855              port->icr &= *data;              port->icr &= *data;
856                gt_eth_update_int_status(d,port);
857             }
858           break;           break;
859    
860        /* IMR: Interrupt Mask Register */        /* IMR: Interrupt Mask Register */
861        case 0x84858:        case 0x84858:
862        case 0x88858:        case 0x88858:
863           if (op_type == MTS_READ)           if (op_type == MTS_READ) {
864              *data = port->imr;              *data = port->imr;
865           else           } else {
866              port->imr = *data;              port->imr = *data;
867                gt_eth_update_int_status(d,port);
868             }
869           break;           break;
870    
871        /* PCR: Port Configuration Register */        /* PCR: Port Configuration Register */
# Line 1037  static int gt_eth_access(cpu_mips_t *cpu Line 1044  static int gt_eth_access(cpu_mips_t *cpu
1044           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
1045              cpu_log(cpu,"GT96100/ETH",              cpu_log(cpu,"GT96100/ETH",
1046                      "read access to unknown register 0x%x, pc=0x%llx\n",                      "read access to unknown register 0x%x, pc=0x%llx\n",
1047                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
1048           } else {           } else {
1049              cpu_log(cpu,"GT96100/ETH",              cpu_log(cpu,"GT96100/ETH",
1050                      "write access to unknown register 0x%x, value=0x%llx, "                      "write access to unknown register 0x%x, value=0x%llx, "
1051                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
1052           }           }
1053  #endif  #endif
1054     }     }
# Line 1055  static int gt_eth_access(cpu_mips_t *cpu Line 1062  static int gt_eth_access(cpu_mips_t *cpu
1062  /*  /*
1063   * dev_gt96100_access()   * dev_gt96100_access()
1064   */   */
1065  void *dev_gt96100_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_gt96100_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
1066                           u_int op_size,u_int op_type,m_uint64_t *data)                           u_int op_size,u_int op_type,m_uint64_t *data)
1067  {  {
1068     struct gt_data *gt_data = dev->priv_data;     struct gt_data *gt_data = dev->priv_data;
# Line 1195  void *dev_gt96100_access(cpu_mips_t *cpu Line 1202  void *dev_gt96100_access(cpu_mips_t *cpu
1202              if (gt_data->eth_ports[1].icr & GT_ICR_INT_SUM)              if (gt_data->eth_ports[1].icr & GT_ICR_INT_SUM)
1203                 *data |= GT_SCR_ETH1_SUM;                 *data |= GT_SCR_ETH1_SUM;
1204    
1205                gt_update_irq_status(gt_data);
1206              *data = swap32(*data);              *data = swap32(*data);
1207           }           }
1208           break;           break;
# Line 1221  void *dev_gt96100_access(cpu_mips_t *cpu Line 1229  void *dev_gt96100_access(cpu_mips_t *cpu
1229        default:        default:
1230           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
1231              cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"GT96100","read from addr 0x%x, pc=0x%llx\n",
1232                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
1233           } else {           } else {
1234              cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"GT96100","write to addr 0x%x, value=0x%llx, "
1235                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
1236           }           }
1237  #endif  #endif
1238     }     }
# Line 1772  int dev_gt64010_init(vm_instance_t *vm,c Line 1780  int dev_gt64010_init(vm_instance_t *vm,c
1780   *   *
1781   * Read a PCI register.   * Read a PCI register.
1782   */   */
1783  static m_uint32_t pci_gt64120_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_gt64120_read(cpu_gen_t *cpu,struct pci_device *dev,
1784                                     int reg)                                     int reg)
1785  {    {  
1786     switch (reg) {     switch (reg) {
# Line 1833  int dev_gt64120_init(vm_instance_t *vm,c Line 1841  int dev_gt64120_init(vm_instance_t *vm,c
1841   *   *
1842   * Read a PCI register.   * Read a PCI register.
1843   */   */
1844  static m_uint32_t pci_gt96100_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_gt96100_read(cpu_gen_t *cpu,struct pci_device *dev,
1845                                     int reg)                                     int reg)
1846  {    {  
1847     switch (reg) {     switch (reg) {
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