/[dynamips]/trunk/dev_gt.c
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Diff of /trunk/dev_gt.c

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upstream/dynamips-0.2.7-RC1/dev_gt.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC upstream/dynamips-0.2.7/dev_gt.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC
# Line 708  void *dev_gt64120_access(cpu_gen_t *cpu, Line 708  void *dev_gt64120_access(cpu_gen_t *cpu,
708     return NULL;     return NULL;
709  }  }
710    
711    /* Trigger/clear Ethernet interrupt if one or both port have pending events */
712    static void gt_eth_set_int_status(struct gt_data *d)
713    {
714       if ((d->eth_ports[0].icr & GT_ICR_INT_SUM) ||
715           (d->eth_ports[1].icr & GT_ICR_INT_SUM))
716          vm_set_irq(d->vm,d->eth_irq);
717       else
718          vm_clear_irq(d->vm,d->eth_irq);
719    }
720    
721  /* Update the Ethernet port interrupt status */  /* Update the Ethernet port interrupt status */
722  static void gt_eth_update_int_status(struct gt_data *d,struct eth_port *port)  static void gt_eth_update_int_status(struct gt_data *d,struct eth_port *port)
723  {  {
724     if (port->icr & GT_ICR_MASK)     if (port->icr & port->imr & GT_ICR_MASK) {
725        port->icr |= GT_ICR_INT_SUM;        port->icr |= GT_ICR_INT_SUM;
726       } else {
727          port->icr &= ~GT_ICR_INT_SUM;
728       }
729    
730     if (port->icr & port->imr & GT_ICR_MASK)     gt_eth_set_int_status(d);
       vm_set_irq(d->vm,d->eth_irq);  
731  }  }
732    
733  /* Read a MII register */  /* Read a MII register */
# Line 847  static int gt_eth_access(cpu_gen_t *cpu, Line 859  static int gt_eth_access(cpu_gen_t *cpu,
859        /* ICR: Interrupt Cause Register */        /* ICR: Interrupt Cause Register */
860        case 0x84850:        case 0x84850:
861        case 0x88850:        case 0x88850:
862           if (op_type == MTS_READ)           if (op_type == MTS_READ) {
863              *data = port->icr;              *data = port->icr;
864           else           } else {
865              port->icr &= *data;              port->icr &= *data;
866                gt_eth_update_int_status(d,port);
867             }
868           break;           break;
869    
870        /* IMR: Interrupt Mask Register */        /* IMR: Interrupt Mask Register */
871        case 0x84858:        case 0x84858:
872        case 0x88858:        case 0x88858:
873           if (op_type == MTS_READ)           if (op_type == MTS_READ) {
874              *data = port->imr;              *data = port->imr;
875           else           } else {
876              port->imr = *data;              port->imr = *data;
877                gt_eth_update_int_status(d,port);
878             }
879           break;           break;
880    
881        /* PCR: Port Configuration Register */        /* PCR: Port Configuration Register */
# Line 1196  void *dev_gt96100_access(cpu_gen_t *cpu, Line 1212  void *dev_gt96100_access(cpu_gen_t *cpu,
1212              if (gt_data->eth_ports[1].icr & GT_ICR_INT_SUM)              if (gt_data->eth_ports[1].icr & GT_ICR_INT_SUM)
1213                 *data |= GT_SCR_ETH1_SUM;                 *data |= GT_SCR_ETH1_SUM;
1214    
1215                gt_update_irq_status(gt_data);
1216              *data = swap32(*data);              *data = swap32(*data);
1217           }           }
1218           break;           break;
# Line 1282  static int gt_eth_handle_txqueue(struct Line 1299  static int gt_eth_handle_txqueue(struct
1299     tx_start = tx_current = port->tx_current[queue];     tx_start = tx_current = port->tx_current[queue];
1300    
1301     if (!tx_start)     if (!tx_start)
1302        goto done;        return(FALSE);
1303    
1304     ptxd = &txd0;     ptxd = &txd0;
1305     gt_eth_desc_read(d,tx_start,ptxd);     gt_eth_desc_read(d,tx_start,ptxd);
1306    
1307     /* If we don't own the first descriptor, we cannot transmit */     /* If we don't own the first descriptor, we cannot transmit */
1308     if (!(txd0.cmd_stat & GT_TXDESC_OWN))     if (!(txd0.cmd_stat & GT_TXDESC_OWN))
1309        goto done;        return(FALSE);
1310    
1311     /* Empty packet for now */     /* Empty packet for now */
1312     pkt_ptr = pkt;     pkt_ptr = pkt;
# Line 1362  static int gt_eth_handle_txqueue(struct Line 1379  static int gt_eth_handle_txqueue(struct
1379     else     else
1380        port->icr |= GT_ICR_TXBUFH;        port->icr |= GT_ICR_TXBUFH;
1381    
  done:  
1382     if (abort) {     if (abort) {
1383        /* TX underrun */        /* TX underrun */
1384        port->icr |= GT_ICR_TXUDR;        port->icr |= GT_ICR_TXUDR;
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