/[dynamips]/trunk/dev_c7200.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC4/dev_c7200.h revision 5 by dpavlin, Sat Oct 6 16:08:03 2007 UTC upstream/dynamips-0.2.7-RC3/dev_c7200.h revision 9 by dpavlin, Sat Oct 6 16:26:06 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Generic Cisco 7200 routines and definitions (EEPROM,...).   * Generic Cisco 7200 routines and definitions (EEPROM,...).
# Line 28  Line 28 
28  #include "net.h"  #include "net.h"
29  #include "device.h"  #include "device.h"
30  #include "pci_dev.h"  #include "pci_dev.h"
31  #include "nmc93c46.h"  #include "nmc93cX6.h"
32    #include "dev_mv64460.h"
33  #include "net_io.h"  #include "net_io.h"
34  #include "vm.h"  #include "vm.h"
35    
# Line 47  Line 48 
48  /* 6 slots + 1 I/O card */  /* 6 slots + 1 I/O card */
49  #define C7200_MAX_PA_BAYS  7  #define C7200_MAX_PA_BAYS  7
50    
51    /* C7200 Timer IRQ (virtual) */
52    #define C7200_VTIMER_IRQ 0
53    
54  /* C7200 DUART Interrupt */  /* C7200 DUART Interrupt */
55  #define C7200_DUART_IRQ  5  #define C7200_DUART_IRQ  5
56    
# Line 62  Line 66 
66  /* C7200 Error/OIR Interrupt */  /* C7200 Error/OIR Interrupt */
67  #define C7200_OIR_IRQ    6  #define C7200_OIR_IRQ    6
68    
69    /* Network IRQ */
70    #define C7200_NETIO_IRQ_BASE       32
71    #define C7200_NETIO_IRQ_PORT_BITS  3
72    #define C7200_NETIO_IRQ_PORT_MASK  ((1 << C7200_NETIO_IRQ_PORT_BITS) - 1)
73    #define C7200_NETIO_IRQ_PER_SLOT   (1 << C7200_NETIO_IRQ_PORT_BITS)
74    #define C7200_NETIO_IRQ_END        \
75        (C7200_NETIO_IRQ_BASE + (C7200_MAX_PA_BAYS * C7200_NETIO_IRQ_PER_SLOT) - 1)
76    
77  /* C7200 base ram limit (256 Mb) */  /* C7200 base ram limit (256 Mb) */
78  #define C7200_BASE_RAM_LIMIT  256  #define C7200_BASE_RAM_LIMIT  256
79    
80  /* C7200 common device addresses */  /* C7200 common device addresses */
81  #define C7200_GT64K_ADDR        0x14000000ULL  #define C7200_GT64K_ADDR         0x14000000ULL
82  #define C7200_GT64K_SEC_ADDR    0x15000000ULL  #define C7200_GT64K_SEC_ADDR     0x15000000ULL
83  #define C7200_BOOTFLASH_ADDR    0x1a000000ULL  #define C7200_BOOTFLASH_ADDR     0x1a000000ULL
84  #define C7200_NVRAM_ADDR        0x1e000000ULL  #define C7200_NVRAM_ADDR         0x1e000000ULL
85  #define C7200_NPEG1_NVRAM_ADDR  0x1e400000ULL  #define C7200_MPFPGA_ADDR        0x1e800000ULL
86  #define C7200_MPFPGA_ADDR       0x1e800000ULL  #define C7200_IOFPGA_ADDR        0x1e840000ULL
87  #define C7200_IOFPGA_ADDR       0x1e840000ULL  #define C7200_BITBUCKET_ADDR     0x1f000000ULL
88  #define C7200_BITBUCKET_ADDR    0x1f000000ULL  #define C7200_ROM_ADDR           0x1fc00000ULL
89  #define C7200_ROM_ADDR          0x1fc00000ULL  #define C7200_IOMEM_ADDR         0x20000000ULL
90  #define C7200_IOMEM_ADDR        0x20000000ULL  #define C7200_SRAM_ADDR          0x4b000000ULL
91  #define C7200_SRAM_ADDR         0x4b000000ULL  #define C7200_BSWAP_ADDR         0xc0000000ULL
92  #define C7200_PCI_IO_ADDR       0x100000000ULL  #define C7200_PCI_IO_ADDR        0x100000000ULL
93    
94    /* NPE-G1 specific info */
95    #define C7200_G1_NVRAM_ADDR      0x1e400000ULL
96    
97    /* NPE-G2 specific info */
98    #define C7200_G2_BSWAP_ADDR      0xc0000000ULL
99    #define C7200_G2_BOOTFLASH_ADDR  0xe8000000ULL
100    #define C7200_G2_PCI_IO_ADDR     0xf0000000ULL
101    #define C7200_G2_MV64460_ADDR    0xf1000000ULL
102    #define C7200_G2_MPFPGA_ADDR     0xfe000000ULL
103    #define C7200_G2_IOFPGA_ADDR     0xfe040000ULL
104    #define C7200_G2_NVRAM_ADDR      0xff000000ULL
105    #define C7200_G2_ROM_ADDR        0xfff00000ULL
106    
107    /* NVRAM size for NPE-G2: 2 Mb */
108    #define C7200_G2_NVRAM_SIZE      (2 * 1048576)
109    
110  /* Reserved space for ROM in NVRAM */  /* Reserved space for ROM in NVRAM */
111  #define C7200_NVRAM_ROM_RES_SIZE  2048  #define C7200_NVRAM_ROM_RES_SIZE  2048
# Line 88  Line 116 
116  /* C7200 ELF Platform ID */  /* C7200 ELF Platform ID */
117  #define C7200_ELF_MACHINE_ID  0x19  #define C7200_ELF_MACHINE_ID  0x19
118    
119    /* NPE families */
120    enum {
121       C7200_NPE_FAMILY_MIPS = 0,
122       C7200_NPE_FAMILY_PPC,
123    };
124    
125  /* C7200 router */  /* C7200 router */
126  typedef struct c7200_router c7200_t;  typedef struct c7200_router c7200_t;
127    
# Line 143  struct c7200_pa_bay { Line 177  struct c7200_pa_bay {
177  /* C7200 NPE Driver */  /* C7200 NPE Driver */
178  struct c7200_npe_driver {  struct c7200_npe_driver {
179     char *npe_type;     char *npe_type;
180       int npe_family;
181     c7200_npe_init_fn npe_init;     c7200_npe_init_fn npe_init;
182     int max_ram_size;     int max_ram_size;
183     int supported;     int supported;
184     m_uint64_t nvram_addr;     m_uint64_t nvram_addr;
185       int iocard_required;
186     int clpd6729_pci_bus;     int clpd6729_pci_bus;
187     int clpd6729_pci_dev;     int clpd6729_pci_dev;
188     int dec21140_pci_bus;     int dec21140_pci_bus;
# Line 163  struct c7200_router { Line 199  struct c7200_router {
199     /* Associated VM instance */     /* Associated VM instance */
200     vm_instance_t *vm;     vm_instance_t *vm;
201    
202       /* MV64460 device for NPE-G2 */
203       struct mv64460_data *mv64460_sysctr;
204    
205       /* Midplane FPGA */
206       struct c7200_mpfpga_data *mpfpga_data;
207    
208     /* NPE and PA information */     /* NPE and PA information */
209     struct c7200_npe_driver *npe_driver;     struct c7200_npe_driver *npe_driver;
210     struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS];     struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS];
# Line 175  struct c7200_router { Line 217  struct c7200_router {
217     /* Midplane EEPROM can be modified to change the chassis MAC address... */     /* Midplane EEPROM can be modified to change the chassis MAC address... */
218     struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom;     struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom;
219    
220     struct nmc93c46_group sys_eeprom_g1;    /* EEPROMs for CPU and Midplane */     struct nmc93cX6_group sys_eeprom_g1;    /* EEPROMs for CPU and Midplane */
221     struct nmc93c46_group sys_eeprom_g2;    /* EEPROM for PEM */     struct nmc93cX6_group sys_eeprom_g2;    /* EEPROM for PEM */
222     struct nmc93c46_group pa_eeprom_g1;     /* EEPROMs for bays 0, 1, 3, 4 */     struct nmc93cX6_group pa_eeprom_g1;     /* EEPROMs for bays 0, 1, 3, 4 */
223     struct nmc93c46_group pa_eeprom_g2;     /* EEPROMs for bays 2, 5, 6 */     struct nmc93cX6_group pa_eeprom_g2;     /* EEPROMs for bays 2, 5, 6 */
224  };  };
225    
226  /* Initialize EEPROM groups */  /* Initialize EEPROM groups */
# Line 199  void c7200_save_config(c7200_t *router,F Line 241  void c7200_save_config(c7200_t *router,F
241  /* Save configurations of all C7200 instances */  /* Save configurations of all C7200 instances */
242  void c7200_save_config_all(FILE *fd);  void c7200_save_config_all(FILE *fd);
243    
244    /* Get network IRQ for specified slot/port */
245    u_int c7200_net_irq_for_slot_port(u_int slot,u_int port);
246    
247  /* Set PA EEPROM definition */  /* Set PA EEPROM definition */
248  int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay,  int c7200_pa_set_eeprom(c7200_t *router,u_int pa_bay,
249                          const struct cisco_eeprom *eeprom);                          const struct cisco_eeprom *eeprom);
# Line 295  void c7200_show_hardware(c7200_t *router Line 340  void c7200_show_hardware(c7200_t *router
340  /* Initialize default parameters for a C7200 */  /* Initialize default parameters for a C7200 */
341  void c7200_init_defaults(c7200_t *router);  void c7200_init_defaults(c7200_t *router);
342    
 /* Initialize the C7200 Platform */  
 int c7200_init_platform(c7200_t *router);  
   
 /* Boot the IOS image */  
 int c7200_boot_ios(c7200_t *router);  
   
343  /* Initialize a Cisco 7200 instance */  /* Initialize a Cisco 7200 instance */
344  int c7200_init_instance(c7200_t *router);  int c7200_init_instance(c7200_t *router);
345    
# Line 319  int c7200_pa_stop_online(c7200_t *router Line 358  int c7200_pa_stop_online(c7200_t *router
358  /* dev_c7200_iofpga_init() */  /* dev_c7200_iofpga_init() */
359  int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);  int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);
360    
 /* dev_mpfpga_init() */  
 int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);  
   
361  /* PA drivers */  /* PA drivers */
362  extern struct c7200_pa_driver dev_c7200_io_fe_driver;  extern struct c7200_pa_driver dev_c7200_iocard_fe_driver;
363    extern struct c7200_pa_driver dev_c7200_iocard_2fe_driver;
364    extern struct c7200_pa_driver dev_c7200_iocard_ge_e_driver;
365  extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver;  extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver;
366    extern struct c7200_pa_driver dev_c7200_pa_2fe_tx_driver;
367    extern struct c7200_pa_driver dev_c7200_pa_ge_driver;
368  extern struct c7200_pa_driver dev_c7200_pa_4e_driver;  extern struct c7200_pa_driver dev_c7200_pa_4e_driver;
369  extern struct c7200_pa_driver dev_c7200_pa_8e_driver;  extern struct c7200_pa_driver dev_c7200_pa_8e_driver;
370  extern struct c7200_pa_driver dev_c7200_pa_4t_driver;  extern struct c7200_pa_driver dev_c7200_pa_4t_driver;
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