/[dynamips]/trunk/dev_c7200.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_c7200.h revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c7200.h revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Generic Cisco 7200 routines and definitions (EEPROM,...).   * Generic Cisco 7200 routines and definitions (EEPROM,...).
# Line 29  Line 29 
29  #include "device.h"  #include "device.h"
30  #include "pci_dev.h"  #include "pci_dev.h"
31  #include "nmc93c46.h"  #include "nmc93c46.h"
32    #include "dev_mv64460.h"
33  #include "net_io.h"  #include "net_io.h"
34  #include "vm.h"  #include "vm.h"
35    
# Line 47  Line 48 
48  /* 6 slots + 1 I/O card */  /* 6 slots + 1 I/O card */
49  #define C7200_MAX_PA_BAYS  7  #define C7200_MAX_PA_BAYS  7
50    
51    /* C7200 Timer IRQ (virtual) */
52    #define C7200_VTIMER_IRQ 0
53    
54  /* C7200 DUART Interrupt */  /* C7200 DUART Interrupt */
55  #define C7200_DUART_IRQ  5  #define C7200_DUART_IRQ  5
56    
# Line 66  Line 70 
70  #define C7200_BASE_RAM_LIMIT  256  #define C7200_BASE_RAM_LIMIT  256
71    
72  /* C7200 common device addresses */  /* C7200 common device addresses */
73  #define C7200_GT64K_ADDR        0x14000000ULL  #define C7200_GT64K_ADDR         0x14000000ULL
74  #define C7200_GT64K_SEC_ADDR    0x15000000ULL  #define C7200_GT64K_SEC_ADDR     0x15000000ULL
75  #define C7200_BOOTFLASH_ADDR    0x1a000000ULL  #define C7200_BOOTFLASH_ADDR     0x1a000000ULL
76  #define C7200_NVRAM_ADDR        0x1e000000ULL  #define C7200_NVRAM_ADDR         0x1e000000ULL
77  #define C7200_NPEG1_NVRAM_ADDR  0x1e400000ULL  #define C7200_MPFPGA_ADDR        0x1e800000ULL
78  #define C7200_MPFPGA_ADDR       0x1e800000ULL  #define C7200_IOFPGA_ADDR        0x1e840000ULL
79  #define C7200_IOFPGA_ADDR       0x1e840000ULL  #define C7200_BITBUCKET_ADDR     0x1f000000ULL
80  #define C7200_BITBUCKET_ADDR    0x1f000000ULL  #define C7200_ROM_ADDR           0x1fc00000ULL
81  #define C7200_ROM_ADDR          0x1fc00000ULL  #define C7200_IOMEM_ADDR         0x20000000ULL
82  #define C7200_IOMEM_ADDR        0x20000000ULL  #define C7200_SRAM_ADDR          0x4b000000ULL
83  #define C7200_SRAM_ADDR         0x4b000000ULL  #define C7200_BSWAP_ADDR         0xc0000000ULL
84  #define C7200_PCI_IO_ADDR       0x100000000ULL  #define C7200_PCI_IO_ADDR        0x100000000ULL
85    
86    /* NPE-G1 specific info */
87    #define C7200_G1_NVRAM_ADDR      0x1e400000ULL
88    
89    /* NPE-G2 specific info */
90    #define C7200_G2_BSWAP_ADDR      0xc0000000ULL
91    #define C7200_G2_BOOTFLASH_ADDR  0xe8000000ULL
92    #define C7200_G2_PCI_IO_ADDR     0xf0000000ULL
93    #define C7200_G2_MV64460_ADDR    0xf1000000ULL
94    #define C7200_G2_MPFPGA_ADDR     0xfe000000ULL
95    #define C7200_G2_IOFPGA_ADDR     0xfe040000ULL
96    #define C7200_G2_NVRAM_ADDR      0xff000000ULL
97    #define C7200_G2_ROM_ADDR        0xfff00000ULL
98    
99    /* NVRAM size for NPE-G2: 2 Mb */
100    #define C7200_G2_NVRAM_SIZE      (2 * 1048576)
101    
102  /* Reserved space for ROM in NVRAM */  /* Reserved space for ROM in NVRAM */
103  #define C7200_NVRAM_ROM_RES_SIZE  2048  #define C7200_NVRAM_ROM_RES_SIZE  2048
# Line 88  Line 108 
108  /* C7200 ELF Platform ID */  /* C7200 ELF Platform ID */
109  #define C7200_ELF_MACHINE_ID  0x19  #define C7200_ELF_MACHINE_ID  0x19
110    
111    /* NPE families */
112    enum {
113       C7200_NPE_FAMILY_MIPS = 0,
114       C7200_NPE_FAMILY_PPC,
115    };
116    
117  /* C7200 router */  /* C7200 router */
118  typedef struct c7200_router c7200_t;  typedef struct c7200_router c7200_t;
119    
# Line 143  struct c7200_pa_bay { Line 169  struct c7200_pa_bay {
169  /* C7200 NPE Driver */  /* C7200 NPE Driver */
170  struct c7200_npe_driver {  struct c7200_npe_driver {
171     char *npe_type;     char *npe_type;
172       int npe_family;
173     c7200_npe_init_fn npe_init;     c7200_npe_init_fn npe_init;
174     int max_ram_size;     int max_ram_size;
175     int supported;     int supported;
176     m_uint64_t nvram_addr;     m_uint64_t nvram_addr;
177       int iocard_required;
178     int clpd6729_pci_bus;     int clpd6729_pci_bus;
179     int clpd6729_pci_dev;     int clpd6729_pci_dev;
180     int dec21140_pci_bus;     int dec21140_pci_bus;
# Line 163  struct c7200_router { Line 191  struct c7200_router {
191     /* Associated VM instance */     /* Associated VM instance */
192     vm_instance_t *vm;     vm_instance_t *vm;
193    
194       /* MV64460 device for NPE-G2 */
195       struct mv64460_data *mv64460_sysctr;
196    
197     /* NPE and PA information */     /* NPE and PA information */
198     struct c7200_npe_driver *npe_driver;     struct c7200_npe_driver *npe_driver;
199     struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS];     struct c7200_pa_bay pa_bay[C7200_MAX_PA_BAYS];
# Line 295  void c7200_show_hardware(c7200_t *router Line 326  void c7200_show_hardware(c7200_t *router
326  /* Initialize default parameters for a C7200 */  /* Initialize default parameters for a C7200 */
327  void c7200_init_defaults(c7200_t *router);  void c7200_init_defaults(c7200_t *router);
328    
 /* Initialize the C7200 Platform */  
 int c7200_init_platform(c7200_t *router);  
   
 /* Boot the IOS image */  
 int c7200_boot_ios(c7200_t *router);  
   
329  /* Initialize a Cisco 7200 instance */  /* Initialize a Cisco 7200 instance */
330  int c7200_init_instance(c7200_t *router);  int c7200_init_instance(c7200_t *router);
331    
# Line 323  int dev_c7200_iofpga_init(c7200_t *route Line 348  int dev_c7200_iofpga_init(c7200_t *route
348  int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);  int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);
349    
350  /* PA drivers */  /* PA drivers */
351  extern struct c7200_pa_driver dev_c7200_io_fe_driver;  extern struct c7200_pa_driver dev_c7200_iocard_fe_driver;
352    extern struct c7200_pa_driver dev_c7200_iocard_2fe_driver;
353    extern struct c7200_pa_driver dev_c7200_iocard_ge_e_driver;
354  extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver;  extern struct c7200_pa_driver dev_c7200_pa_fe_tx_driver;
355    extern struct c7200_pa_driver dev_c7200_pa_2fe_tx_driver;
356    extern struct c7200_pa_driver dev_c7200_pa_ge_driver;
357  extern struct c7200_pa_driver dev_c7200_pa_4e_driver;  extern struct c7200_pa_driver dev_c7200_pa_4e_driver;
358  extern struct c7200_pa_driver dev_c7200_pa_8e_driver;  extern struct c7200_pa_driver dev_c7200_pa_8e_driver;
359  extern struct c7200_pa_driver dev_c7200_pa_4t_driver;  extern struct c7200_pa_driver dev_c7200_pa_4t_driver;

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