/[dynamips]/trunk/dev_c3745_iofpga.c
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upstream/dynamips-0.2.7/dev_c3745_iofpga.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/dev_c3745_iofpga.c revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 3745 simulation platform.   * Cisco 3745 simulation platform.
3   * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
  *  
  * This is very similar to c2691.  
4   */   */
5    
6  #include <stdio.h>  #include <stdio.h>
# Line 81  struct c3745_iofpga_data { Line 79  struct c3745_iofpga_data {
79    
80     /* EEPROM select */     /* EEPROM select */
81     u_int eeprom_select;     u_int eeprom_select;
82    
83       /* WIC select */
84       u_int wic_select;
85       u_int wic_cmd_pos;
86       u_int wic_cmd_valid;
87       m_uint16_t wic_cmd[2];
88  };  };
89    
90  /* Motherboard EEPROM definition */  /* Motherboard EEPROM definition */
# Line 103  static const struct nmc93cX6_eeprom_def Line 107  static const struct nmc93cX6_eeprom_def
107    
108  /* System EEPROM group */  /* System EEPROM group */
109  static const struct nmc93cX6_group eeprom_sys_group = {  static const struct nmc93cX6_group eeprom_sys_group = {
110     EEPROM_TYPE_NMC93C46, 3, 0, "System EEPROM", 0,     EEPROM_TYPE_NMC93C46, 3, 0,
111       EEPROM_DORD_NORMAL,
112       EEPROM_DOUT_HIGH,
113       EEPROM_DEBUG_DISABLED,
114       "System EEPROM",
115     { &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def },     { &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def },
116  };  };
117    
# Line 115  static const struct nmc93cX6_eeprom_def Line 123  static const struct nmc93cX6_eeprom_def
123    
124  /* NM EEPROM */  /* NM EEPROM */
125  static const struct nmc93cX6_group eeprom_nm_group = {  static const struct nmc93cX6_group eeprom_nm_group = {
126     EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def },     EEPROM_TYPE_NMC93C46, 1, 0,
127       EEPROM_DORD_NORMAL,
128       EEPROM_DOUT_HIGH,
129       EEPROM_DEBUG_DISABLED,
130       "NM EEPROM",
131       { &eeprom_nm_def },
132  };  };
133    
134  /* Update network interrupt status */  /* Update network interrupt status */
# Line 158  void dev_c3745_iofpga_net_clear_irq(stru Line 171  void dev_c3745_iofpga_net_clear_irq(stru
171     dev_c3745_iofpga_net_update_irq(d);     dev_c3745_iofpga_net_update_irq(d);
172  }  }
173    
174    /* Read a WIC EEPROM */
175    static m_uint16_t dev_c3745_read_wic_eeprom(struct c3745_iofpga_data *d)
176    {  
177       struct cisco_eeprom *eeprom;
178       u_int wic_port;
179       u_int eeprom_offset;
180       m_uint8_t val[2];
181    
182       switch(d->wic_select) {
183          case 0x1700:
184             wic_port = 0x10;
185             break;
186          case 0x1D00:
187             wic_port = 0x20;
188             break;
189          case 0x3500:
190             wic_port = 0x30;
191             break;
192          default:
193             wic_port = 0;
194       }
195    
196       /* No WIC in slot or no EEPROM: fake an empty EEPROM */
197       if (!wic_port || !(eeprom = vm_slot_get_eeprom(d->router->vm,0,wic_port)))
198          return(0xFFFF);
199    
200       /* EEPROM offset is in the lowest 6 bits */
201       eeprom_offset = d->wic_cmd[0] & 0x3F;
202    
203       cisco_eeprom_get_byte(eeprom,eeprom_offset,&val[0]);
204       cisco_eeprom_get_byte(eeprom,eeprom_offset+1,&val[1]);
205    
206       return(((m_uint16_t)val[0] << 8) | val[1]);
207    }
208    
209  /*  /*
210   * dev_c3745_iofpga_access()   * dev_c3745_iofpga_access()
211   */   */
# Line 171  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 219  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
219    
220     if (op_type == MTS_READ)     if (op_type == MTS_READ)
221        *data = 0x0;        *data = 0x0;
222      
223  #if DEBUG_ACCESS  #if DEBUG_ACCESS
224     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
225        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",        cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
# Line 323  dev_c3745_iofpga_access(cpu_gen_t *cpu,s Line 371  dev_c3745_iofpga_access(cpu_gen_t *cpu,s
371           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
372              *data = 0xFFFF;              *data = 0xFFFF;
373                            
374              if (c3745_nm_check_eeprom(d->router,1))              if (vm_slot_get_card_ptr(d->router->vm,1))
375                 *data &= ~0x0100;                 *data &= ~0x0100;
376    
377              if (c3745_nm_check_eeprom(d->router,2))              if (vm_slot_get_card_ptr(d->router->vm,2))
378                 *data &= ~0x0001;                 *data &= ~0x0001;
379    
380              if (c3745_nm_check_eeprom(d->router,3))              if (vm_slot_get_card_ptr(d->router->vm,3))
381                 *data &= ~0x1000;                 *data &= ~0x1000;
382    
383              if (c3745_nm_check_eeprom(d->router,4))              if (vm_slot_get_card_ptr(d->router->vm,4))
384                 *data &= ~0x0010;                 *data &= ~0x0010;
385           }           }
386           break;           break;
387    
388        /* VWIC/WIC related */        /*
389           * VWIC/WIC related
390           * Bits 0-2: WIC presence
391           */
392        case 0x100004:        case 0x100004:
393             if (op_type == MTS_READ) {
394               *data = 0xFFFF;
395    
396               /* check WIC 0 */
397                if (vm_slot_check_eeprom(d->router->vm,0,0x10))
398                   *data &= ~0x01;
399    
400                /* check WIC 1 */
401                if (vm_slot_check_eeprom(d->router->vm,0,0x20))
402                   *data &= ~0x02;
403    
404                /* check WIC 2 */
405                if (vm_slot_check_eeprom(d->router->vm,0,0x30))
406                   *data &= ~0x04;
407             } else {
408                d->wic_select = *data;
409             }
410             break;
411    
412        case 0x100006:        case 0x100006:
       case 0x100008:  
413           if (op_type == MTS_READ)           if (op_type == MTS_READ)
414              *data = 0xFFFF;              *data = 0x0004;
415             break;
416    
417          case 0x100008:
418             if (op_type == MTS_READ) {
419                if (d->wic_cmd_valid) {
420                   *data = dev_c3745_read_wic_eeprom(d);
421                   d->wic_cmd_valid = FALSE;
422                } else {
423                   *data = 0xFFFF;
424                }
425             } else {
426                /*
427                 * Store the EEPROM command (in 2 words).
428                 *
429                 * For a read, we have:
430                 *    Word 0: 0x180 (nmc93c46 READ) + offset (6-bits).
431                 *    Word 1: 0 (no data).
432                 */
433                d->wic_cmd[d->wic_cmd_pos++] = *data;
434                
435                if (d->wic_cmd_pos == 2) {
436                   d->wic_cmd_pos = 0;
437                   d->wic_cmd_valid = TRUE;
438                }
439             }
440           break;           break;
441    
442  #if DEBUG_UNKNOWN  #if DEBUG_UNKNOWN
# Line 380  void c3745_init_eeprom_groups(c3745_t *r Line 474  void c3745_init_eeprom_groups(c3745_t *r
474     /* EEPROMs for Network Modules */     /* EEPROMs for Network Modules */
475     for(i=1;i<=4;i++) {     for(i=1;i<=4;i++) {
476        router->nm_eeprom_group[i-1] = eeprom_nm_group;        router->nm_eeprom_group[i-1] = eeprom_nm_group;
477        router->nm_eeprom_group[i-1].eeprom[0] = &router->nm_bay[i].eeprom;        router->nm_eeprom_group[i-1].eeprom[0] = NULL;
478     }     }
479  }  }
480    

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