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#include "memory.h" |
#include "memory.h" |
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#include "device.h" |
#include "device.h" |
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#include "dev_vtty.h" |
#include "dev_vtty.h" |
24 |
#include "nmc93c46.h" |
#include "nmc93cX6.h" |
25 |
#include "dev_c3745.h" |
#include "dev_c3745.h" |
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27 |
/* Debugging flags */ |
/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
30 |
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#define DEBUG_NET_IRQ 0 |
31 |
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32 |
/* Definitions for Motherboard EEPROM (0x00) */ |
/* Definitions for Motherboard EEPROM (0x00) */ |
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#define EEPROM_MB_DOUT 3 |
#define EEPROM_MB_DOUT 3 |
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#define EEPROM_NM_CLK 2 |
#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
#define EEPROM_NM_CS 4 |
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56 |
#define C3745_NET_IRQ_CLEARING_DELAY 16 |
/* Network IRQ distribution */ |
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struct net_irq_distrib { |
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u_int reg; |
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u_int offset; |
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}; |
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62 |
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static struct net_irq_distrib net_irq_dist[C3745_MAX_NM_BAYS] = { |
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{ 0, 0 }, /* Slot 0: reg 0x20, 0x00XX */ |
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{ 1, 0 }, /* Slot 1: reg 0x22, 0x000X */ |
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{ 1, 4 }, /* Slot 2: reg 0x22, 0x00X0 */ |
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{ 1, 8 }, /* Slot 3: reg 0x22, 0x0X00 */ |
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{ 1, 12 }, /* Slot 4: reg 0x22, 0xX000 */ |
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}; |
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/* IO FPGA structure */ |
/* IO FPGA structure */ |
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struct iofpga_data { |
struct c3745_iofpga_data { |
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vm_obj_t vm_obj; |
vm_obj_t vm_obj; |
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struct vdevice dev; |
struct vdevice dev; |
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c3745_t *router; |
c3745_t *router; |
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/* |
/* Network IRQ status */ |
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* Used to introduce a "delay" before clearing the network interrupt |
m_uint16_t net_irq_status[2]; |
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* on 3620/3640 platforms. Added due to a packet loss when using an |
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* Ethernet NM on these platforms. |
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* |
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* Anyway, we should rely on the device information with appropriate IRQ |
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* routing. |
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*/ |
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int net_irq_clearing_count; |
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/* Interrupt mask */ |
/* Interrupt mask */ |
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m_uint16_t intr_mask,io_mask2; |
m_uint16_t intr_mask,io_mask2; |
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}; |
}; |
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86 |
/* Motherboard EEPROM definition */ |
/* Motherboard EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mb_def = { |
static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
}; |
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/* I/O board EEPROM definition */ |
/* I/O board EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_io_def = { |
static const struct nmc93cX6_eeprom_def eeprom_io_def = { |
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EEPROM_IO_CLK, EEPROM_IO_CS, |
EEPROM_IO_CLK, EEPROM_IO_CS, |
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EEPROM_IO_DIN, EEPROM_IO_DOUT, |
EEPROM_IO_DIN, EEPROM_IO_DOUT, |
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}; |
}; |
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/* Midplane EEPROM definition */ |
/* Midplane EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_mp_def = { |
static const struct nmc93cX6_eeprom_def eeprom_mp_def = { |
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EEPROM_MP_CLK, EEPROM_MP_CS, |
EEPROM_MP_CLK, EEPROM_MP_CS, |
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EEPROM_MP_DIN, EEPROM_MP_DOUT, |
EEPROM_MP_DIN, EEPROM_MP_DOUT, |
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}; |
}; |
103 |
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104 |
/* System EEPROM group */ |
/* System EEPROM group */ |
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static const struct nmc93c46_group eeprom_sys_group = { |
static const struct nmc93cX6_group eeprom_sys_group = { |
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3, 0, "System EEPROM", 0, |
EEPROM_TYPE_NMC93C46, 3, 0, "System EEPROM", 0, |
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{ &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def }, |
{ &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def }, |
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}; |
}; |
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/* NM EEPROM definition */ |
/* NM EEPROM definition */ |
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static const struct nmc93c46_eeprom_def eeprom_nm_def = { |
static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
}; |
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/* NM EEPROM */ |
/* NM EEPROM */ |
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static const struct nmc93c46_group eeprom_nm_group = { |
static const struct nmc93cX6_group eeprom_nm_group = { |
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1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
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}; |
}; |
120 |
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121 |
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/* Update network interrupt status */ |
122 |
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static inline void dev_c3745_iofpga_net_update_irq(struct c3745_iofpga_data *d) |
123 |
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{ |
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if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) { |
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vm_set_irq(d->router->vm,C3745_NETIO_IRQ); |
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} else { |
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vm_clear_irq(d->router->vm,C3745_NETIO_IRQ); |
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} |
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} |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c3745_iofpga_net_set_irq(struct c3745_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
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dev_c3745_iofpga_net_update_irq(d); |
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} |
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/* Clear a Network IRQ for the specified slot/port */ |
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void dev_c3745_iofpga_net_clear_irq(struct c3745_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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152 |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port)); |
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dev_c3745_iofpga_net_update_irq(d); |
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} |
160 |
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/* |
/* |
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* dev_c3745_iofpga_access() |
* dev_c3745_iofpga_access() |
163 |
*/ |
*/ |
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m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
167 |
m_uint64_t *data) |
m_uint64_t *data) |
168 |
{ |
{ |
169 |
struct iofpga_data *d = dev->priv_data; |
struct c3745_iofpga_data *d = dev->priv_data; |
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u_int slot; |
u_int slot; |
171 |
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
237 |
/* System EEPROMs */ |
/* System EEPROMs */ |
238 |
case 0x00000e: |
case 0x00000e: |
239 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
240 |
nmc93c46_write(&d->router->sys_eeprom_group,(u_int)(*data)); |
nmc93cX6_write(&d->router->sys_eeprom_group,(u_int)(*data)); |
241 |
else |
else |
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*data = nmc93c46_read(&d->router->sys_eeprom_group); |
*data = nmc93cX6_read(&d->router->sys_eeprom_group); |
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break; |
break; |
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/* |
/* |
251 |
*/ |
*/ |
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case 0x000020: |
case 0x000020: |
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
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*data = 0xFFFE; |
*data = d->net_irq_status[0]; |
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break; |
break; |
256 |
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/* |
/* |
264 |
*/ |
*/ |
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case 0x000022: |
case 0x000022: |
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if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
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*data = 0x0000; |
*data = d->net_irq_status[1]; |
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vm_clear_irq(d->router->vm,C3745_NETIO_IRQ); |
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break; |
break; |
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/* |
/* |
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slot = (offset - 0x000040) >> 1; |
slot = (offset - 0x000040) >> 1; |
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296 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
297 |
nmc93c46_write(&d->router->nm_eeprom_group[slot],(u_int)(*data)); |
nmc93cX6_write(&d->router->nm_eeprom_group[slot],(u_int)(*data)); |
298 |
else |
else |
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*data = nmc93c46_read(&d->router->nm_eeprom_group[slot]); |
*data = nmc93cX6_read(&d->router->nm_eeprom_group[slot]); |
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break; |
break; |
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/* AIM slot 0 EEPROM */ |
/* AIM slot 0 EEPROM */ |
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} |
} |
386 |
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/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |
388 |
void dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
static void |
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dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct c3745_iofpga_data *d) |
390 |
{ |
{ |
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if (d != NULL) { |
if (d != NULL) { |
392 |
/* Remove the device */ |
/* Remove the device */ |
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int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len) |
int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len) |
404 |
{ |
{ |
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vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
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struct iofpga_data *d; |
struct c3745_iofpga_data *d; |
407 |
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408 |
/* Allocate private data structure */ |
/* Allocate private data structure */ |
409 |
if (!(d = malloc(sizeof(*d)))) { |
if (!(d = malloc(sizeof(*d)))) { |
413 |
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memset(d,0,sizeof(*d)); |
memset(d,0,sizeof(*d)); |
415 |
d->router = router; |
d->router = router; |
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d->net_irq_status[0] = 0xFFFF; |
417 |
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d->net_irq_status[1] = 0xFFFF; |
418 |
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419 |
vm_object_init(&d->vm_obj); |
vm_object_init(&d->vm_obj); |
420 |
d->vm_obj.name = "io_fpga"; |
d->vm_obj.name = "io_fpga"; |